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White Rabbit Calibration
Commit 3b435d56 authored by Peter Jansweijer's avatar Peter Jansweijer
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moved on to wrpc v4.0 => clb_abs_calibration works (with standard wrpc-sw-v4.0… 

moved on to wrpc v4.0 => clb_abs_calibration works (with standard wrpc-sw-v4.0 tuned for the CLB, no abs cal PPSi yet!)
parent 6c07897f
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Showing with 6686 additions and 7114 deletions
.gitmodules
View file @ 3b435d56
[submodule "hdl/wr-cores"]
path = hdl/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "sw/embedded/wrpc-sw"]
path = sw/embedded/wrpc-sw
url = git@ohwr.org:hdl-core-lib/wr-cores/wrpc-sw
hdl/clb_abs_calibration/clb_abs_calibration.ews/project.xml
View file @ 3b435d56
......@@ -20,7 +20,7 @@
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_peter/fw/CLBv2_Design/clb/clb.ews/html/index.htm" name="Index"/>
</section>
<section name="Markers">
<key type="string" value="design:Toplevel:&lt;Internal>" name="CurrentPath"/>
<key type="string" value="design:Toplevel:&lt;Internal>/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c53c2dcc02544c0e1bc3b126856/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c533e9b92250ae0e1bce243a135" name="CurrentPath"/>
<key type="string" value="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c146f9025cc61e8b58876eb73" name="HdlOutputObject"/>
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_mesfin/fw/CLBv2_Design/clb_wrpc/top/clb_wrpc_top_tb.vhd" name="HdlOutputFile"/>
</section>
......
hdl/clb_abs_calibration/sim/VSim_Functional.tcl
View file @ 3b435d56
......@@ -40,9 +40,9 @@ if { $sim_task == "load"} {
source VSim_Current_Revision.tcl
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\WRPC_simu\\wrc.elf"]"
puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\wrpc-spec-sw-simu\\wrc.elf"]"
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\wrpc-sw\\wrc.elf"]"
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\precompiled\\WRPC_simu\\wrc.elf"]"
puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\precompiled\\wrpc-sw-simu\\wrc.elf"]"
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\precompiled\\wrpc-sw\\wrc.elf"]"
# !!! Note !!!: Don't forget to compile the software (elf file) for simulation (avoid printf etc. to speed up simulation time)
# !!! Note !!!: The double \\ are there since the DOS command below needs backslashes and a single backslash is seen as a switch in tcl
......@@ -74,11 +74,12 @@ if { $sim_task == "load"} {
+nowarn151 \
+nowarn8684 \
-G/clb_top_tb/g_simulation=$g_simulation \
-G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/g_must_have_init_file=true \
-G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/g_init_file=lm32_wrpc_memory.ldr \
-t ps -L unisim -lib work work.clb_top_tb
# -G/clb_top_tb/u2/tx_data_swap=false \
# -G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/g_must_have_init_file=true \
# -G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/g_init_file=lm32_wrpc_memory.ldr \
do wave.tcl
......
hdl/clb_abs_calibration/syn/Convert_ShoppingList_to_do_input_file_list.py 0 → 100644
View file @ 3b435d56
#!/usr/bin/python
"""
Convert_ShoppingList_to_do_input_file_list.py: Converts
"hdlmake list-files > shoppinglist" file into do_input_file_list.cmd
-------------------------------------------------------------------------------
Copyright (C) 2017 Peter Jansweijer
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>
-------------------------------------------------------------------------------
Usage:
Convert_ShoppingList_to_do_input_file_list.py
Convert_ShoppingList_to_do_input_file_list.py -h | --help
<name> name of the hdlmake output file that lists al files needed
in the project (the shopplinlist)
-o <name> optional output file name, default: "do_input_file_list.cmd"
Options:
-h --help Show this screen.
"""
import os
import sys
import datetime
import pdb
############################################################################
def add_verilog(cmd_file, line):
cmd_file.write("@echo verilog work " + line + "\" >> %PrjFile%\n")
cmd_file.write("@echo ^<file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VERILOG\"^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"BehavioralSimulation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^</file^> >> %XISEFile%\n")
return()
def add_vhdl(cmd_file, line):
cmd_file.write("@echo vhdl work " + line + "\" >> %PrjFile%\n")
cmd_file.write("@echo ^<file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VHDL\"^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"BehavioralSimulation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^</file^> >> %XISEFile%\n")
return()
############################################################################
#
# If run from commandline, we can test the library
#
"""
Usage:
Convert_ShoppingList_to_do_input_file_list.py
Convert_ShoppingList_to_do_input_file_list.py -h | --help
<name> name of the hdlmake output file that lists al files needed
in the project (the shopplinlist)
-o <name> optional output file name, default: "do_input_file_list.cmd"
Options:
-h --help Show this screen.
"""
if __name__ == "__main__":
import argparse
parser = argparse.ArgumentParser()
parser.add_argument("name", help="shopping list")
parser.add_argument("-oname", default="do_input_file_list.cmd", help="outfut file name ")
args = parser.parse_args()
name = args.name
oname = args.oname
if os.path.isfile(name) == True:
hdlmakelist = open(name,"r")
if os.path.isfile(oname) == True:
os.remove(oname)
xlx_cmd_file = open(oname,"w")
timestamp = datetime.datetime.now() #micro secounds timing
xlx_cmd_file.write("rem do_input_file_list.cmd PeterJ " + timestamp.strftime("%d %b %Y") + ", AutoGenerated by Convert_ShoppingList_to_do_input_file_list.py \n")
xlx_cmd_file.write("rem Prepares a .prj file for input to XST\n")
xlx_cmd_file.write("@prompt $$$s\n")
xlx_cmd_file.write("\n")
xlx_cmd_file.write("set lst_LM32_Sources=%1%\n")
xlx_cmd_file.write("set lst_WRPC_Sources=%2%\n")
xlx_cmd_file.write("set lst_Arch1Path=%3%\n")
xlx_cmd_file.write("set PrjFile=%4%.prj\n")
xlx_cmd_file.write("rem Output to XISEFile can be used to copy/paste into the \".xise\" file of a Xilinx ISE project in order to\n")
xlx_cmd_file.write("rem run the Xilinx GUI .\n")
xlx_cmd_file.write("set XISEFile=%4%.ise\n")
xlx_cmd_file.write("set lst_currentdate=%5%\n")
xlx_cmd_file.write("set lst_currentrevision=%6%\n")
xlx_cmd_file.write("set lst_lm32wrpc_dpramsize=%7%\n")
xlx_cmd_file.write("rem set lst_lm32_2nd_dpramsize=%8%\n")
xlx_cmd_file.write("rem set lst_clbv2_1=%9%\n")
xlx_cmd_file.write("\n")
xlx_cmd_file.write("del %PrjFile%\n") # restart writing PrjFile and
xlx_cmd_file.write("del %XISEFile%\n") # XISEFile (note '>' not '>>')
xlx_cmd_file.write("\n")
for line in hdlmakelist:
line = line.strip()
if line == "" or line[0] == "#":
pass
elif line[-2:] == ".v":
#add_verilog(xlx_cmd_file, "\"%lst_WRPC_Sources%\\" + line.replace("/","\\"))
add_verilog(xlx_cmd_file, "\"%lst_WRPC_Sources%/" + line)
elif line[-4:] == ".vhd":
#add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%\\" + line.replace("/","\\"))
add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%/" + line)
hdlmakelist.close()
"""
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\clb_wrpc\\top\\clb_wrpc.vhd")
# General and Generic files CLB Related
add_vhdl(xlx_cmd_file, "..\\..\\general_packages\\V_ARRAY_package.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_packages\\EMAC16bit_package.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummyMaster.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySlave.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySink.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySource.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\stimuli\\ClkRstGen.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\stimuli\\TransmitFrame16bit.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\metastabilizer.vhd")
# IPMUX related
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\modules\\clkdist.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\modules\\reg1en.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\top\\ipmux.vhd")
"""
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/clb_wrpc/top/clb_wrpc.vhd")
# General and Generic files CLB Related
add_vhdl(xlx_cmd_file, "\"../../../general_packages/V_ARRAY_package.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_packages/EMAC16bit_package.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummyMaster.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySlave.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySink.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySource.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/stimuli/ClkRstGen.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/stimuli/TransmitFrame16bit.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/metastabilizer.vhd")
# IPMUX related
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/modules/clkdist.vhd")
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/modules/reg1en.vhd")
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/top/ipmux.vhd")
# rem General files
add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd")
# rem CLB Top Level for FPGA
add_vhdl(xlx_cmd_file, "\"../../top/fpga.vhd")
xlx_cmd_file.write("@echo ^<file xil_pn:name=\"./fpga.ucf\" xil_pn:type=\"FILE_UCF\"^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^</file^> >> %XISEFile%\n")
# @echo ^<property xil_pn:name=\"Generics, Parameters\" xil_pn:value=\"g_date_id=%lst_currentdate% g_revision_id=%lst_currentrevision% g_lm32_wrpc_dpram_size=%lst_lm32wrpc_dpramsize% g_lm32_wrpc_profile=%lst_lm32wrpc_profile% g_lm32_2nd_dpram_size=%lst_lm32_2nd_dpramsize% g_lm32_2nd_profile=%lst_lm32_2nd_profile% g_use_clbv2_1=%lst_clbv2_1%" xil_pn:valueState="non-default"/^> >> %XISEFile%
xlx_cmd_file.write("@echo ^<property xil_pn:name=\"Generics, Parameters\" xil_pn:value=\"g_date_id=%lst_currentdate% g_revision_id=%lst_currentrevision% g_lm32_wrpc_dpram_size=%lst_lm32wrpc_dpramsize%\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^<property xil_pn:name=\"Other Ngdbuild Command Line Options\" xil_pn:value=\"-bm fpga.bmm -sd %lst_Arch1Path%\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^<property xil_pn:name=\"Other Bitgen Command Line Options\" xil_pn:value=\"-g UnconstrainedPins:Allow\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
xlx_cmd_file.close()
sys.exit()
hdl/clb_abs_calibration/syn/do_elf.cmd
View file @ 3b435d56
......@@ -7,9 +7,12 @@ rem the other "elf" file.
Rem reference design software
rem set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-sw\wrc.elf
rem set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-sw-v4_0\wrc.elf
set elf_file_lm32_wrpc=..\..\..\sw\embedded\wrpc-sw\wrc.elf
Rem calibration software
set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-cal-sw\wrc.elf
rem set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-cal-sw\wrc.elf
rem set elf_file_lm32_wrpc=..\..\..\..\InSituAlpha\wrpc-sw\wrc.elf
set tag_lm32_wrpc="lm32_wrpc_memory"
......
hdl/clb_abs_calibration/syn/do_input_file_list.cmd
View file @ 3b435d56
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/clb_abs_calibration/syn/fpga_xst.bmm
View file @ 3b435d56
......@@ -36,38 +36,38 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [31];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [30];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [29];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [28];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [27];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [26];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [25];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [24];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [23];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [22];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [21];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [20];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [19];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [18];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [17];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [16];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [15];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [14];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [13];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [12];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [11];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [10];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [9];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [8];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [7];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [6];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [5];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [4];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [3];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [2];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [1];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [0];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
......
hdl/ip_cores/clb_wrpc/clb_wrpc.ews/ease.db/lib0c012c7c15fe2515c321e8b5dea5b556/hdlf0c012c7c488d5a150970e8b590272832.eas
View file @ 3b435d56
(DATABASE_VERSION 17)
(DATABASE_VERSION 23)
(HDL_FILE
(OBID "hdlf0c012c7c488d5a150970e8b590272832")
(PROPERTIES
(PROPERTY "IMPORTED_LAST" "1445933596")
(PROPERTY "IMPORTED_LAST" "1490265023")
(PROPERTY "STAMP_PLATFORM" "PC")
(PROPERTY "STAMP_REVISION" "Revision 10")
(PROPERTY "STAMP_TIME" "Tue Oct 27 09:30:30 2015")
(PROPERTY "STAMP_REVISION" "Revision 5")
(PROPERTY "STAMP_TIME" "Thu Mar 23 11:35:33 2017")
(PROPERTY "STAMP_TOOL" "Ease")
(PROPERTY "STAMP_VERSION" "8.0")
(PROPERTY "STAMP_VERSION" "8.3")
(PROPERTY "SkipFileInFlow" "true")
(PROPERTY "TIME_MODIFIED_ONIMPORT" "1445874898")
(PROPERTY "TIME_MODIFIED_ONIMPORT" "1490256955")
)
(FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd")
(FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd")
(OBJSTAMP
(DESIGNER "peterj")
(CREATED 1369823364 "Wed May 29 12:29:24 2013")
(MODIFIED 1445933596 "Tue Oct 27 09:13:16 2015")
(MODIFIED 1490265023 "Thu Mar 23 11:30:23 2017")
)
)
(END_OF_FILE)
hdl/ip_cores/clb_wrpc/clb_wrpc.ews/ease.db/lib0c012c7c15fe2515c321e8b5dea5b556/library.eas
View file @ 3b435d56
......@@ -7,7 +7,7 @@
(PROPERTY "OUTPUT_FILE" "clb_wrpc.vhd")
(PROPERTY "STAMP_PLATFORM" "PC")
(PROPERTY "STAMP_REVISION" "Revision 5")
(PROPERTY "STAMP_TIME" "Fri Nov 04 11:42:45 2016")
(PROPERTY "STAMP_TIME" "Thu Mar 23 12:09:56 2017")
(PROPERTY "STAMP_TOOL" "Ease")
(PROPERTY "STAMP_VERSION" "8.3")
(PROPERTY "UseProjectHdlSettings" "yes")
......@@ -28,7 +28,7 @@
(ENTITY "wb_DummyMaster" "ent0c012c7c2f3c80250621e8b569bba6e4")
(ENTITY "wb_DummySlave" "ent0c012c7c5d94a025cda0e8b5da657ce4")
(ENTITY "wb_slave_adapter" "ent0c012c7cea719f154931e8b50db5c7e4")
(ENTITY "wr_gtx_phy_kintex7" "ent0c012c7c988d5a150970e8b5c0272832")
(ENTITY "wr_gtx_phy_family7" "ent0c012c5308ba3d85c191e1bcb726a481")
(ENTITY "wrc_periph" "ent0c012c7c68619f154931e8b55aa5c7e4")
(ENTITY "xwb_crossbar" "ent0c012c7c18e1e9158011e8b5d3c32f80")
(ENTITY "xwb_dpram" "ent0c012c7c76fe2515c321e8b506b5b556")
......@@ -36,6 +36,7 @@
(ENTITY "xwb_onewire_master" "ent0c012c7c785567154c61e8b50fc25380")
(ENTITY "xwb_sdb_crossbar" "ent0c012c7ce9af2515c321e8b50ac5b556")
(ENTITY "xwb_simple_uart" "ent0c012c7c35903515c321e8b53cd5b556")
(ENTITY "xwr_core" "ent0c012c532350cc850ae0e1bc54f313f1")
(ENTITY "xwr_endpoint" "ent0c012c7cb6119f150961e8b500e7aae2")
(ENTITY "xwr_mini_nic" "ent0c012c7c62519f154931e8b5bc85c7e4")
(ENTITY "xwr_pps_gen" "ent0c012c7c6db09f150961e8b597c7aae2")
......@@ -56,14 +57,14 @@
(PACKAGE "wishbone_pkg" "pack0c012c7cb02c80250621e8b5053ba6e4")
(PACKAGE "wr_fabric_pkg" "pack0c012c7c68d13515c321e8b59e6cb556")
(PACKAGE "wrcore_pkg" "pack0c012c7c37a34515c321e8b563bcb556")
(HDL_FILE "../../../general_packages/EMAC16bit_package.vhd" "hdlf0c012c7caf43b0250d11e8b5b7979ec4")
(HDL_FILE "../../../general_packages/v_array_package.vhd" "hdlf0c012c7c74da9b150201e8b542f62174")
(HDL_FILE "../../../general_modules/stimuli/ClkRstGen.vhd" "hdlf0c012c7c0050a025cc61e8b58d68eb73")
(HDL_FILE "../../../general_modules/stimuli/TransmitFrame16bit.vhd" "hdlf0c012c7cf910a025cc61e8b5df37eb73")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummyMaster.vhd" "hdlf0c012c7c963c80250621e8b587aba6e4")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummySink.vhd" "hdlf0c012c7cc4c4a025cda0e8b538b57ce4")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummySlave.vhd" "hdlf0c012c7c9c94a025cda0e8b5e6657ce4")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummySource.vhd" "hdlf0c012c7c95c4a025cda0e8b5acb57ce4")
(HDL_FILE "../../../general_packages/EMAC16bit_package.vhd" "hdlf0c012c7caf43b0250d11e8b5b7979ec4")
(HDL_FILE "../../../general_packages/v_array_package.vhd" "hdlf0c012c7c74da9b150201e8b542f62174")
(HDL_FILE "../../../wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd" "hdlf0c012c7cf3f1e9158011e8b5f1d32f80")
(HDL_FILE "../../../wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" "hdlf0c012c7c17fe2515c321e8b5c9b5b556")
(HDL_FILE "../../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" "hdlf0c012c7cc6fe2515c321e8b568b5b556")
......@@ -91,6 +92,7 @@
(HDL_FILE "../../../wr-cores/modules/wrc_core/wrc_periph.vhd" "hdlf0c012c7c58619f154931e8b52aa5c7e4")
(HDL_FILE "../../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" "hdlf0c012c7cb4a34515c321e8b5f0bcb556")
(HDL_FILE "../../../wr-cores/modules/wrc_core/wrcore_pkg.vhd" "hdlf0c012c7c37a34515c321e8b533bcb556")
(HDL_FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" "hdlf0c012c7c488d5a150970e8b590272832")
(HDL_FILE "../../../wr-cores/modules/wrc_core/xwr_core.vhd" "hdlf0c012c531350cc850ae0e1bc24f313f1")
(HDL_FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd" "hdlf0c012c53f7ba3d85c191e1bc8726a481")
)
(END_OF_FILE)
hdl/ip_cores/clb_wrpc/clb_wrpc.ews/project.xml
View file @ 3b435d56
......@@ -7,7 +7,7 @@
<section name="ObjectSearch">
<key type="bool" value="false" name="CaseSensitive"/>
<key type="bool" value="true" name="WholeWord"/>
<key type="string" value="pps_ext_i" name="SearchString"/>
<key type="string" value="dio" name="SearchString"/>
<key type="string" value="Any" name="TypeName"/>
</section>
<section name="TextSearch">
......@@ -20,7 +20,7 @@
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_peter/fw/CLBv2_Design/clb_wrpc/clb_wrpc.ews/html/index.htm" name="Index"/>
</section>
<section name="Markers">
<key type="string" value="design:Toplevel:&lt;Internal>/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c53c2dcc02544c0e1bc3b126856/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c533e9b92250ae0e1bce243a135" name="CurrentPath"/>
<key type="string" value="design:Toplevel:&lt;Internal>/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c53c2dcc02544c0e1bc3b126856" name="CurrentPath"/>
<key type="string" value="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c146f9025cc61e8b58876eb73" name="HdlOutputObject"/>
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_mesfin/fw/CLBv2_Design/clb_wrpc/top/clb_wrpc_top_tb.vhd" name="HdlOutputFile"/>
</section>
......@@ -32,8 +32,8 @@
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c99ab80250621e8b530c9a6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c39ab80250621e8b5e189a6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c39ab80250621e8b5b689a6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c212c80250621e8b5d83ba6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c212c80250621e8b5fb3ba6e4"/>
<key type="string" value="1490267408" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c212c80250621e8b5d83ba6e4"/>
<key type="string" value="1490267408" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c212c80250621e8b5fb3ba6e4"/>
</section>
<section name="GeneratedHdlFiles">
<key type="string" value="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/wr-calibration/hdl/ip_cores/clb_wrpc/clb_wrpc.ews/../top/clb_wrpc.vhd" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c99ab80250621e8b52ab9a6e4"/>
......@@ -95,12 +95,12 @@
<key type="bool" value="true" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c39ab80250621e8b5e189a6e4"/>
<key type="bool" value="true" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c99ab80250621e8b52ab9a6e4"/>
<key type="int" value="0" name="offset_x"/>
<key type="int" value="0" name="offset_y"/>
<key type="int" value="255" name="offset_y"/>
</section>
<section name="GenerationChecksums">
<key type="string" value="157F184AA09D776D" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/designs/ReferenceDesigns/fw/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
<key type="string" value="1D6E366A0D88F0AD" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/designs/clb_abs_calibration_V3/fw/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
<key type="string" value="4EC542A7B1F2F077" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/wr-calibration/hdl/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
<key type="string" value="E09C14362308EBE8" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/wr-calibration/hdl/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
</section>
<section name="FileView">
<key type="int" value="0" name="offset_x"/>
......
hdl/ip_cores/clb_wrpc/top/clb_wrpc.vhd
View file @ 3b435d56
......@@ -6,7 +6,7 @@
-- HDL library : work
-- Host name : SERING
-- User name : peterj
-- Time stamp : Fri Nov 04 11:48:18 2016
-- Time stamp : Thu Mar 23 12:10:08 2017
--
-- Designed by :
-- Company :
......@@ -14,1146 +14,9 @@
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Object : Entity design.clb_wr_core
-- Last modified : Tue Oct 27 09:30:06 2015
--------------------------------------------------------------------------------
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wrcore_pkg.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.softpll_pkg.all;
entity clb_wr_core is
generic(
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_pcs_16bit : boolean := false;
g_rx_buffer_size : integer := 1024;
g_dpram_size : integer := 90112/4; --in 32-bit words;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_simulation : integer := 0;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_tx_runt_padding : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_dpram_initf : string := "");
port (
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_p1_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
ext_snk_i : in t_wrf_sink_in;
ext_snk_o : out t_wrf_sink_out;
ext_src_i : in t_wrf_source_in;
ext_src_o : out t_wrf_source_out;
fc_pause_ack_o : out std_logic;
fc_pause_delay_i : in std_logic_vector(15 downto 0);
fc_pause_p_i : in std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
link_ok_o : out std_logic;
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0) := (others => '1');
owr_pwren_o : out std_logic_vector(1 downto 0);
phy_loopen_o : out std_logic_vector(2 downto 0);
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
phy_rst_o : out std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_sfp_tx_fault_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
pps_ext_i : in std_logic := '0';
pps_led_o : out std_logic;
pps_o : out std_logic;
rst_aux_n_o : out std_logic;
rst_n_i : in std_logic;
rxts_o : out std_logic;
scl_i : in std_logic := '1';
scl_o : out std_logic;
sda_i : in std_logic := '1';
sda_o : out std_logic;
sfp_det_i : in std_logic := '1';
sfp_scl_i : in std_logic := '1';
sfp_scl_o : out std_logic;
sfp_sda_i : in std_logic := '1';
sfp_sda_o : out std_logic;
spi_miso_i : in std_logic := '0';
spi_mosi_o : out std_logic;
spi_ncs_o : out std_logic;
spi_sclk_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_link_up_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_time_valid_o : out std_logic;
txts_o : out std_logic;
txtsu_ack_i : in std_logic := '1';
txtsu_frame_id_o : out std_logic_vector(15 downto 0);
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_stb_o : out std_logic;
txtsu_ts_incorrect_o : out std_logic;
txtsu_ts_value_o : out std_logic_vector(31 downto 0);
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
wb_bridge_master_i : in t_wishbone_master_in;
wb_bridge_master_o : out t_wishbone_master_out;
wb_bridge_slave_i : in t_wishbone_slave_in;
wb_bridge_slave_o : out t_wishbone_slave_out);
end entity clb_wr_core;
--------------------------------------------------------------------------------
-- Object : Architecture design.clb_wr_core.structure
-- Last modified : Tue Oct 27 09:30:06 2015
--------------------------------------------------------------------------------
architecture structure of clb_wr_core is
function f_int_to_bool(x : integer) return boolean is
begin
if(x /= 0) then
return true;
else
return false;
end if;
end f_int_to_bool;
-- function f_choose_lm32_firmware_file return string is
-- begin
-- if(g_dpram_initf = "default") then
-- if(g_simulation /= 0) then
-- report "[WR Core] Using simulation LM32 firmware." severity note;
-- return "wrc-simulation.ram";
-- else
-- report "[WR Core] Using release LM32 firmware." severity note;
-- return "wrc-release.ram";
-- end if;
-- else
-- report "[WR Core] Using user-provided LM32 firmware." severity note;
-- return g_dpram_initf;
-- end if;
-- end function;
function f_check_if_lm32_firmware_necessary return boolean is
begin
if(g_dpram_initf /= "") then
return true;
else
return false;
end if;
end function;
-----------------------------------------------------------------------------
--WB Secondary Crossbar
-----------------------------------------------------------------------------
constant c_secbar_layout : t_sdb_record_array(7 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
3 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00000300"),
4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"), -- Syscon
5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"), -- UART
6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"), -- 1-Wire
7 => f_sdb_embed_device(g_aux_sdb, x"00000700") -- aux WB bus
);
constant c_secbar_sdb_address : t_wishbone_address := x"00000800";
constant c_secbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
constant c_lm32_2nd_bridge_sdb : t_sdb_bridge := (
sdb_child => x"0000000000040000",
sdb_component => (
addr_first => x"0000000000000000", -- map LM32_2nd memory space
addr_last => x"000000000004ffff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"d1bbb357",
version => x"00000001",
date => x"20131119",
name => "LM32_2nd MEM SPACE "))
);
-----------------------------------------------------------------------------
--WB intercon
-----------------------------------------------------------------------------
constant c_layout : t_sdb_record_array(2 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00020000"),
2 => f_sdb_embed_bridge(c_lm32_2nd_bridge_sdb, x"00100000"));
constant c_sdb_address : t_wishbone_address := x"00030000";
constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
signal rst_net_n : std_logic;
signal secbar_master_o : t_wishbone_master_out_array(7 downto 0);
signal secbar_master_i : t_wishbone_master_in_array(7 downto 0);
signal ep_wb_out : t_wishbone_slave_out;
signal ep_wb_in : t_wishbone_slave_in;
signal spll_wb_out : t_wishbone_slave_out;
signal rst_wrc_n : std_logic;
signal s_pps_csync : std_logic;
signal pps_valid : std_logic;
signal ep_src_out : t_wrf_source_out;
signal ep_src_in : t_wrf_source_in;
signal ep_snk_out : t_wrf_sink_out;
signal ep_snk_in : t_wrf_sink_in;
signal ep_txtsu_port_id : std_logic_vector(4 downto 0);
signal ep_txtsu_frame_id : std_logic_vector(16 - 1 downto 0);
signal ep_txtsu_ts_value : std_logic_vector(28 + 4 - 1 downto 0);
signal ep_txtsu_ts_incorrect : std_logic;
signal cbar_master_i : t_wishbone_master_in_array(2 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(2 downto 0);
signal cbar_slave_i : t_wishbone_slave_in_array(2 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(2 downto 0);
signal dpram_wbb_o : t_wishbone_slave_out;
signal mnic_mem_data_o : std_logic_vector(31 downto 0);
signal mnic_mem_addr_o : std_logic_vector(c_mnic_memsize_log2 -1 downto 0);
signal mnic_mem_data_i : std_logic_vector(31 downto 0);
signal lm32_irq_slv : std_logic_vector(31 downto 0);
signal softpll_irq : std_logic;
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_sel : std_logic_vector(3 downto 0);
signal dac_dpll_load_p1 : std_logic;
signal clk_fb : std_logic_vector(g_aux_clks downto 0);
signal out_enable : std_logic_vector(g_aux_clks downto 0);
signal spll_out_locked : std_logic_vector(g_aux_clks downto 0);
signal mnic_txtsu_ack : std_logic;
signal U_SOFTPLL_clk_ref_i : std_logic_vector(0 downto 0);
signal periph_slave_o : t_wishbone_slave_out_array(0 to 2);
signal periph_slave_i : t_wishbone_slave_in_array(0 to 2);
signal dpram_wbb_i : t_wishbone_slave_in;
signal slave1_o : t_wishbone_slave_out;
signal slave1_i : t_wishbone_slave_in;
signal dwb_o : t_wishbone_master_out;
signal dwb_i : t_wishbone_master_in;
signal iwb_o : t_wishbone_master_out;
signal iwb_i : t_wishbone_master_in;
signal minic_wb_out : t_wishbone_slave_out;
signal minic_wb_in : t_wishbone_slave_in;
signal spll_wb_in : t_wishbone_slave_in;
signal ppsg_wb_out : t_wishbone_slave_out;
signal ppsg_wb_in : t_wishbone_slave_in;
signal slave_i : t_wishbone_slave_in_array(0 downto 0);
signal slave_o : t_wishbone_slave_out_array(0 downto 0);
signal ep_txtsu_stb : std_logic;
signal ep_led_link : std_logic;
signal dummy_slave_i : t_wishbone_slave_in;
signal dummy_slave_o : t_wishbone_slave_out;
signal mux_snk_out : t_wrf_sink_out_array(1 downto 0);
signal mux_snk_in : t_wrf_sink_in_array(1 downto 0);
signal mux_src_out : t_wrf_source_out_array(1 downto 0);
signal mux_src_in : t_wrf_source_in_array(1 downto 0);
signal mux_class : t_wrf_mux_class(1 downto 0);
signal ep_txtsu_ack : std_logic;
signal mnic_mem_wr_o : std_logic;
component xwr_pps_gen
generic(
g_interface_mode : t_wishbone_interface_mode := classic;
g_address_granularity : t_wishbone_address_granularity := word;
g_ref_clock_rate : integer := 125000000;
g_ext_clock_rate : integer := 10000000;
g_with_ext_clock_input : boolean := false);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic;
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0));
end component xwr_pps_gen;
component xwr_softpll_ng
generic(
g_tag_bits : integer;
g_num_ref_inputs : integer := 1;
g_num_outputs : integer := 1;
g_with_debug_fifo : boolean := false;
g_with_ext_clock_input : boolean := false;
g_reverse_dmtds : boolean := true;
g_divide_input_by_2 : boolean := false;
g_interface_mode : t_wishbone_interface_mode := pipelined;
g_address_granularity : t_wishbone_address_granularity := byte;
g_ref_clock_rate : integer := 125000000;
g_ext_clock_rate : integer := 10000000);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0);
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic;
clk_ext_mul_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
clk_ext_mul_locked_i : in std_logic := '1');
end component xwr_softpll_ng;
component xwr_mini_nic
generic(
g_interface_mode : t_wishbone_interface_mode := classic;
g_address_granularity : t_wishbone_address_granularity := word;
g_memsize_log2 : integer := 14;
g_buffer_little_endian : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_tsincorrect_i : in std_logic;
txtsu_stb_i : in std_logic;
txtsu_ack_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component xwr_mini_nic;
component wb_DummySlave
port (
Slave_i : in t_wishbone_slave_in;
Slave_o : out t_wishbone_slave_out);
end component wb_DummySlave;
begin
dio_o <= "0000";
rst_aux_n_o <= rst_net_n;
ext_src_o <= mux_src_out(1);
mux_src_in(1) <= ext_src_i;
led_link_o <= ep_led_link;
tm_link_up_o <= ep_led_link;
link_ok_o <= ep_led_link;
ext_snk_o <= mux_snk_out(1);
mux_snk_in(1) <= ext_snk_i;
PPS_GEN: xwr_pps_gen
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_ref_clock_rate => 62500000,
g_ext_clock_rate => 10000000,
g_with_ext_clock_input => g_with_external_clock_input)
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
clk_ext_i => clk_ext_i,
rst_n_i => rst_net_n,
slave_i => ppsg_wb_in,
slave_o => ppsg_wb_out,
pps_in_i => pps_ext_i,
pps_csync_o => s_pps_csync,
pps_out_o => pps_o,
pps_led_o => pps_led_o,
pps_valid_o => pps_valid,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o,
tm_utc_o => tm_tai_o);
U_SOFTPLL: xwr_softpll_ng
generic map(
g_tag_bits => 22,
g_num_ref_inputs => 1,
g_num_outputs => 1 + g_aux_clks,
g_with_debug_fifo => g_softpll_enable_debugger,
g_with_ext_clock_input => g_with_external_clock_input,
g_reverse_dmtds => false,
g_divide_input_by_2 => not g_pcs_16bit,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_ref_clock_rate => 62500000,
g_ext_clock_rate => 10000000)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_net_n,
clk_ref_i => U_SOFTPLL_clk_ref_i,
clk_fb_i => clk_fb,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
dac_dmtd_data_o => dac_hpll_data_o,
dac_dmtd_load_o => dac_hpll_load_p1_o,
dac_out_data_o => dac_dpll_data,
dac_out_sel_o => dac_dpll_sel,
dac_out_load_o => dac_dpll_load_p1,
out_enable_i => out_enable,
out_locked_o => spll_out_locked,
slave_i => spll_wb_in,
slave_o => spll_wb_out,
debug_o => open,
dbg_fifo_irq_o => open,
clk_ext_mul_i => clk_ext_mul_i,
pps_csync_p1_i => s_pps_csync,
pps_ext_a_i => pps_ext_i,
out_status_o => open,
clk_ext_mul_locked_i => clk_ext_mul_locked_i);
U_Endpoint: xwr_endpoint
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_simulation => f_int_to_bool(g_simulation),
g_pcs_16bit => g_pcs_16bit,
g_rx_buffer_size => g_rx_buffer_size,
g_with_rx_buffer => true,
g_with_flow_control => false,
g_with_timestamper => true,
g_with_dpi_classifier => true,
g_with_vlans => false,
g_with_rtu => false,
g_with_leds => true,
g_tx_force_gap_length => 0,
g_with_dmtd => false,
g_tx_runt_padding => g_tx_runt_padding,
g_with_packet_injection => false,
g_use_new_rxcrc => true,
g_use_new_txcrc => false,
g_with_stop_traffic => false)
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_net_n,
pps_csync_p1_i => s_pps_csync,
pps_valid_i => pps_valid,
phy_rst_o => phy_rst_o,
phy_loopen_o => open,
phy_enable_o => open,
phy_syncen_o => open,
phy_ref_clk_i => phy_ref_clk_i,
phy_tx_data_o => phy_tx_data_o,
phy_tx_k_o => phy_tx_k_o,
phy_tx_disparity_i => phy_tx_disparity_i,
phy_tx_enc_err_i => phy_tx_enc_err_i,
phy_rx_data_i => phy_rx_data_i,
phy_rx_clk_i => phy_rx_rbclk_i,
phy_rx_k_i => phy_rx_k_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_i,
gmii_tx_clk_i => open,
gmii_txd_o => open,
gmii_tx_en_o => open,
gmii_tx_er_o => open,
gmii_rx_clk_i => open,
gmii_rxd_i => open,
gmii_rx_er_i => open,
gmii_rx_dv_i => open,
src_o => ep_src_out,
src_i => ep_src_in,
snk_o => ep_snk_out,
snk_i => ep_snk_in,
txtsu_port_id_o => ep_txtsu_port_id,
txtsu_frame_id_o => ep_txtsu_frame_id,
txtsu_ts_value_o => ep_txtsu_ts_value,
txtsu_ts_incorrect_o => ep_txtsu_ts_incorrect,
txtsu_stb_o => ep_txtsu_stb,
txtsu_ack_i => ep_txtsu_ack,
rtu_full_i => open,
rtu_almost_full_i => open,
rtu_rq_strobe_p1_o => open,
rtu_rq_smac_o => open,
rtu_rq_dmac_o => open,
rtu_rq_vid_o => open,
rtu_rq_has_vid_o => open,
rtu_rq_prio_o => open,
rtu_rq_has_prio_o => open,
wb_i => ep_wb_in,
wb_o => ep_wb_out,
led_link_o => ep_led_link,
led_act_o => led_act_o,
rtu_rq_abort_o => open,
pfilter_pclass_o => open,
pfilter_drop_o => open,
pfilter_done_o => open,
fc_tx_pause_req_i => fc_pause_p_i,
fc_tx_pause_delay_i => fc_pause_delay_i,
fc_tx_pause_ready_o => fc_pause_ack_o,
fc_rx_pause_start_p_o => open,
fc_rx_pause_quanta_o => open,
fc_rx_pause_prio_mask_o => open,
fc_rx_buffer_occupation_o => open,
inject_req_i => open,
inject_ready_o => open,
inject_packet_sel_i => open,
inject_user_value_i => open,
rmon_events_o => open,
link_kill_i => open,
link_up_o => open,
dbg_tx_pcs_wr_count_o => open,
dbg_tx_pcs_rd_count_o => open,
phy_tx_prbs_sel_o => phy_tx_prbs_sel_o,
phy_sfp_tx_fault_i => phy_sfp_tx_fault_i,
phy_sfp_los_i => phy_sfp_los_i,
phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
phy_loopen_vec_o => phy_loopen_o,
phy_rdy_i => phy_rdy_i,
stop_traffic_i => '0',
nice_dbg_o => open,
txts_o => txts_o,
rxts_o => rxts_o);
MINI_NIC: xwr_mini_nic
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_memsize_log2 => f_log2_size(g_dpram_size),
g_buffer_little_endian => false)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_net_n,
mem_data_o => mnic_mem_data_o,
mem_addr_o => mnic_mem_addr_o,
mem_data_i => mnic_mem_data_i,
mem_wr_o => mnic_mem_wr_o,
src_o => mux_snk_in(0),
src_i => mux_snk_out(0),
snk_o => mux_src_in(0),
snk_i => mux_src_out(0),
txtsu_port_id_i => ep_txtsu_port_id,
txtsu_frame_id_i => ep_txtsu_frame_id,
txtsu_tsval_i => ep_txtsu_ts_value,
txtsu_tsincorrect_i => ep_txtsu_ts_incorrect,
txtsu_stb_i => ep_txtsu_stb,
txtsu_ack_o => mnic_txtsu_ack,
wb_i => minic_wb_in,
wb_o => minic_wb_out);
LM32_CORE: xwb_lm32
generic map(
g_profile => "medium_icache_debug",
g_reset_vector => X"00000000",
g_sdb_address => X"00000000")
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_wrc_n,
irq_i => lm32_irq_slv,
dwb_o => dwb_o,
dwb_i => dwb_i,
iwb_o => iwb_o,
iwb_i => iwb_i);
DPRAM: xwb_dpram
generic map(
g_size => g_dpram_size,
g_init_file => g_dpram_initf,
g_must_have_init_file => f_check_if_lm32_firmware_necessary,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => WORD)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave1_i => slave1_i,
slave1_o => slave1_o,
slave2_i => dpram_wbb_i,
slave2_o => dpram_wbb_o);
PERIPH: wrc_periph
generic map(
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_cntr_period => 62500,
g_mem_words => g_dpram_size,
g_vuart_fifo_size => g_vuart_fifo_size)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_net_n_o => rst_net_n,
rst_wrc_n_o => rst_wrc_n,
led_red_o => open,
led_green_o => open,
scl_o => scl_o,
scl_i => scl_i,
sda_o => sda_o,
sda_i => sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i,
memsize_i => "0000",
btn1_i => btn1_i,
btn2_i => btn2_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_pwren_o => owr_pwren_o,
owr_en_o => owr_en_o,
owr_i => owr_i,
slave_i => periph_slave_i,
slave_o => periph_slave_o,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i);
WB_CON: xwb_sdb_crossbar
generic map(
g_num_masters => 3,
g_num_slaves => 3,
g_registered => true,
g_wraparound => true,
g_layout => c_layout,
g_sdb_addr => c_sdb_address)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
master_i => cbar_master_i,
master_o => cbar_master_o);
WB_SECONDARY_CON: xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 8,
g_registered => true,
g_wraparound => true,
g_layout => c_secbar_layout,
g_sdb_addr => c_secbar_sdb_address)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => slave_i,
slave_o => slave_o,
master_i => secbar_master_i,
master_o => secbar_master_o);
U_wp_DummySlave: wb_DummySlave
port map(
Slave_i => dummy_slave_i,
Slave_o => dummy_slave_o);
U_WBP_MUX: xwrf_mux
generic map(
g_muxed_ports => 2)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
ep_src_o => ep_snk_in,
ep_src_i => ep_snk_out,
ep_snk_o => ep_src_in,
ep_snk_i => ep_src_out,
mux_src_o => mux_src_out,
mux_src_i => mux_src_in,
mux_snk_o => mux_snk_out,
mux_snk_i => mux_snk_in,
mux_class_i => mux_class);
lm32_irq_slv(31 downto 1) <= (others => '0');
lm32_irq_slv(0) <= softpll_irq; -- according to the doc, it's active low.
out_enable(0) <= '1';
out_enable(g_aux_clks downto 1) <= tm_clk_aux_lock_en_i;
dac_dpll_data_o <= dac_dpll_data;
dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"0") else '0';
tm_dac_value_o <= x"00" & dac_dpll_data;
p_decode_dac_writes : process(dac_dpll_load_p1, dac_dpll_sel)
begin
for i in 0 to g_aux_clks-1 loop
if dac_dpll_sel = std_logic_vector(to_unsigned(i+1, 4)) then
tm_dac_wr_o(i) <= dac_dpll_load_p1;
else
tm_dac_wr_o(i) <= '0';
end if;
end loop; -- i
end process;
locked_spll : if g_aux_clks > 0 generate
tm_clk_aux_locked_o <= spll_out_locked(g_aux_clks downto 1);
end generate;
cbar_master_i(0) <= slave1_o;
slave1_i <= cbar_master_o(0);
slave_i(0) <= cbar_master_o(1);
cbar_master_i(1) <= slave_o(0);
wb_bridge_master_o <= cbar_master_o(2);
cbar_master_i(2) <= wb_bridge_master_i;
dpram_wbb_i.cyc <= '1';
dpram_wbb_i.stb <= '1';
dpram_wbb_i.adr(c_mnic_memsize_log2-1 downto 0) <= mnic_mem_addr_o;
dpram_wbb_i.sel <= "1111";
dpram_wbb_i.we <= mnic_mem_wr_o;
dpram_wbb_i.dat <= mnic_mem_data_o;
mnic_mem_data_i <= dpram_wbb_o.dat;
dwb_i <= cbar_slave_o(0);
cbar_slave_i(0) <= dwb_o;
iwb_i <= cbar_slave_o(1);
cbar_slave_i(1) <= iwb_o;
wb_bridge_slave_o <= cbar_slave_o(2);
-- cbar_slave_i(2) <= wb_bridge_slave_i;
cbar_slave_i(2).adr <= wb_bridge_slave_i.adr and x"000fffff"; -- LM32_2nd Address 0x00100000 maps onto WRPC address 0x00000000
cbar_slave_i(2).cyc <= wb_bridge_slave_i.cyc;
cbar_slave_i(2).stb <= wb_bridge_slave_i.stb;
cbar_slave_i(2).sel <= wb_bridge_slave_i.sel;
cbar_slave_i(2).we <= wb_bridge_slave_i.we;
cbar_slave_i(2).dat <= wb_bridge_slave_i.dat;
secbar_master_i(0) <= minic_wb_out;
minic_wb_in <= secbar_master_o(0);
secbar_master_i(1) <= ep_wb_out;
ep_wb_in <= secbar_master_o(1);
secbar_master_i(2) <= spll_wb_out;
spll_wb_in <= secbar_master_o(2);
secbar_master_i(3) <= ppsg_wb_out;
ppsg_wb_in <= secbar_master_o(3);
--peripherials
secbar_master_i(4) <= periph_slave_o(0);
secbar_master_i(5) <= periph_slave_o(1);
secbar_master_i(6) <= periph_slave_o(2);
periph_slave_i(0) <= secbar_master_o(4);
periph_slave_i(1) <= secbar_master_o(5);
periph_slave_i(2) <= secbar_master_o(6);
dummy_slave_i <= secbar_master_o(7);
secbar_master_i(7) <= dummy_slave_o;
clk_fb(0) <= clk_ref_i;
clk_fb(g_aux_clks downto 1) <= clk_aux_i;
softpll_irq <= spll_wb_out.int;
txtsu_port_id_o <= ep_txtsu_port_id;
txtsu_frame_id_o <= ep_txtsu_frame_id;
txtsu_ts_value_o <= ep_txtsu_ts_value;
txtsu_ts_incorrect_o <= ep_txtsu_ts_incorrect;
txtsu_stb_o <= '1' when (ep_txtsu_stb = '1' and (ep_txtsu_frame_id /= x"0000")) else
'0';
U_SOFTPLL_clk_ref_i(0) <= phy_rx_rbclk_i;
mux_class(0) <= x"0f";
mux_class(1) <= x"f0";
ep_txtsu_ack <= txtsu_ack_i or mnic_txtsu_ack;
end architecture structure ; -- of clb_wr_core
--------------------------------------------------------------------------------
-- Object : Entity design.clb_xwr_core
-- Last modified : Tue Oct 27 09:27:50 2015
--------------------------------------------------------------------------------
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wrcore_pkg.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.softpll_pkg.all;
entity clb_xwr_core is
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_size : integer := 90112/4;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_pcs_16bit : boolean := false;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_tx_runt_padding : boolean := false;
g_dpram_initf : string := "");
port (
btn1_i : in std_logic;
btn2_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_p1_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
fc_pause_ack_o : out std_logic;
fc_pause_delay_i : in std_logic_vector(15 downto 0);
fc_pause_p_i : in std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
link_ok_o : out std_logic;
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
owr_pwren_o : out std_logic_vector(1 downto 0);
phy_loopen_o : out std_logic_vector(2 downto 0);
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
phy_rst_o : out std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_sfp_tx_fault_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
pps_ext_i : in std_logic := '0';
pps_led_o : out std_logic;
pps_o : out std_logic;
rst_aux_n_o : out std_logic;
rst_n_i : in std_logic;
rxts_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sfp_det_i : in std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
spi_miso_i : in std_logic;
spi_mosi_o : out std_logic;
spi_ncs_o : out std_logic;
spi_sclk_o : out std_logic;
timestamps_ack_i : in std_logic := '1';
timestamps_o : out t_txtsu_timestamp;
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_link_up_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_time_valid_o : out std_logic;
txts_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wb_bridge_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wb_bridge_master_o : out t_wishbone_master_out;
wb_bridge_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_bridge_slave_o : out t_wishbone_slave_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_src_o : out t_wrf_source_out);
end entity clb_xwr_core;
--------------------------------------------------------------------------------
-- Object : Architecture design.clb_xwr_core.structure
-- Last modified : Tue Oct 27 09:27:50 2015
--------------------------------------------------------------------------------
architecture structure of clb_xwr_core is
signal txtsu_port_id_o : std_logic_vector(4 downto 0);
signal txtsu_frame_id_o : std_logic_vector(15 downto 0);
signal txtsu_ts_value_o : std_logic_vector(31 downto 0);
signal txtsu_ts_incorrect_o : std_logic;
signal txtsu_stb_o : std_logic;
component clb_wr_core
generic(
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_pcs_16bit : boolean := false;
g_rx_buffer_size : integer := 1024;
g_dpram_size : integer := 90112/4; --in 32-bit words;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_simulation : integer := 0;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_tx_runt_padding : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_dpram_initf : string := "");
port (
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_p1_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
ext_snk_i : in t_wrf_sink_in;
ext_snk_o : out t_wrf_sink_out;
ext_src_i : in t_wrf_source_in;
ext_src_o : out t_wrf_source_out;
fc_pause_ack_o : out std_logic;
fc_pause_delay_i : in std_logic_vector(15 downto 0);
fc_pause_p_i : in std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
link_ok_o : out std_logic;
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0) := (others => '1');
owr_pwren_o : out std_logic_vector(1 downto 0);
phy_loopen_o : out std_logic_vector(2 downto 0);
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
phy_rst_o : out std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
phy_sfp_tx_fault_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
pps_ext_i : in std_logic := '0';
pps_led_o : out std_logic;
pps_o : out std_logic;
rst_aux_n_o : out std_logic;
rst_n_i : in std_logic;
rxts_o : out std_logic;
scl_i : in std_logic := '1';
scl_o : out std_logic;
sda_i : in std_logic := '1';
sda_o : out std_logic;
sfp_det_i : in std_logic := '1';
sfp_scl_i : in std_logic := '1';
sfp_scl_o : out std_logic;
sfp_sda_i : in std_logic := '1';
sfp_sda_o : out std_logic;
spi_miso_i : in std_logic := '0';
spi_mosi_o : out std_logic;
spi_ncs_o : out std_logic;
spi_sclk_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_link_up_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_time_valid_o : out std_logic;
txts_o : out std_logic;
txtsu_ack_i : in std_logic := '1';
txtsu_frame_id_o : out std_logic_vector(15 downto 0);
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_stb_o : out std_logic;
txtsu_ts_incorrect_o : out std_logic;
txtsu_ts_value_o : out std_logic_vector(31 downto 0);
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
wb_bridge_master_i : in t_wishbone_master_in;
wb_bridge_master_o : out t_wishbone_master_out;
wb_bridge_slave_i : in t_wishbone_slave_in;
wb_bridge_slave_o : out t_wishbone_slave_out);
end component clb_wr_core;
begin
WRPC: clb_wr_core
generic map(
g_with_external_clock_input => g_with_external_clock_input,
g_aux_clks => g_aux_clks,
g_pcs_16bit => g_pcs_16bit,
g_rx_buffer_size => g_ep_rxbuf_size,
g_dpram_size => g_dpram_size,
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_simulation => g_simulation,
g_aux_sdb => g_aux_sdb,
g_softpll_enable_debugger => false,
g_tx_runt_padding => g_tx_runt_padding,
g_vuart_fifo_size => g_vuart_fifo_size,
g_softpll_channels_config => c_softpll_default_channel_config,
g_dpram_initf => g_dpram_initf)
port map(
btn1_i => btn1_i,
btn2_i => btn2_i,
clk_aux_i => clk_aux_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
dac_dpll_data_o => dac_dpll_data_o,
dac_dpll_load_p1_o => dac_dpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dio_o => dio_o,
ext_snk_i => wrf_snk_i,
ext_snk_o => wrf_snk_o,
ext_src_i => wrf_src_i,
ext_src_o => wrf_src_o,
fc_pause_ack_o => fc_pause_ack_o,
fc_pause_delay_i => fc_pause_delay_i,
fc_pause_p_i => fc_pause_p_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
link_ok_o => link_ok_o,
owr_en_o => owr_en_o,
owr_i => owr_i,
owr_pwren_o => owr_pwren_o,
phy_loopen_o => phy_loopen_o,
phy_rdy_i => phy_rdy_i,
phy_ref_clk_i => phy_ref_clk_i,
phy_rst_o => phy_rst_o,
phy_rx_bitslide_i => phy_rx_bitslide_i,
phy_rx_data_i => phy_rx_data_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_k_i => phy_rx_k_i,
phy_rx_rbclk_i => phy_rx_rbclk_i,
phy_sfp_los_i => phy_sfp_los_i,
phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
phy_sfp_tx_fault_i => phy_sfp_tx_fault_i,
phy_tx_data_o => phy_tx_data_o,
phy_tx_disparity_i => phy_tx_disparity_i,
phy_tx_enc_err_i => phy_tx_enc_err_i,
phy_tx_k_o => phy_tx_k_o,
phy_tx_prbs_sel_o => phy_tx_prbs_sel_o,
pps_ext_i => pps_ext_i,
pps_led_o => pps_led_o,
pps_o => pps_o,
rst_aux_n_o => rst_aux_n_o,
rst_n_i => rst_n_i,
rxts_o => rxts_o,
scl_i => scl_i,
scl_o => scl_o,
sda_i => sda_i,
sda_o => sda_o,
sfp_det_i => sfp_det_i,
sfp_scl_i => sfp_scl_i,
sfp_scl_o => sfp_scl_o,
sfp_sda_i => sfp_sda_i,
sfp_sda_o => sfp_sda_o,
spi_miso_i => spi_miso_i,
spi_mosi_o => spi_mosi_o,
spi_ncs_o => spi_ncs_o,
spi_sclk_o => spi_sclk_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
tm_cycles_o => tm_cycles_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_link_up_o => tm_link_up_o,
tm_tai_o => tm_tai_o,
tm_time_valid_o => tm_time_valid_o,
txts_o => txts_o,
txtsu_ack_i => timestamps_ack_i,
txtsu_frame_id_o => txtsu_frame_id_o,
txtsu_port_id_o => txtsu_port_id_o,
txtsu_stb_o => txtsu_stb_o,
txtsu_ts_incorrect_o => txtsu_ts_incorrect_o,
txtsu_ts_value_o => txtsu_ts_value_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
wb_bridge_master_i => wb_bridge_master_i,
wb_bridge_master_o => wb_bridge_master_o,
wb_bridge_slave_i => wb_bridge_slave_i,
wb_bridge_slave_o => wb_bridge_slave_o);
timestamps_o.port_id(4 downto 0) <= txtsu_port_id_o;
timestamps_o.port_id(5) <= '0';
timestamps_o.frame_id <= txtsu_frame_id_o;
timestamps_o.tsval <= txtsu_ts_value_o;
timestamps_o.incorrect <= txtsu_ts_incorrect_o;
timestamps_o.stb <= txtsu_stb_o;
end architecture structure ; -- of clb_xwr_core
--------------------------------------------------------------------------------
-- Object : Entity design.clb_wrpc
-- Last modified : Fri Nov 04 11:36:27 2016
-- Last modified : Thu Mar 23 12:08:05 2017
--------------------------------------------------------------------------------
......@@ -1234,7 +97,7 @@ end entity clb_wrpc;
--------------------------------------------------------------------------------
-- Object : Architecture design.clb_wrpc.structure
-- Last modified : Fri Nov 04 11:36:27 2016
-- Last modified : Thu Mar 23 12:08:05 2017
--------------------------------------------------------------------------------
architecture structure of clb_wrpc is
......@@ -1268,7 +131,7 @@ architecture structure of clb_wrpc is
signal u3_CLKFBOUT : std_ulogic := '0';
signal phy_rst_o : std_logic;
signal rx_data_o : std_logic_vector(15 downto 0);
signal clk_rx_o_net : std_logic;
signal rx_rbclk_o_net : std_logic;
signal ref_clk_o_net : std_logic;
signal phy_loopen_o : std_logic_vector(2 downto 0);
signal tx_prbs_sel : std_logic_vector(2 downto 0);
......@@ -1293,11 +156,13 @@ architecture structure of clb_wrpc is
dac_din_o : out std_logic);
end component spec_serial_dac_arb;
component wr_gtx_phy_kintex7
component wr_gtx_phy_family7
generic(
g_simulation : integer := 0);
port (
clk_gtx_i : in std_logic;
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
......@@ -1309,115 +174,13 @@ architecture structure of clb_wrpc is
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic_vector(2 downto 0);
tx_prbs_sel_i : in std_logic_vector(2 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
tx_prbs_sel_i : in std_logic_vector(2 downto 0);
rdy_o : out std_logic);
end component wr_gtx_phy_kintex7;
component clb_xwr_core
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_size : integer := 90112/4;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_pcs_16bit : boolean := false;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_tx_runt_padding : boolean := false;
g_dpram_initf : string := "");
port (
btn1_i : in std_logic;
btn2_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_p1_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
fc_pause_ack_o : out std_logic;
fc_pause_delay_i : in std_logic_vector(15 downto 0);
fc_pause_p_i : in std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
link_ok_o : out std_logic;
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
owr_pwren_o : out std_logic_vector(1 downto 0);
phy_loopen_o : out std_logic_vector(2 downto 0);
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
phy_rst_o : out std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_sfp_tx_fault_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
pps_ext_i : in std_logic := '0';
pps_led_o : out std_logic;
pps_o : out std_logic;
rst_aux_n_o : out std_logic;
rst_n_i : in std_logic;
rxts_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sfp_det_i : in std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
spi_miso_i : in std_logic;
spi_mosi_o : out std_logic;
spi_ncs_o : out std_logic;
spi_sclk_o : out std_logic;
timestamps_ack_i : in std_logic := '1';
timestamps_o : out t_txtsu_timestamp;
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_link_up_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_time_valid_o : out std_logic;
txts_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wb_bridge_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wb_bridge_master_o : out t_wishbone_master_out;
wb_bridge_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_bridge_slave_o : out t_wishbone_slave_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_src_o : out t_wrf_source_out);
end component clb_xwr_core;
end component wr_gtx_phy_family7;
begin
--Source and Sink ports:
......@@ -1437,7 +200,7 @@ begin
dac_cs2_n_o <= dac_cs_n_o(1);
dac_cs1_n_o <= dac_cs_n_o(0);
dio_led_top_o <= pps_led;
rx_rbclk_o <= clk_rx_o_net;
rx_rbclk_o <= rx_rbclk_o_net;
ref_clk_o <= ref_clk_o_net;
cmp_clk_dmtd_buf: BUFG
......@@ -1541,32 +304,7 @@ begin
PWRDWN => '0',
RST => '0');
U_GTP: wr_gtx_phy_kintex7
generic map(
g_simulation => g_simulation)
port map(
clk_gtx_i => clk_gtx_i,
tx_data_i => phy_tx_data_o,
tx_k_i => phy_tx_k_o,
tx_disparity_o => ch1_tx_disparity_o,
tx_enc_err_o => ch1_tx_enc_err_o,
rx_rbclk_o => clk_rx_o_net,
rx_data_o => rx_data_o,
rx_k_o => rx_k_o,
rx_enc_err_o => ch1_rx_enc_err_o,
rx_bitslide_o => bitslide_net,
rst_i => phy_rst_o,
loopen_i => phy_loopen_o,
pad_txn_o => sfp_txn_o,
pad_txp_o => sfp_txp_o,
pad_rxn_i => sfp_rxn_i,
pad_rxp_i => sfp_rxp_i,
tx_out_clk_o => ref_clk_o_net,
tx_locked_o => ref_clk_locked_o,
tx_prbs_sel_i => tx_prbs_sel,
rdy_o => rdy_o);
U_WR_CORE: clb_xwr_core
U_WR_CORE: xwr_core
generic map(
g_simulation => g_simulation,
g_phys_uart => true,
......@@ -1574,96 +312,134 @@ begin
g_with_external_clock_input => true,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => true,
g_dpram_initf => g_dpram_initf,
g_dpram_size => g_dpram_size,
g_interface_mode => PIPELINED,
g_address_granularity => WORD,
g_pcs_16bit => TRUE,
g_address_granularity => BYTE,
g_aux_sdb => c_wrc_periph3_sdb,
g_softpll_enable_debugger => false,
g_vuart_fifo_size => 1024,
g_tx_runt_padding => TRUE,
g_dpram_initf => g_dpram_initf)
g_pcs_16bit => true,
g_records_for_phy => false,
g_diag_id => 0,
g_diag_ver => 0,
g_diag_ro_size => 0,
g_diag_rw_size => 0)
port map(
btn1_i => button1_i,
btn2_i => button2_i,
clk_aux_i => (others => '0'),
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd,
clk_ext_i => clk_ext_i,
clk_ref_i => ref_clk_o_net,
clk_aux_i => (others => '0'),
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ref_i => ref_clk_o_net,
clk_sys_i => clk_sys_i,
dac_dpll_data_o => dac_dpll_data_o,
dac_dpll_load_p1_o => dac_dpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o,
clk_ext_stopped_i => '0',
clk_ext_rst_o => open,
clk_ext_i => clk_ext_i,
pps_ext_i => pps_ext_i,
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dio_o => open,
fc_pause_ack_o => fc_pause_ack_o,
fc_pause_delay_i => fc_pause_delay_i,
fc_pause_p_i => fc_pause_p_i,
led_act_o => LED_ACT,
led_link_o => LED_LINK,
link_ok_o => open,
owr_en_o => owr_en,
owr_i => owr_i,
owr_pwren_o => open,
phy_loopen_o => phy_loopen_o,
phy_rdy_i => rdy_o,
dac_hpll_data_o => dac_hpll_data_o,
dac_dpll_load_p1_o => dac_dpll_load_p1_o,
dac_dpll_data_o => dac_dpll_data_o,
phy_ref_clk_i => ref_clk_o_net,
phy_rst_o => phy_rst_o,
phy_rx_bitslide_i => bitslide_net,
phy_rx_data_i => rx_data_o,
phy_rx_enc_err_i => ch1_rx_enc_err_o,
phy_rx_k_i => rx_k_o,
phy_rx_rbclk_i => clk_rx_o_net,
phy_sfp_los_i => sfp_los_i,
phy_sfp_tx_disable_o => sfp_tx_disable_o,
phy_sfp_tx_fault_i => sfp_tx_fault_i,
phy_tx_data_o => phy_tx_data_o,
phy_tx_k_o => phy_tx_k_o,
phy_tx_disparity_i => ch1_tx_disparity_o,
phy_tx_enc_err_i => ch1_tx_enc_err_o,
phy_tx_k_o => phy_tx_k_o,
phy_rx_data_i => rx_data_o,
phy_rx_rbclk_i => rx_rbclk_o_net,
phy_rx_k_i => rx_k_o,
phy_rx_enc_err_i => ch1_rx_enc_err_o,
phy_rx_bitslide_i => bitslide_net,
phy_rst_o => phy_rst_o,
phy_rdy_i => rdy_o,
phy_loopen_o => open,
phy_loopen_vec_o => phy_loopen_o,
phy_tx_prbs_sel_o => tx_prbs_sel,
pps_ext_i => pps_ext_i,
pps_led_o => pps_led,
pps_o => pps_o,
rst_aux_n_o => open,
rst_n_i => local_reset_n,
rxts_o => rxts_o,
scl_i => wrc_scl_i,
phy_sfp_tx_fault_i => sfp_tx_fault_i,
phy_sfp_los_i => sfp_los_i,
phy_sfp_tx_disable_o => sfp_tx_disable_o,
phy8_o => open,
phy8_i => open,
phy16_o => open,
phy16_i => open,
led_act_o => LED_ACT,
led_link_o => LED_LINK,
scl_o => wrc_scl_o,
sda_i => wrc_sda_i,
scl_i => wrc_scl_i,
sda_o => wrc_sda_o,
sfp_det_i => sfp_mod_def0_b,
sfp_scl_i => sfp_scl_i,
sda_i => wrc_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_sda_i => sfp_sda_i,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
spi_miso_i => '0',
spi_mosi_o => open,
spi_ncs_o => open,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_mod_def0_b,
btn1_i => button1_i,
btn2_i => button2_i,
spi_sclk_o => open,
timestamps_ack_i => '1',
spi_ncs_o => open,
spi_mosi_o => open,
spi_miso_i => '0',
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_pwren_o => open,
owr_en_o => owr_en,
owr_i => owr_i,
slave_i => wb_bridge_slave_i,
slave_o => wb_bridge_slave_o,
aux_master_o => wb_bridge_master_o,
aux_master_i => wb_bridge_master_i,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
timestamps_o => open,
tm_clk_aux_lock_en_i => (others => '0'),
tm_clk_aux_locked_o => open,
tm_cycles_o => tm_cycles_o,
timestamps_ack_i => '1',
txts_o => txts_o,
rxts_o => rxts_o,
fc_tx_pause_req_i => fc_pause_p_i,
fc_tx_pause_delay_i => fc_pause_delay_i,
fc_tx_pause_ready_o => fc_pause_ack_o,
tm_link_up_o => open,
tm_dac_value_o => open,
tm_dac_wr_o => open,
tm_link_up_o => open,
tm_tai_o => tm_tai_o,
tm_clk_aux_lock_en_i => (others => '0'),
tm_clk_aux_locked_o => open,
tm_time_valid_o => tm_time_valid_o,
txts_o => txts_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
wb_bridge_master_i => wb_bridge_master_i,
wb_bridge_master_o => wb_bridge_master_o,
wb_bridge_slave_i => wb_bridge_slave_i,
wb_bridge_slave_o => wb_bridge_slave_o,
wrf_snk_i => wrf_snk_i,
wrf_snk_o => wrf_snk_o,
wrf_src_i => wrf_src_i,
wrf_src_o => wrf_src_o);
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
pps_p_o => pps_o,
pps_led_o => pps_led,
rst_aux_n_o => open,
link_ok_o => open,
aux_diag_i => (others => (others => '0')),
aux_diag_o => open);
U_GTX: wr_gtx_phy_family7
generic map(
g_simulation => g_simulation)
port map(
clk_gtx_i => clk_gtx_i,
tx_out_clk_o => ref_clk_o_net,
tx_locked_o => ref_clk_locked_o,
tx_data_i => phy_tx_data_o,
tx_k_i => phy_tx_k_o,
tx_disparity_o => ch1_tx_disparity_o,
tx_enc_err_o => ch1_tx_enc_err_o,
rx_rbclk_o => rx_rbclk_o_net,
rx_data_o => rx_data_o,
rx_k_o => rx_k_o,
rx_enc_err_o => ch1_rx_enc_err_o,
rx_bitslide_o => bitslide_net,
rst_i => phy_rst_o,
loopen_i => phy_loopen_o,
tx_prbs_sel_i => tx_prbs_sel,
pad_txn_o => sfp_txn_o,
pad_txp_o => sfp_txp_o,
pad_rxn_i => sfp_rxn_i,
pad_rxp_i => sfp_rxp_i,
rdy_o => rdy_o);
fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
fpga_sda_b <= '0' when wrc_sda_o = '0' else 'Z';
......
wr-cores @ 89a58a48
Subproject commit 62e1d5ad0e7ab8e154462e34d166ab822a345280
Subproject commit 89a58a48d54f1f12adf746f9934751b9dc9c6299
wrpc-sw @ 54772b5b
Subproject commit 54772b5b5caf82787cb461b24163ae2eca8be438
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