Commit 3b435d56 authored by Peter Jansweijer's avatar Peter Jansweijer

moved on to wrpc v4.0 => clb_abs_calibration works (with standard wrpc-sw-v4.0…

moved on to wrpc v4.0 => clb_abs_calibration works (with standard wrpc-sw-v4.0 tuned for the CLB, no abs cal PPSi yet!)
parent 6c07897f
[submodule "hdl/wr-cores"]
path = hdl/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "sw/embedded/wrpc-sw"]
path = sw/embedded/wrpc-sw
url = git@ohwr.org:hdl-core-lib/wr-cores/wrpc-sw
......@@ -20,7 +20,7 @@
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_peter/fw/CLBv2_Design/clb/clb.ews/html/index.htm" name="Index"/>
</section>
<section name="Markers">
<key type="string" value="design:Toplevel:&lt;Internal>" name="CurrentPath"/>
<key type="string" value="design:Toplevel:&lt;Internal>/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c53c2dcc02544c0e1bc3b126856/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c533e9b92250ae0e1bce243a135" name="CurrentPath"/>
<key type="string" value="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c146f9025cc61e8b58876eb73" name="HdlOutputObject"/>
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_mesfin/fw/CLBv2_Design/clb_wrpc/top/clb_wrpc_top_tb.vhd" name="HdlOutputFile"/>
</section>
......
......@@ -40,9 +40,9 @@ if { $sim_task == "load"} {
source VSim_Current_Revision.tcl
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\WRPC_simu\\wrc.elf"]"
puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\wrpc-spec-sw-simu\\wrc.elf"]"
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\wrpc-sw\\wrc.elf"]"
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\precompiled\\WRPC_simu\\wrc.elf"]"
puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\precompiled\\wrpc-sw-simu\\wrc.elf"]"
# puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\precompiled\\wrpc-sw\\wrc.elf"]"
# !!! Note !!!: Don't forget to compile the software (elf file) for simulation (avoid printf etc. to speed up simulation time)
# !!! Note !!!: The double \\ are there since the DOS command below needs backslashes and a single backslash is seen as a switch in tcl
......@@ -74,11 +74,12 @@ if { $sim_task == "load"} {
+nowarn151 \
+nowarn8684 \
-G/clb_top_tb/g_simulation=$g_simulation \
-G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/g_must_have_init_file=true \
-G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/g_init_file=lm32_wrpc_memory.ldr \
-t ps -L unisim -lib work work.clb_top_tb
# -G/clb_top_tb/u2/tx_data_swap=false \
# -G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/g_must_have_init_file=true \
# -G/clb_top_tb/u5/u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/g_init_file=lm32_wrpc_memory.ldr \
do wave.tcl
......
#!/usr/bin/python
"""
Convert_ShoppingList_to_do_input_file_list.py: Converts
"hdlmake list-files > shoppinglist" file into do_input_file_list.cmd
-------------------------------------------------------------------------------
Copyright (C) 2017 Peter Jansweijer
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>
-------------------------------------------------------------------------------
Usage:
Convert_ShoppingList_to_do_input_file_list.py
Convert_ShoppingList_to_do_input_file_list.py -h | --help
<name> name of the hdlmake output file that lists al files needed
in the project (the shopplinlist)
-o <name> optional output file name, default: "do_input_file_list.cmd"
Options:
-h --help Show this screen.
"""
import os
import sys
import datetime
import pdb
############################################################################
def add_verilog(cmd_file, line):
cmd_file.write("@echo verilog work " + line + "\" >> %PrjFile%\n")
cmd_file.write("@echo ^<file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VERILOG\"^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"BehavioralSimulation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^</file^> >> %XISEFile%\n")
return()
def add_vhdl(cmd_file, line):
cmd_file.write("@echo vhdl work " + line + "\" >> %PrjFile%\n")
cmd_file.write("@echo ^<file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VHDL\"^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"BehavioralSimulation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
cmd_file.write("@echo ^</file^> >> %XISEFile%\n")
return()
############################################################################
#
# If run from commandline, we can test the library
#
"""
Usage:
Convert_ShoppingList_to_do_input_file_list.py
Convert_ShoppingList_to_do_input_file_list.py -h | --help
<name> name of the hdlmake output file that lists al files needed
in the project (the shopplinlist)
-o <name> optional output file name, default: "do_input_file_list.cmd"
Options:
-h --help Show this screen.
"""
if __name__ == "__main__":
import argparse
parser = argparse.ArgumentParser()
parser.add_argument("name", help="shopping list")
parser.add_argument("-oname", default="do_input_file_list.cmd", help="outfut file name ")
args = parser.parse_args()
name = args.name
oname = args.oname
if os.path.isfile(name) == True:
hdlmakelist = open(name,"r")
if os.path.isfile(oname) == True:
os.remove(oname)
xlx_cmd_file = open(oname,"w")
timestamp = datetime.datetime.now() #micro secounds timing
xlx_cmd_file.write("rem do_input_file_list.cmd PeterJ " + timestamp.strftime("%d %b %Y") + ", AutoGenerated by Convert_ShoppingList_to_do_input_file_list.py \n")
xlx_cmd_file.write("rem Prepares a .prj file for input to XST\n")
xlx_cmd_file.write("@prompt $$$s\n")
xlx_cmd_file.write("\n")
xlx_cmd_file.write("set lst_LM32_Sources=%1%\n")
xlx_cmd_file.write("set lst_WRPC_Sources=%2%\n")
xlx_cmd_file.write("set lst_Arch1Path=%3%\n")
xlx_cmd_file.write("set PrjFile=%4%.prj\n")
xlx_cmd_file.write("rem Output to XISEFile can be used to copy/paste into the \".xise\" file of a Xilinx ISE project in order to\n")
xlx_cmd_file.write("rem run the Xilinx GUI .\n")
xlx_cmd_file.write("set XISEFile=%4%.ise\n")
xlx_cmd_file.write("set lst_currentdate=%5%\n")
xlx_cmd_file.write("set lst_currentrevision=%6%\n")
xlx_cmd_file.write("set lst_lm32wrpc_dpramsize=%7%\n")
xlx_cmd_file.write("rem set lst_lm32_2nd_dpramsize=%8%\n")
xlx_cmd_file.write("rem set lst_clbv2_1=%9%\n")
xlx_cmd_file.write("\n")
xlx_cmd_file.write("del %PrjFile%\n") # restart writing PrjFile and
xlx_cmd_file.write("del %XISEFile%\n") # XISEFile (note '>' not '>>')
xlx_cmd_file.write("\n")
for line in hdlmakelist:
line = line.strip()
if line == "" or line[0] == "#":
pass
elif line[-2:] == ".v":
#add_verilog(xlx_cmd_file, "\"%lst_WRPC_Sources%\\" + line.replace("/","\\"))
add_verilog(xlx_cmd_file, "\"%lst_WRPC_Sources%/" + line)
elif line[-4:] == ".vhd":
#add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%\\" + line.replace("/","\\"))
add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%/" + line)
hdlmakelist.close()
"""
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\clb_wrpc\\top\\clb_wrpc.vhd")
# General and Generic files CLB Related
add_vhdl(xlx_cmd_file, "..\\..\\general_packages\\V_ARRAY_package.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_packages\\EMAC16bit_package.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummyMaster.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySlave.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySink.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySource.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\stimuli\\ClkRstGen.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\stimuli\\TransmitFrame16bit.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\metastabilizer.vhd")
# IPMUX related
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\modules\\clkdist.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\modules\\reg1en.vhd")
add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\top\\ipmux.vhd")
"""
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/clb_wrpc/top/clb_wrpc.vhd")
# General and Generic files CLB Related
add_vhdl(xlx_cmd_file, "\"../../../general_packages/V_ARRAY_package.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_packages/EMAC16bit_package.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummyMaster.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySlave.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySink.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySource.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/stimuli/ClkRstGen.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/stimuli/TransmitFrame16bit.vhd")
add_vhdl(xlx_cmd_file, "\"../../../general_modules/metastabilizer.vhd")
# IPMUX related
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/modules/clkdist.vhd")
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/modules/reg1en.vhd")
add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/top/ipmux.vhd")
# rem General files
add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd")
# rem CLB Top Level for FPGA
add_vhdl(xlx_cmd_file, "\"../../top/fpga.vhd")
xlx_cmd_file.write("@echo ^<file xil_pn:name=\"./fpga.ucf\" xil_pn:type=\"FILE_UCF\"^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^</file^> >> %XISEFile%\n")
# @echo ^<property xil_pn:name=\"Generics, Parameters\" xil_pn:value=\"g_date_id=%lst_currentdate% g_revision_id=%lst_currentrevision% g_lm32_wrpc_dpram_size=%lst_lm32wrpc_dpramsize% g_lm32_wrpc_profile=%lst_lm32wrpc_profile% g_lm32_2nd_dpram_size=%lst_lm32_2nd_dpramsize% g_lm32_2nd_profile=%lst_lm32_2nd_profile% g_use_clbv2_1=%lst_clbv2_1%" xil_pn:valueState="non-default"/^> >> %XISEFile%
xlx_cmd_file.write("@echo ^<property xil_pn:name=\"Generics, Parameters\" xil_pn:value=\"g_date_id=%lst_currentdate% g_revision_id=%lst_currentrevision% g_lm32_wrpc_dpram_size=%lst_lm32wrpc_dpramsize%\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^<property xil_pn:name=\"Other Ngdbuild Command Line Options\" xil_pn:value=\"-bm fpga.bmm -sd %lst_Arch1Path%\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
xlx_cmd_file.write("@echo ^<property xil_pn:name=\"Other Bitgen Command Line Options\" xil_pn:value=\"-g UnconstrainedPins:Allow\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
xlx_cmd_file.close()
sys.exit()
......@@ -7,9 +7,12 @@ rem the other "elf" file.
Rem reference design software
rem set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-sw\wrc.elf
rem set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-sw-v4_0\wrc.elf
set elf_file_lm32_wrpc=..\..\..\sw\embedded\wrpc-sw\wrc.elf
Rem calibration software
set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-cal-sw\wrc.elf
rem set elf_file_lm32_wrpc=..\..\..\sw\embedded\precompiled\wrpc-clb-cal-sw\wrc.elf
rem set elf_file_lm32_wrpc=..\..\..\..\InSituAlpha\wrpc-sw\wrc.elf
set tag_lm32_wrpc="lm32_wrpc_memory"
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -36,38 +36,38 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [31];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [30];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [29];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [28];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [27];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [26];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [25];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[3].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [24];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [23];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [22];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [21];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [20];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [19];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [18];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [17];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[2].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [16];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [15];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [14];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [13];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [12];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [11];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [10];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [9];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[1].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [8];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [7];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [6];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [5];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [4];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [3];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [2];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [1];
u0/U_WR_CORE/WRPC/DPRAM/GEN_NO_INITF.GEN_BYTESEL[0].U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [0];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
u0/U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
......
(DATABASE_VERSION 17)
(DATABASE_VERSION 23)
(HDL_FILE
(OBID "hdlf0c012c7c488d5a150970e8b590272832")
(PROPERTIES
(PROPERTY "IMPORTED_LAST" "1445933596")
(PROPERTY "IMPORTED_LAST" "1490265023")
(PROPERTY "STAMP_PLATFORM" "PC")
(PROPERTY "STAMP_REVISION" "Revision 10")
(PROPERTY "STAMP_TIME" "Tue Oct 27 09:30:30 2015")
(PROPERTY "STAMP_REVISION" "Revision 5")
(PROPERTY "STAMP_TIME" "Thu Mar 23 11:35:33 2017")
(PROPERTY "STAMP_TOOL" "Ease")
(PROPERTY "STAMP_VERSION" "8.0")
(PROPERTY "STAMP_VERSION" "8.3")
(PROPERTY "SkipFileInFlow" "true")
(PROPERTY "TIME_MODIFIED_ONIMPORT" "1445874898")
(PROPERTY "TIME_MODIFIED_ONIMPORT" "1490256955")
)
(FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd")
(FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd")
(OBJSTAMP
(DESIGNER "peterj")
(CREATED 1369823364 "Wed May 29 12:29:24 2013")
(MODIFIED 1445933596 "Tue Oct 27 09:13:16 2015")
(MODIFIED 1490265023 "Thu Mar 23 11:30:23 2017")
)
)
(END_OF_FILE)
......@@ -7,7 +7,7 @@
(PROPERTY "OUTPUT_FILE" "clb_wrpc.vhd")
(PROPERTY "STAMP_PLATFORM" "PC")
(PROPERTY "STAMP_REVISION" "Revision 5")
(PROPERTY "STAMP_TIME" "Fri Nov 04 11:42:45 2016")
(PROPERTY "STAMP_TIME" "Thu Mar 23 12:09:56 2017")
(PROPERTY "STAMP_TOOL" "Ease")
(PROPERTY "STAMP_VERSION" "8.3")
(PROPERTY "UseProjectHdlSettings" "yes")
......@@ -28,7 +28,7 @@
(ENTITY "wb_DummyMaster" "ent0c012c7c2f3c80250621e8b569bba6e4")
(ENTITY "wb_DummySlave" "ent0c012c7c5d94a025cda0e8b5da657ce4")
(ENTITY "wb_slave_adapter" "ent0c012c7cea719f154931e8b50db5c7e4")
(ENTITY "wr_gtx_phy_kintex7" "ent0c012c7c988d5a150970e8b5c0272832")
(ENTITY "wr_gtx_phy_family7" "ent0c012c5308ba3d85c191e1bcb726a481")
(ENTITY "wrc_periph" "ent0c012c7c68619f154931e8b55aa5c7e4")
(ENTITY "xwb_crossbar" "ent0c012c7c18e1e9158011e8b5d3c32f80")
(ENTITY "xwb_dpram" "ent0c012c7c76fe2515c321e8b506b5b556")
......@@ -36,6 +36,7 @@
(ENTITY "xwb_onewire_master" "ent0c012c7c785567154c61e8b50fc25380")
(ENTITY "xwb_sdb_crossbar" "ent0c012c7ce9af2515c321e8b50ac5b556")
(ENTITY "xwb_simple_uart" "ent0c012c7c35903515c321e8b53cd5b556")
(ENTITY "xwr_core" "ent0c012c532350cc850ae0e1bc54f313f1")
(ENTITY "xwr_endpoint" "ent0c012c7cb6119f150961e8b500e7aae2")
(ENTITY "xwr_mini_nic" "ent0c012c7c62519f154931e8b5bc85c7e4")
(ENTITY "xwr_pps_gen" "ent0c012c7c6db09f150961e8b597c7aae2")
......@@ -56,14 +57,14 @@
(PACKAGE "wishbone_pkg" "pack0c012c7cb02c80250621e8b5053ba6e4")
(PACKAGE "wr_fabric_pkg" "pack0c012c7c68d13515c321e8b59e6cb556")
(PACKAGE "wrcore_pkg" "pack0c012c7c37a34515c321e8b563bcb556")
(HDL_FILE "../../../general_packages/EMAC16bit_package.vhd" "hdlf0c012c7caf43b0250d11e8b5b7979ec4")
(HDL_FILE "../../../general_packages/v_array_package.vhd" "hdlf0c012c7c74da9b150201e8b542f62174")
(HDL_FILE "../../../general_modules/stimuli/ClkRstGen.vhd" "hdlf0c012c7c0050a025cc61e8b58d68eb73")
(HDL_FILE "../../../general_modules/stimuli/TransmitFrame16bit.vhd" "hdlf0c012c7cf910a025cc61e8b5df37eb73")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummyMaster.vhd" "hdlf0c012c7c963c80250621e8b587aba6e4")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummySink.vhd" "hdlf0c012c7cc4c4a025cda0e8b538b57ce4")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummySlave.vhd" "hdlf0c012c7c9c94a025cda0e8b5e6657ce4")
(HDL_FILE "../../../general_modules/wb_dummys/wb_DummySource.vhd" "hdlf0c012c7c95c4a025cda0e8b5acb57ce4")
(HDL_FILE "../../../general_packages/EMAC16bit_package.vhd" "hdlf0c012c7caf43b0250d11e8b5b7979ec4")
(HDL_FILE "../../../general_packages/v_array_package.vhd" "hdlf0c012c7c74da9b150201e8b542f62174")
(HDL_FILE "../../../wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd" "hdlf0c012c7cf3f1e9158011e8b5f1d32f80")
(HDL_FILE "../../../wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" "hdlf0c012c7c17fe2515c321e8b5c9b5b556")
(HDL_FILE "../../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" "hdlf0c012c7cc6fe2515c321e8b568b5b556")
......@@ -91,6 +92,7 @@
(HDL_FILE "../../../wr-cores/modules/wrc_core/wrc_periph.vhd" "hdlf0c012c7c58619f154931e8b52aa5c7e4")
(HDL_FILE "../../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" "hdlf0c012c7cb4a34515c321e8b5f0bcb556")
(HDL_FILE "../../../wr-cores/modules/wrc_core/wrcore_pkg.vhd" "hdlf0c012c7c37a34515c321e8b533bcb556")
(HDL_FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" "hdlf0c012c7c488d5a150970e8b590272832")
(HDL_FILE "../../../wr-cores/modules/wrc_core/xwr_core.vhd" "hdlf0c012c531350cc850ae0e1bc24f313f1")
(HDL_FILE "../../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd" "hdlf0c012c53f7ba3d85c191e1bc8726a481")
)
(END_OF_FILE)
......@@ -7,7 +7,7 @@
<section name="ObjectSearch">
<key type="bool" value="false" name="CaseSensitive"/>
<key type="bool" value="true" name="WholeWord"/>
<key type="string" value="pps_ext_i" name="SearchString"/>
<key type="string" value="dio" name="SearchString"/>
<key type="string" value="Any" name="TypeName"/>
</section>
<section name="TextSearch">
......@@ -20,7 +20,7 @@
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_peter/fw/CLBv2_Design/clb_wrpc/clb_wrpc.ews/html/index.htm" name="Index"/>
</section>
<section name="Markers">
<key type="string" value="design:Toplevel:&lt;Internal>/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c53c2dcc02544c0e1bc3b126856/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c533e9b92250ae0e1bce243a135" name="CurrentPath"/>
<key type="string" value="design:Toplevel:&lt;Internal>/lib0c012c7c15fe2515c321e8b5dea5b556_comp0c012c53c2dcc02544c0e1bc3b126856" name="CurrentPath"/>
<key type="string" value="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c146f9025cc61e8b58876eb73" name="HdlOutputObject"/>
<key type="string" value="P:/App/KM3Net/CLB/CLBv2/SVN_Valencia/CLBv2_mesfin/fw/CLBv2_Design/clb_wrpc/top/clb_wrpc_top_tb.vhd" name="HdlOutputFile"/>
</section>
......@@ -32,8 +32,8 @@
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c99ab80250621e8b530c9a6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c39ab80250621e8b5e189a6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c39ab80250621e8b5b689a6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c212c80250621e8b5d83ba6e4"/>
<key type="string" value="1478256498" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c212c80250621e8b5fb3ba6e4"/>
<key type="string" value="1490267408" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c212c80250621e8b5d83ba6e4"/>
<key type="string" value="1490267408" name="lib0c012c7c15fe2515c321e8b5dea5b556_arch0c012c7c212c80250621e8b5fb3ba6e4"/>
</section>
<section name="GeneratedHdlFiles">
<key type="string" value="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/wr-calibration/hdl/ip_cores/clb_wrpc/clb_wrpc.ews/../top/clb_wrpc.vhd" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c99ab80250621e8b52ab9a6e4"/>
......@@ -95,12 +95,12 @@
<key type="bool" value="true" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c39ab80250621e8b5e189a6e4"/>
<key type="bool" value="true" name="lib0c012c7c15fe2515c321e8b5dea5b556_ent0c012c7c99ab80250621e8b52ab9a6e4"/>
<key type="int" value="0" name="offset_x"/>
<key type="int" value="0" name="offset_y"/>
<key type="int" value="255" name="offset_y"/>
</section>
<section name="GenerationChecksums">
<key type="string" value="157F184AA09D776D" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/designs/ReferenceDesigns/fw/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
<key type="string" value="1D6E366A0D88F0AD" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/designs/clb_abs_calibration_V3/fw/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
<key type="string" value="4EC542A7B1F2F077" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/wr-calibration/hdl/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
<key type="string" value="E09C14362308EBE8" name="P:/App/ASTERICS_Cleopatra_WP5_1/WR_Calibration/wr-calibration/hdl/ip_cores/clb_wrpc/top/clb_wrpc.vhd"/>
</section>
<section name="FileView">
<key type="int" value="0" name="offset_x"/>
......
This diff is collapsed.
wr-cores @ 89a58a48
Subproject commit 62e1d5ad0e7ab8e154462e34d166ab822a345280
Subproject commit 89a58a48d54f1f12adf746f9934751b9dc9c6299
wrpc-sw @ 54772b5b
Subproject commit 54772b5b5caf82787cb461b24163ae2eca8be438
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