added clock constraints

c35a0ef3 · Peter Jansweijer · 7fc1d74f · c35a0ef3
Commit c35a0ef3 authored Sep 13, 2017 by Peter Jansweijer
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clb_abs_calibration.xdc hdl/clb_abs_calibration/vivado/clb_abs_calibration.xdc +5 -1

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--- a/hdl/clb_abs_calibration/vivado/clb_abs_calibration.xdc
+++ b/hdl/clb_abs_calibration/vivado/clb_abs_calibration.xdc
@@ -346,7 +346,10 @@ set_property PACKAGE_PIN D6 [get_ports FPGA_PLL_REF_CLK0_P]
 create_clock -period 8.000 -name FPGA_PLL_REF_CLK0_P -waveform {0.000 4.000} [get_ports FPGA_PLL_REF_CLK0_P]
 set_property PACKAGE_PIN D5 [get_ports FPGA_PLL_REF_CLK0_N]
 #set_property IOSTANDARD LVDS_25 [get_ports FPGA_PLL_REF_CLK0_N]
-create_clock -period 8.000 -name FPGA_PLL_REF_CLK0_n -waveform {0.000 4.000} [get_ports FPGA_PLL_REF_CLK0_N]
+#create_clock -period 8.000 -name FPGA_PLL_REF_CLK0_n -waveform {0.000 4.000} [get_ports FPGA_PLL_REF_CLK0_N]
+
+create_clock -period 16.000 -name u0/U_GTX/U_GTX_INST/gtxe2_i/RXOUTCLK -waveform {0.000 8.000} [get_pins u0/U_GTX/U_GTX_INST/gtxe2_i/RXOUTCLK]
+create_clock -period 16.000 -name u0/U_GTX/U_GTX_INST/gtxe2_i/TXOUTCLK -waveform {0.000 8.000} [get_pins u0/U_GTX/U_GTX_INST/gtxe2_i/TXOUTCLK]

 #>>>#NET "FPGA_PLL_REF_CLK0_P" TNM_NET = FPGA_PLL_REF_CLK0_P;
 #>>>#TIMESPEC TS_FPGA_PLL_REF_CLK0_P = PERIOD "FPGA_PLL_REF_CLK0_P" 8 ns HIGH 50%;
@@ -560,6 +563,7 @@ set_property IOSTANDARD LVCMOS25 [get_ports dio_onewire_b]
 # DIO inputs
 set_property PACKAGE_PIN Y22 [get_ports dio_clk_p_i]
 set_property IOSTANDARD LVDS_25 [get_ports dio_clk_p_i]
+create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
 #CLK1_M2C_P L20

 set_property PACKAGE_PIN AA22 [get_ports dio_clk_n_i]