wr_transmission_wb

WR Transmission control, status and debug

-----------------------------------------------------------------
This WB registers allow to diagnose transmission and reception of
data using WR streamers.
In particular, these registers provide access to streamer's
statistics that can be also access from SNMP, if supported.
-----------------------------------------------------------------
Copyright (c) 2016 CERN/BE-CO-HT & CERN/TE-MS-MM

This source file is free software; you can redistribute it
and/or modify it under the terms of the GNU Lesser General
Public License as published by the Free Software Foundation;
either version 2.1 of the License, or (at your option) any
later version.

This source is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU Lesser General Public License for more
details

You should have received a copy of the GNU Lesser General
Public License along with this source; if not, download it
from http://www.gnu.org/licenses/lgpl-2.1.html
-----------------------------------------------------------------

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Statistics status and ctrl register
3.2. Statistics status and ctrl register
3.3. Tx statistics
3.4. Rx statistics
3.5. Rx statistics
3.6. Rx statistics
3.7. Rx statistics
3.8. Rx statistics
3.9. Rx statistics
3.10. Rx statistics
3.11. Rx statistics
3.12. Tx Config Reg 0
3.13. Tx Config Reg 1
3.14. Tx Config Reg 2
3.15. Tx Config Reg 3
3.16. Tx Config Reg 4
3.17. Rx Config Reg 0
3.18. Rx Config Reg 1
3.19. Rx Config Reg 2
3.20. Rx Config Reg 3
3.21. Rx Config Reg 4
3.22. Rx Config Reg 5
3.23. TxRx Config Override
3.24. DBG Control register
3.25. DBG Data
3.26. DBG RX_BVALUE
3.27. DBG tx bvalue
3.28. Test value

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	Statistics status and ctrl register	wr_transmission_sscr1	SSCR1
0x1	REG	Statistics status and ctrl register	wr_transmission_sscr2	SSCR2
0x2	REG	Tx statistics	wr_transmission_tx_stat	TX_STAT
0x3	REG	Rx statistics	wr_transmission_rx_stat1	RX_STAT1
0x4	REG	Rx statistics	wr_transmission_rx_stat2	RX_STAT2
0x5	REG	Rx statistics	wr_transmission_rx_stat3	RX_STAT3
0x6	REG	Rx statistics	wr_transmission_rx_stat4	RX_STAT4
0x7	REG	Rx statistics	wr_transmission_rx_stat5	RX_STAT5
0x8	REG	Rx statistics	wr_transmission_rx_stat6	RX_STAT6
0x9	REG	Rx statistics	wr_transmission_rx_stat7	RX_STAT7
0xa	REG	Rx statistics	wr_transmission_rx_stat8	RX_STAT8
0xb	REG	Tx Config Reg 0	wr_transmission_tx_cfg0	TX_CFG0
0xc	REG	Tx Config Reg 1	wr_transmission_tx_cfg1	TX_CFG1
0xd	REG	Tx Config Reg 2	wr_transmission_tx_cfg2	TX_CFG2
0xe	REG	Tx Config Reg 3	wr_transmission_tx_cfg3	TX_CFG3
0xf	REG	Tx Config Reg 4	wr_transmission_tx_cfg4	TX_CFG4
0x10	REG	Rx Config Reg 0	wr_transmission_rx_cfg0	RX_CFG0
0x11	REG	Rx Config Reg 1	wr_transmission_rx_cfg1	RX_CFG1
0x12	REG	Rx Config Reg 2	wr_transmission_rx_cfg2	RX_CFG2
0x13	REG	Rx Config Reg 3	wr_transmission_rx_cfg3	RX_CFG3
0x14	REG	Rx Config Reg 4	wr_transmission_rx_cfg4	RX_CFG4
0x15	REG	Rx Config Reg 5	wr_transmission_rx_cfg5	RX_CFG5
0x16	REG	TxRx Config Override	wr_transmission_cfg	CFG
0x17	REG	DBG Control register	wr_transmission_dbg_ctrl	DBG_CTRL
0x18	REG	DBG Data	wr_transmission_dbg_data	DBG_DATA
0x19	REG	DBG RX_BVALUE	wr_transmission_dbg_rx_bvalue	DBG_RX_BVALUE
0x1a	REG	DBG tx bvalue	wr_transmission_dbg_tx_bvalue	DBG_TX_BVALUE
0x1b	REG	Test value	wr_transmission_dummy	DUMMY

2. HDL symbol

→	rst_n_i	Statistics status and ctrl register:
→	clk_sys_i	wr_transmission_sscr1_rst_stats_o	→
⇒	wb_adr_i[4:0]	wr_transmission_sscr1_rst_seq_id_o	→
⇒	wb_dat_i[31:0]	wr_transmission_sscr1_snapshot_stats_o	→
⇐	wb_dat_o[31:0]	wr_transmission_sscr1_rx_latency_acc_overflow_i	←
→	wb_cyc_i	wr_transmission_sscr1_rst_ts_cyc_i[27:0]	⇐
⇒	wb_sel_i[3:0]
→	wb_stb_i	Statistics status and ctrl register:
→	wb_we_i	wr_transmission_sscr2_rst_ts_tai_lsb_i[31:0]	⇐
←	wb_ack_o
←	wb_stall_o	Tx statistics:
		wr_transmission_tx_stat_tx_sent_cnt_i[31:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat1_rx_rcvd_cnt_i[31:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat2_rx_loss_cnt_i[31:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat3_rx_latency_max_i[27:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat4_rx_latency_min_i[27:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat5_rx_latency_acc_lsb_i[31:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat6_rx_latency_acc_msb_i[31:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat7_rx_latency_acc_cnt_i[31:0]	⇐

		Rx statistics:
		wr_transmission_rx_stat8_rx_lost_block_cnt_i[31:0]	⇐

		Tx Config Reg 0:
		wr_transmission_tx_cfg0_ethertype_o[15:0]	⇒

		Tx Config Reg 1:
		wr_transmission_tx_cfg1_mac_local_lsb_o[31:0]	⇒

		Tx Config Reg 2:
		wr_transmission_tx_cfg2_mac_local_msb_o[15:0]	⇒

		Tx Config Reg 3:
		wr_transmission_tx_cfg3_mac_target_lsb_o[31:0]	⇒

		Tx Config Reg 4:
		wr_transmission_tx_cfg4_mac_target_msb_o[15:0]	⇒

		Rx Config Reg 0:
		wr_transmission_rx_cfg0_ethertype_o[15:0]	⇒
		wr_transmission_rx_cfg0_accept_broadcast_o	→
		wr_transmission_rx_cfg0_filter_remote_o	→

		Rx Config Reg 1:
		wr_transmission_rx_cfg1_mac_local_lsb_o[31:0]	⇒

		Rx Config Reg 2:
		wr_transmission_rx_cfg2_mac_local_msb_o[15:0]	⇒

		Rx Config Reg 3:
		wr_transmission_rx_cfg3_mac_remote_lsb_o[31:0]	⇒

		Rx Config Reg 4:
		wr_transmission_rx_cfg4_mac_remote_msb_o[15:0]	⇒

		Rx Config Reg 5:
		wr_transmission_rx_cfg5_fixed_latency_o[27:0]	⇒

		TxRx Config Override:
		wr_transmission_cfg_or_tx_ethtype_o	→
		wr_transmission_cfg_or_tx_mac_loc_o	→
		wr_transmission_cfg_or_tx_mac_tar_o	→
		wr_transmission_cfg_or_rx_ethertype_o	→
		wr_transmission_cfg_or_rx_mac_loc_o	→
		wr_transmission_cfg_or_rx_mac_rem_o	→
		wr_transmission_cfg_or_rx_acc_broadcast_o	→
		wr_transmission_cfg_or_rx_ftr_remote_o	→
		wr_transmission_cfg_or_rx_fix_lat_o	→

		DBG Control register:
		wr_transmission_dbg_ctrl_mux_o	→
		wr_transmission_dbg_ctrl_start_byte_o[7:0]	⇒

		DBG Data:
		wr_transmission_dbg_data_i[31:0]	⇐

		DBG RX_BVALUE:
		wr_transmission_dbg_rx_bvalue_i[31:0]	⇐

		DBG tx bvalue:
		wr_transmission_dbg_tx_bvalue_i[31:0]	⇐

		Test value:
		wr_transmission_dummy_dummy_i[31:0]	⇐

3. Register description

3.1. Statistics status and ctrl register

HW prefix:	wr_transmission_sscr1
HW address:	0x0
C prefix:	SSCR1
C offset:	0x0

31	30	29	28	27	26	25	24
RST_TS_CYC[27:20]

23	22	21	20	19	18	17	16
RST_TS_CYC[19:12]

15	14	13	12	11	10	9	8
RST_TS_CYC[11:4]

7	6	5	4	3	2	1	0
RST_TS_CYC[3:0]				RX_LATENCY_ACC_OVERFLOW	SNAPSHOT_STATS	RST_SEQ_ID	RST_STATS

RST_STATS [write-only]: Reset statistics
Writing 1 reset counters, latency acc/max/min. This reset is timestamped
RST_SEQ_ID [write-only]: Reset tx seq id
Writing 1 reset sequence ID of transmitted frames
SNAPSHOT_STATS [read/write]: Snapshot statistics
Writing 1 snapshots statistics for reading, it means that all the counters
are copied at the same instant to registers and this registers can be read
via wishbone/snmp while the counters are still running in the background.
this allows to read coherent data
RX_LATENCY_ACC_OVERFLOW [read-only]: Latency accumulator overflow
Latency accumulator overflow - the lateny accumulator value is invalid
RST_TS_CYC [read-only]: Reset timestamp cycles
Timestamp of the last reset of stats (RST_STAT) -- count of clock cycles

3.2. Statistics status and ctrl register

HW prefix:	wr_transmission_sscr2
HW address:	0x1
C prefix:	SSCR2
C offset:	0x4

31	30	29	28	27	26	25	24
RST_TS_TAI_LSB[31:24]

23	22	21	20	19	18	17	16
RST_TS_TAI_LSB[23:16]

15	14	13	12	11	10	9	8
RST_TS_TAI_LSB[15:8]

7	6	5	4	3	2	1	0
RST_TS_TAI_LSB[7:0]

RST_TS_TAI_LSB [read-only]: Reset timestamp 32 LSB of TAI
Timestamp of the last reset of stats (RST_STAT) -- LSB 32 bits of TAI

3.3. Tx statistics

HW prefix:	wr_transmission_tx_stat
HW address:	0x2
C prefix:	TX_STAT
C offset:	0x8

31	30	29	28	27	26	25	24
TX_SENT_CNT[31:24]

23	22	21	20	19	18	17	16
TX_SENT_CNT[23:16]

15	14	13	12	11	10	9	8
TX_SENT_CNT[15:8]

7	6	5	4	3	2	1	0
TX_SENT_CNT[7:0]

TX_SENT_CNT [read-only]: WR Streamer frame sent count
Number of sent wr streamer frames since reset

3.4. Rx statistics

HW prefix:	wr_transmission_rx_stat1
HW address:	0x3
C prefix:	RX_STAT1
C offset:	0xc

31	30	29	28	27	26	25	24
RX_RCVD_CNT[31:24]

23	22	21	20	19	18	17	16
RX_RCVD_CNT[23:16]

15	14	13	12	11	10	9	8
RX_RCVD_CNT[15:8]

7	6	5	4	3	2	1	0
RX_RCVD_CNT[7:0]

RX_RCVD_CNT [read-only]: WR Streamer frame received count
Number of received wr streamer frames since reset

3.5. Rx statistics

HW prefix:	wr_transmission_rx_stat2
HW address:	0x4
C prefix:	RX_STAT2
C offset:	0x10

31	30	29	28	27	26	25	24
RX_LOSS_CNT[31:24]

23	22	21	20	19	18	17	16
RX_LOSS_CNT[23:16]

15	14	13	12	11	10	9	8
RX_LOSS_CNT[15:8]

7	6	5	4	3	2	1	0
RX_LOSS_CNT[7:0]

RX_LOSS_CNT [read-only]: WR Streamer frame loss count
Number of lost wr streamer frames since reset

3.6. Rx statistics

HW prefix:	wr_transmission_rx_stat3
HW address:	0x5
C prefix:	RX_STAT3
C offset:	0x14

31	30	29	28	27	26	25	24
-	-	-	-	RX_LATENCY_MAX[27:24]

23	22	21	20	19	18	17	16
RX_LATENCY_MAX[23:16]

15	14	13	12	11	10	9	8
RX_LATENCY_MAX[15:8]

7	6	5	4	3	2	1	0
RX_LATENCY_MAX[7:0]

RX_LATENCY_MAX [read-only]: WR Streamer frame latency
Maximum latency of received frames since reset

3.7. Rx statistics

HW prefix:	wr_transmission_rx_stat4
HW address:	0x6
C prefix:	RX_STAT4
C offset:	0x18

31	30	29	28	27	26	25	24
-	-	-	-	RX_LATENCY_MIN[27:24]

23	22	21	20	19	18	17	16
RX_LATENCY_MIN[23:16]

15	14	13	12	11	10	9	8
RX_LATENCY_MIN[15:8]

7	6	5	4	3	2	1	0
RX_LATENCY_MIN[7:0]

RX_LATENCY_MIN [read-only]: WR Streamer frame latency
Minimum latency of received frames since reset

3.8. Rx statistics

HW prefix:	wr_transmission_rx_stat5
HW address:	0x7
C prefix:	RX_STAT5
C offset:	0x1c

31	30	29	28	27	26	25	24
RX_LATENCY_ACC_LSB[31:24]

23	22	21	20	19	18	17	16
RX_LATENCY_ACC_LSB[23:16]

15	14	13	12	11	10	9	8
RX_LATENCY_ACC_LSB[15:8]

7	6	5	4	3	2	1	0
RX_LATENCY_ACC_LSB[7:0]

RX_LATENCY_ACC_LSB [read-only]: WR Streamer frame latency
Accumulated latency (LSB) of received frames since reset

3.9. Rx statistics

HW prefix:	wr_transmission_rx_stat6
HW address:	0x8
C prefix:	RX_STAT6
C offset:	0x20

31	30	29	28	27	26	25	24
RX_LATENCY_ACC_MSB[31:24]

23	22	21	20	19	18	17	16
RX_LATENCY_ACC_MSB[23:16]

15	14	13	12	11	10	9	8
RX_LATENCY_ACC_MSB[15:8]

7	6	5	4	3	2	1	0
RX_LATENCY_ACC_MSB[7:0]

RX_LATENCY_ACC_MSB [read-only]: WR Streamer frame latency
Accumulated latency (MSB) of received frames since reset

3.10. Rx statistics

HW prefix:	wr_transmission_rx_stat7
HW address:	0x9
C prefix:	RX_STAT7
C offset:	0x24

31	30	29	28	27	26	25	24
RX_LATENCY_ACC_CNT[31:24]

23	22	21	20	19	18	17	16
RX_LATENCY_ACC_CNT[23:16]

15	14	13	12	11	10	9	8
RX_LATENCY_ACC_CNT[15:8]

7	6	5	4	3	2	1	0
RX_LATENCY_ACC_CNT[7:0]

RX_LATENCY_ACC_CNT [read-only]: WR Streamer frame latency counter
Counter of the accumulated frequency (so avg can be calculated in SW) since reset

3.11. Rx statistics

HW prefix:	wr_transmission_rx_stat8
HW address:	0xa
C prefix:	RX_STAT8
C offset:	0x28

31	30	29	28	27	26	25	24
RX_LOST_BLOCK_CNT[31:24]

23	22	21	20	19	18	17	16
RX_LOST_BLOCK_CNT[23:16]

15	14	13	12	11	10	9	8
RX_LOST_BLOCK_CNT[15:8]

7	6	5	4	3	2	1	0
RX_LOST_BLOCK_CNT[7:0]

RX_LOST_BLOCK_CNT [read-only]: WR Streamer block loss count
Number of indications that one or more blocks in a frame were lost (probably CRC
error) since reset

3.12. Tx Config Reg 0

HW prefix:	wr_transmission_tx_cfg0
HW address:	0xb
C prefix:	TX_CFG0
C offset:	0x2c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
ETHERTYPE[15:8]

7	6	5	4	3	2	1	0
ETHERTYPE[7:0]

ETHERTYPE [read/write]: Ethertype

3.13. Tx Config Reg 1

HW prefix:	wr_transmission_tx_cfg1
HW address:	0xc
C prefix:	TX_CFG1
C offset:	0x30

31	30	29	28	27	26	25	24
MAC_LOCAL_LSB[31:24]

23	22	21	20	19	18	17	16
MAC_LOCAL_LSB[23:16]

15	14	13	12	11	10	9	8
MAC_LOCAL_LSB[15:8]

7	6	5	4	3	2	1	0
MAC_LOCAL_LSB[7:0]

MAC_LOCAL_LSB [read/write]: MAC Local LSB

3.14. Tx Config Reg 2

HW prefix:	wr_transmission_tx_cfg2
HW address:	0xd
C prefix:	TX_CFG2
C offset:	0x34

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
MAC_LOCAL_MSB[15:8]

7	6	5	4	3	2	1	0
MAC_LOCAL_MSB[7:0]

MAC_LOCAL_MSB [read/write]: MAC Local MSB

3.15. Tx Config Reg 3

HW prefix:	wr_transmission_tx_cfg3
HW address:	0xe
C prefix:	TX_CFG3
C offset:	0x38

31	30	29	28	27	26	25	24
MAC_TARGET_LSB[31:24]

23	22	21	20	19	18	17	16
MAC_TARGET_LSB[23:16]

15	14	13	12	11	10	9	8
MAC_TARGET_LSB[15:8]

7	6	5	4	3	2	1	0
MAC_TARGET_LSB[7:0]

MAC_TARGET_LSB [read/write]: MAC Target LSB

3.16. Tx Config Reg 4

HW prefix:	wr_transmission_tx_cfg4
HW address:	0xf
C prefix:	TX_CFG4
C offset:	0x3c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
MAC_TARGET_MSB[15:8]

7	6	5	4	3	2	1	0
MAC_TARGET_MSB[7:0]

MAC_TARGET_MSB [read/write]: MAC Target MSB

3.17. Rx Config Reg 0

HW prefix:	wr_transmission_rx_cfg0
HW address:	0x10
C prefix:	RX_CFG0
C offset:	0x40

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	FILTER_REMOTE	ACCEPT_BROADCAST

15	14	13	12	11	10	9	8
ETHERTYPE[15:8]

7	6	5	4	3	2	1	0
ETHERTYPE[7:0]

ETHERTYPE [read/write]: Ethertype
ACCEPT_BROADCAST [read/write]: Accept Broadcast
0: accept only unicasts;
1: accept all broadcast packets
FILTER_REMOTE [read/write]: Filter Remote
0: accept streamer frames with any source MAC address;
1: accept streamer frames only with the source MAC address defined in mac_remote

3.18. Rx Config Reg 1

HW prefix:	wr_transmission_rx_cfg1
HW address:	0x11
C prefix:	RX_CFG1
C offset:	0x44

31	30	29	28	27	26	25	24
MAC_LOCAL_LSB[31:24]

23	22	21	20	19	18	17	16
MAC_LOCAL_LSB[23:16]

15	14	13	12	11	10	9	8
MAC_LOCAL_LSB[15:8]

7	6	5	4	3	2	1	0
MAC_LOCAL_LSB[7:0]

MAC_LOCAL_LSB [read/write]: MAC Local LSB

3.19. Rx Config Reg 2

HW prefix:	wr_transmission_rx_cfg2
HW address:	0x12
C prefix:	RX_CFG2
C offset:	0x48

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
MAC_LOCAL_MSB[15:8]

7	6	5	4	3	2	1	0
MAC_LOCAL_MSB[7:0]

MAC_LOCAL_MSB [read/write]: MAC Local MSB

3.20. Rx Config Reg 3

HW prefix:	wr_transmission_rx_cfg3
HW address:	0x13
C prefix:	RX_CFG3
C offset:	0x4c

31	30	29	28	27	26	25	24
MAC_REMOTE_LSB[31:24]

23	22	21	20	19	18	17	16
MAC_REMOTE_LSB[23:16]

15	14	13	12	11	10	9	8
MAC_REMOTE_LSB[15:8]

7	6	5	4	3	2	1	0
MAC_REMOTE_LSB[7:0]

MAC_REMOTE_LSB [read/write]: MAC Remote LSB

3.21. Rx Config Reg 4

HW prefix:	wr_transmission_rx_cfg4
HW address:	0x14
C prefix:	RX_CFG4
C offset:	0x50

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
MAC_REMOTE_MSB[15:8]

7	6	5	4	3	2	1	0
MAC_REMOTE_MSB[7:0]

MAC_REMOTE_MSB [read/write]: MAC Remote MSB

3.22. Rx Config Reg 5

HW prefix:	wr_transmission_rx_cfg5
HW address:	0x15
C prefix:	RX_CFG5
C offset:	0x54

31	30	29	28	27	26	25	24
-	-	-	-	FIXED_LATENCY[27:24]

23	22	21	20	19	18	17	16
FIXED_LATENCY[23:16]

15	14	13	12	11	10	9	8
FIXED_LATENCY[15:8]

7	6	5	4	3	2	1	0
FIXED_LATENCY[7:0]

FIXED_LATENCY [read/write]: Fixed Latency
This register allows to configure fixed-latency. If the value is other than zero, the instant of outputing the received data from the rx streamer to the user application is delayed, so that the time-difference between the transmission fo the data and the output to the user matches the provided value. If the configured latency value is smaller than the network latency, the data is provided to the user instantly. The configuration value is expressed in clock cycles (16ns)

3.23. TxRx Config Override

HW prefix:	wr_transmission_cfg
HW address:	0x16
C prefix:	CFG
C offset:	0x58

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	OR_RX_FIX_LAT	OR_RX_FTR_REMOTE	OR_RX_ACC_BROADCAST	OR_RX_MAC_REM	OR_RX_MAC_LOC	OR_RX_ETHERTYPE

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	OR_TX_MAC_TAR	OR_TX_MAC_LOC	OR_TX_ETHTYPE

OR_TX_ETHTYPE [read/write]: Tx Ethertype
Overrides default/application Tx Ethertype configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_TX_MAC_LOC [read/write]: Tx MAC Local
Overrides default/application Tx local MAC configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_TX_MAC_TAR [read/write]: Tx MAC Target
Overrides default/application Tx target MAC configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_RX_ETHERTYPE [read/write]: Rx Ethertype
Overrides default/application Rx Ethertype configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_RX_MAC_LOC [read/write]: Rx MAC Local
Overrides default/application Rx MAC Local configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_RX_MAC_REM [read/write]: Rx MAC Remote
Overrides default/application Rx MAC Remote configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_RX_ACC_BROADCAST [read/write]: Rx Accept Broadcast
Overrides default/application Rx Accept Broardcast configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_RX_FTR_REMOTE [read/write]: Rx Filter Remote
Overrides default/application Rx Filter Remote configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register
OR_RX_FIX_LAT [read/write]: Rx Fixed Latency
Overrides default/application Rx fixed latency configuration with configuration in the proper register:
0: Default/set by application;
1: Value from WB register

3.24. DBG Control register

HW prefix:	wr_transmission_dbg_ctrl
HW address:	0x17
C prefix:	DBG_CTRL
C offset:	0x5c

This register is meant to control simple debugging of transmitted or received data.
It allows to sniff a 32-bit word at a configurable offset from received or transmitted data.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
START_BYTE[7:0]

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	MUX

MUX [read/write]: Debug Tx (0) or Rx (1)
START_BYTE [read/write]: Debug Start byte
The offset, in bytes, from which the 32-bit word is read.

3.25. DBG Data

HW prefix:	wr_transmission_dbg_data
HW address:	0x18
C prefix:	DBG_DATA
C offset:	0x60

31	30	29	28	27	26	25	24
DBG_DATA[31:24]

23	22	21	20	19	18	17	16
DBG_DATA[23:16]

15	14	13	12	11	10	9	8
DBG_DATA[15:8]

7	6	5	4	3	2	1	0
DBG_DATA[7:0]

DBG_DATA [read-only]: Debug content

3.26. DBG RX_BVALUE

HW prefix:	wr_transmission_dbg_rx_bvalue
HW address:	0x19
C prefix:	DBG_RX_BVALUE
C offset:	0x64

31	30	29	28	27	26	25	24
DBG_RX_BVALUE[31:24]

23	22	21	20	19	18	17	16
DBG_RX_BVALUE[23:16]

15	14	13	12	11	10	9	8
DBG_RX_BVALUE[15:8]

7	6	5	4	3	2	1	0
DBG_RX_BVALUE[7:0]

DBG_RX_BVALUE [read-only]: Debug content

3.27. DBG tx bvalue

HW prefix:	wr_transmission_dbg_tx_bvalue
HW address:	0x1a
C prefix:	DBG_TX_BVALUE
C offset:	0x68

31	30	29	28	27	26	25	24
DBG_TX_BVALUE[31:24]

23	22	21	20	19	18	17	16
DBG_TX_BVALUE[23:16]

15	14	13	12	11	10	9	8
DBG_TX_BVALUE[15:8]

7	6	5	4	3	2	1	0
DBG_TX_BVALUE[7:0]

DBG_TX_BVALUE [read-only]: Debug content

3.28. Test value

HW prefix:	wr_transmission_dummy
HW address:	0x1b
C prefix:	DUMMY
C offset:	0x6c

31	30	29	28	27	26	25	24
DUMMY[31:24]

23	22	21	20	19	18	17	16
DUMMY[23:16]

15	14	13	12	11	10	9	8
DUMMY[15:8]

7	6	5	4	3	2	1	0
DUMMY[7:0]

DUMMY [read-only]: DUMMY value to read

wr_transmission_wb

WR Transmission control, status and debug

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