#
# Vivado (TM) v2016.4 (64-bit)
#
# wrc_board_fasec_ip.tcl: Tcl script for re-creating project 'wrc_board_fasec_ip'
#
# Generated by Vivado on Thu Aug 17 18:27:57 CEST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (wrc_board_fasec_ip.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/dmtd_with_deglitcher.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/dmtd_phase_meas.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_path.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_path.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_diags_wb.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
#    "/home/greg/wr/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/streamers_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/escape_detector.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_periph.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwb_fabric_sink.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/escape_inserter.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwb_fabric_source.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/dropping_buffer.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/pulse_stamper.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_mux.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wr_core.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xtx_streamer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xrx_streamer.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/xwr_core.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
#    "/home/greg/wr/wr-cores/board/common/wr_board_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/xwr_streamers.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
#    "/home/greg/wr/wr-cores/board/common/xwrc_board_common.vhd"
#    "/home/greg/wr/wr-cores/board/fasec/wr_fasec_pkg.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd"
#    "/home/greg/wr/wr-cores/board/fasec/xwrc_board_fasec.vhd"
#    "/home/greg/wr/wr-cores/board/fasec/wrc_board_fasec.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_free.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_msi.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_tlu/tlu_fsm.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_wb_event.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_tlu/tlu.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/rx_streamer.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_queue.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_auto_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_moving_average.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tag_channel.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_ac_wbm.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/pulse_gen.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_search.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_streamers/tx_streamer.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_tlu/tlu_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_channel.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_auto.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tlu.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_reg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_adder.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_piso_fifo.vhd"
#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_dpram.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tlu_auto.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_word_packer.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_sdp.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_data.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd"
#    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/matrix_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_big_adder.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_queue_auto.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_walker.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/wr_eca.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_offset.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_scan.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_scubus_channel.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_rmw.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd"
#    "/home/greg/wr/wr-cores/modules/timing/hpll_period_detect.vhd"
#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_internals_pkg.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tdp.vhd"
#    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
#    "/home/greg/wr/wr-cores/modules/wr_eca/eca_wr_time.vhd"
#    "/home/greg/wr/wr-cores/component.xml"
#    "/home/greg/wr/wr-cores/board/fasec/wrc_board_fasec_ip.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
#    <none>
#
#*****************************************************************************************

# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."

# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}

variable script_file
set script_file "wrc_board_fasec_ip.tcl"

# Help information for this script
proc help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}

if { $::argc > 0 } {
  for {set i 0} {$i < [llength $::argc]} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
      "--help"       { help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"

# Create project
create_project wrc_board_fasec_ip . -part xc7z030ffg676-2

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Reconstruct message rules
# None

# Set project properties
set obj [get_projects wrc_board_fasec_ip]
set_property "default_lib" "xil_defaultlib" $obj
set_property "ip_cache_permissions" "read write" $obj
set_property "ip_output_repo" "/home/greg/wr/wr-cores/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.cache/ip" $obj
set_property "part" "xc7z030ffg676-2" $obj
set_property "sim.ip.auto_export_scripts" "1" $obj
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "VHDL" $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../"]" $obj

# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"]"\
 "[file normalize "$origin_dir/../../modules/fabric/wr_fabric_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/endpoint_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_registers_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/endpoint_private_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_sync_detect.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_crc32_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_sync_detect_16bit.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_rtu_header_extract.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"]"\
 "[file normalize "$origin_dir/../../modules/timing/dmtd_with_deglitcher.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_autonegotiation.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_tx_crc_inserter.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_ts_counter.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_packet_filter.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_rx_crc_size_check.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_rx_wb_master.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd"]"\
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 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_piso_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wrc_core/wrc_dpram.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tlu_auto.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_word_packer.vhd"]"\
 "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_sdp.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_data.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd"]"\
 "[file normalize "$origin_dir/../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/matrix_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_big_adder.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_queue_auto.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_walker.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tlu_fsm.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"]"\
 "[file normalize "$origin_dir/../../platform/xilinx/chipscope/chipscope_icon.ngc"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/wr_eca.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_offset.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd"]"\
 "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_scan.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_scubus_channel.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_rmw.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tlu_auto_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_tbi_phy/wr_tbi_phy.vhd"]"\
 "[file normalize "$origin_dir/../../platform/xilinx/chipscope/chipscope_ila.ngc"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_queue_auto_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/timing/hpll_period_detect.vhd"]"\
 "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_si57x_interface/wr_si57x_interface.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_mini_nic/minic_packet_buffer.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_internals_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tdp.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_wr_time.vhd"]"\
 "[file normalize "$origin_dir/../../component.xml"]"\
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
# None

# Set 'sources_1' fileset file properties for local files
set file "genrams/genram_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wishbone/wishbone_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "genrams/memory_loader_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/generic_dpram_sameclock.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/generic_dpram_split.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/generic_dpram_dualclock.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fabric/wr_fabric_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/endpoint_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_registers_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_sync_register.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_sync_ffs.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gencores_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/generic_dpram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/endpoint_private_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/inferred_sync_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/inferred_async_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_pulse_synchronizer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "generic/generic_sync_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "generic/generic_async_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wbgen2/wbgen2_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/gc_shiftreg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_crc_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_sync_detect.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_uart/simple_uart_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_crc32_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_sync_detect_16bit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_extend_pulse.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rtu_header_extract.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/generic_simple_dpram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_uart/uart_async_tx.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "timing/dmtd_with_deglitcher.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_status_reg_insert.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_autonegotiation.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_crc_inserter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_ts_counter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_packet_filter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_pcs_16bit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_pulse_synchronizer2.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_crc_size_check.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_wb_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_pcs_8bit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_vlan_unit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_softpll_ng/spll_wbgen2_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_clock_alignment_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wbgen2/wbgen2_fifo_sync.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/generic_shiftreg_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wbgen2/wbgen2_eic.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_inject_ctrl.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_oob_insert.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_header_processor.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_pcs_8bit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_early_address_match.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wrc_diags_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_uart/uart_baud_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_vlan_unit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_hdr_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wrc_syscon_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_uart/uart_async_rx.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_pcs_16bit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_packet_injection.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_uart/simple_uart_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_mini_nic/minic_wbgen2_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_buffer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_softpll_ng/softpll_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_slave_adapter/wb_slave_adapter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_wishbone_controller.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "src/lm32_ram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_softpll_ng/spll_aligner.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "timing/dmtd_phase_meas.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wrcore_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_softpll_ng/spll_wb_slave.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "src/lm32_dp_ram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_leds_controller.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_tx_path.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_mini_nic/minic_wb_slave.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_path.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wrc_syscon_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wrc_diags_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_internals_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_1000basex_pcs.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_frequency_meter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_timestamping_unit.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_uart/wb_simple_uart.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_onewire_master/wb_onewire_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_pps_gen/pps_gen_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_pps_gen/wr_pps_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/wr_endpoint.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_crossbar/sdb_rom.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_crossbar/xwb_crossbar.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_uart/xwb_simple_uart.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/wr_streamers_wbgen2_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/xwr_syscon_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/streamers_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/xwrc_diags_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_softpll_ng/wr_softpll_ng.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_mini_nic/wr_mini_nic.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_onewire_master/xwb_onewire_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/xtx_streamers_stats.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_cfg_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/escape_detector.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_pass_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_slave_fsm.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wrc_periph.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/xrx_streamers_stats.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_softpll_ng/xwr_softpll_ng.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fabric/xwb_fabric_sink.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_pps_gen/xwr_pps_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_wbm_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/escape_inserter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_tag_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fabric/xwb_fabric_source.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/dropping_buffer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_commit_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_dpram/xwb_dpram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_mini_nic/xwr_mini_nic.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "generated/xwb_lm32.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_checksum.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "timing/pulse_stamper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fabric/xwrf_mux.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/xwr_endpoint.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/streamers_priv_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_tx_mux.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_crossbar/xwb_sdb_crossbar.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_stream_widen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_eth_rx.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wr_core.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_slave_top.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_stream_narrow.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/xrtx_streamers_stats.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_tbi_phy/disparity_gen_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/xtx_streamer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/wr_streamers_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/etherbone_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/gtp_phase_align.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_eth_tx.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/gtp_bitslide.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/xrx_streamer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_axi4lite_bridge/axi4_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/wr_xilinx_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/wr_gtx_phy_kintex7.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/wr_gtp_phy_spartan6.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/xwr_core.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_dacs/spec_serial_dac.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/wr_board_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_ethernet_slave.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/xwr_streamers.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_dacs/spec_serial_dac_arb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/xwrc_board_common.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fasec/wr_fasec_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/xwrc_platform_xilinx.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_reset.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_axi4lite_bridge/wb_axi4lite_bridge.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fasec/xwrc_board_fasec.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fasec/wrc_board_fasec.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/xvme64x_core_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_free.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_usb_core/ez_usb_fifos.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_spi/xwb_spi.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_simple_timer/wb_tics.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_msi.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_tlu/tlu_fsm.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/l2p_ser.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_irq/wb_irq_timer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_ac_wbm_auto.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/xvme64x_core.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_bus.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_wb_event.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_irq/wb_irq_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_raw_slave.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_Am_Match.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_i2c_master/wb_i2c_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_async_signals_input_stage.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_tlu/tlu.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_simple_pwm/wb_simple_pwm.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/rx_streamer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xilinx/generic_spram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/serdes_n_to_1_s2_se.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_fsm_watchdog.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_rr_arbiter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_dma/xwb_dma.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_CRAM.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_queue.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_auto_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xwrf_loopback/lbk_wishbone_controller.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_serial_lcd/wb_serial_lcd.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_master_core/eb_framer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_moving_average.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_master_core/eb_commit_len_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_tag_channel.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_CSR_pack.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_serial_dac.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_si57x_interface/xwr_si57x_interface.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_tbi_phy/dec_8b10b.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_tbi_phy/enc_8b10b.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/pulse_sync_rtl.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wbgen2/wbgen2_fifo_async.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_gpio_port/xwb_gpio_port.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_prio_encoder.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_usb_core/ez_usb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_master_core/eb_master_eth_tx.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_gpio_port/wb_gpio_port.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xwrf_loopback/lbk_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/gn4124_core_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_usb_core/ez_usb_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_CR_pack.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_ac_wbm_auto_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/p2l_dma_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_si57x_interface/si570_if_wbgen2_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_irq/wb_irq_lm32.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_Funct_Match.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xil_multiboot/multiboot_fsm.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_master_core/eb_master_top.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_arbitrated_mux.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_vic/xwb_vic.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_i2c_bridge/wb_i2c_bridge.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_crossbar/xwb_register_link.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/dma_controller.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_softpll_ng/spll_period_detect.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_ac_wbm.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/wr_gtx_phy_virtex6.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "timing/pulse_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/gn4124_core.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_CR_CSR_Space.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_single_reset_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_bicolor_led_ctrl.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_search.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/dma_controller_wb_slave.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_i2c_master/xwb_i2c_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_endpoint/ep_rx_bypass_queue.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_streamers/tx_streamer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_master_core/eb_master_slave_wrapper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xwrf_loopback/wrf_loopback.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_tlu/tlu_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_async_bridge/xwb_async_bridge.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_bus_fanout/xwb_bus_fanout.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_simple_pwm/xwb_simple_pwm.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "timing/multi_dmtd_with_deglitcher.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_master_core/eb_master_wb_if.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_channel.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xilinx_fpga_loader/xloader_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_auto.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_tlu.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_i2c_master/i2c_master_byte_ctrl.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "fabric/xwrf_reg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_si57x_interface/si570_if_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_adder.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_SharedComps.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_irq/wb_irq_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_piso_fifo.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wrc_core/wrc_dpram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/vme64x_pack.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "ip_cores/l2p_fifo.ngc"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "NGC" $file_obj

set file "wbgen2/wbgen2_dpssram.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_tlu_auto.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_dual_pi_controller.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_glitch_filt.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/l2p_dma_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_word_packer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_i2c_slave.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_vic/wb_slave_vic.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_Init.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_sdp.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_data.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_crossbar/wb_skidpad.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "xwrf_loopback/xwrf_loopback.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_irq/wb_irq_slave.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/serdes_n_to_1_s2_diff.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/matrix_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xil_multiboot/xwb_xil_multiboot.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_big_adder.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_queue_auto.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_i2c_master/i2c_master_bit_ctrl.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_simple_timer/xwb_tics.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_walker.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wbgenplus/wbgenplus_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_Wb_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/p2l_des.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_tlu_fsm.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_master_core/eb_record_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "chipscope/chipscope_icon.ngc"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "NGC" $file_obj

set file "rtl/l2p_arbiter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_dma/xwb_streamer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/wr_eca.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_offset.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_dyn_glitch_filt.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_simple_pwm/simple_pwm_wb.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME64xCore_Top.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/gtx_reset.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_async_bridge/wb_async_bridge.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_scan.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/wbmaster32.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_scubus_channel.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_Access_Decode.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_irq/irqm_core.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_clock_crossing/xwb_clock_crossing.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_rmw.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xil_multiboot/multiboot_regs.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_spi/wb_spi.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_IRQ_Controller.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_tlu_auto_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_tbi_phy/wr_tbi_phy.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "chipscope/chipscope_ila.ngc"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "NGC" $file_obj

set file "wr_eca/eca_queue_auto_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "timing/hpll_period_detect.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_gtp_phy/gtp_phase_align_virtex6.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_spi_flash/wb_spi_flash.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/p2l_decode32.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_si57x_interface/wr_si57x_interface.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "common/gc_delay_gen.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_mini_nic/minic_packet_buffer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_internals_pkg.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_xil_multiboot/spi_master.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "eb_slave_core/eb_slave_core.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "spartan6/serdes_1_to_n_data_s2_se.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "rtl/VME_swapper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_vic/wb_vic.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_i2c_master/i2c_master_top.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_tdp.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wb_vic/vic_prio_enc.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr_eca/eca_wr_time.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "wr-cores/component.xml"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "IP-XACT" $file_obj


# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property "top" "wrc_board_fasec" $obj

# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}

# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/../../board/fasec/wrc_board_fasec_ip.xdc"]"
set file_added [add_files -norecurse -fileset $obj $file]
set file "fasec/wrc_board_fasec_ip.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property "file_type" "XDC" $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]

# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}

# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property "top" "gn4124_core" $obj
set_property "transport_int_delay" "0" $obj
set_property "transport_path_delay" "0" $obj
set_property "xelab.nosort" "1" $obj
set_property "xelab.unifast" "" $obj

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
  create_run -name synth_1 -part xc7z030ffg676-2 -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  set_property flow "Vivado Synthesis 2016" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property "part" "xc7z030ffg676-2" $obj

# set the current synth run
current_run -synthesis [get_runs synth_1]

# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
  create_run -name impl_1 -part xc7z030ffg676-2 -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
  set_property flow "Vivado Implementation 2016" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property "part" "xc7z030ffg676-2" $obj
set_property "steps.write_bitstream.args.readback_file" "0" $obj
set_property "steps.write_bitstream.args.verbose" "0" $obj

# set the current impl run
current_run -implementation [get_runs impl_1]

puts "INFO: Project created:wrc_board_fasec_ip"
