--! @file        eca_tlu_auto_pkg.vhd
--  DesignUnit   eca_tlu_auto
--! @author      Wesley W. Terpstra <w.terpstra@gsi.de>
--! @date        15/04/2016
--! @version     2.0
--! @copyright   2016 GSI Helmholtz Centre for Heavy Ion Research GmbH
--!

--! @brief AUTOGENERATED WISHBONE-SLAVE PACKAGE FOR eca_tlu.vhd
--!
--------------------------------------------------------------------------------
--! This library is free software; you can redistribute it and/or
--! modify it under the terms of the GNU Lesser General Public
--! License as published by the Free Software Foundation; either
--! version 3 of the License, or (at your option) any later version.
--!
--! This library is distributed in the hope that it will be useful,
--! but WITHOUT ANY WARRANTY; without even the implied warranty of
--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--! Lesser General Public License for more details.
--!
--! You should have received a copy of the GNU Lesser General Public
--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------

-- ***********************************************************
-- ** WARNING - THIS IS AUTO-GENERATED CODE! DO NOT MODIFY! **
-- ***********************************************************
--
-- If you want to change the interface,
-- modify eca_tlu.xml and re-run 'python wbgenplus.py eca_tlu.xml' !

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wbgenplus_pkg.all;
use work.genram_pkg.all;
package eca_tlu_auto_pkg is

  constant c_num_inputs_GET   : natural := 16#00#;  -- ro,  8 b, Total number of inputs attached to the TLU
  constant c_input_select_RW  : natural := 16#04#;  -- rw,  8 b, Write the configuration of this input
  constant c_enable_RW        : natural := 16#08#;  -- rw,  1 b, Will this input generate timing events on an edge
  constant c_stable_RW        : natural := 16#0c#;  -- rw, 32 b, Signal must be high/low for stable cycles to be counted as a valid transition
  constant c_event_hi_RW      : natural := 16#10#;  -- rw, 32 b, Timing Event to generate (high word)
  constant c_event_lo_RW      : natural := 16#14#;  -- rw, 32 b, Timing Event to generate (low word), lowest bit is replaced with the edge of the transition
  constant c_write_OWR        : natural := 16#18#;  -- wo,  1 b, Write register contents to TLU configuration

  --| Component ----------------------- eca_tlu_auto ------------------------------------------|
  component eca_tlu_auto is
  generic(
    g_num_inputs  : natural := 0  --Total number of inputs attached to the TLU
  );
  Port(
    clk_sys_i       : std_logic;                            -- Clock input for sys domain
    rst_sys_n_i     : std_logic;                            -- Reset input (active low) for sys domain
    error_i         : in  std_logic_vector(1-1 downto 0);   -- Error control
    stall_i         : in  std_logic_vector(1-1 downto 0);   -- flow control
    enable_o        : out std_logic_vector(1-1 downto 0);   -- Will this input generate timing events on an edge
    event_hi_o      : out std_logic_vector(32-1 downto 0);  -- Timing Event to generate (high word)
    event_lo_o      : out std_logic_vector(32-1 downto 0);  -- Timing Event to generate (low word), lowest bit is replaced with the edge of the transition
    input_select_o  : out std_logic_vector(8-1 downto 0);   -- Write the configuration of this input
    stable_o        : out std_logic_vector(32-1 downto 0);  -- Signal must be high/low for stable cycles to be counted as a valid transition
    write_o         : out std_logic_vector(1-1 downto 0);   -- Write register contents to TLU configuration
    
    slave_i         : in  t_wishbone_slave_in;
    slave_o         : out t_wishbone_slave_out

    
  );
  end component;

  constant c_eca_tlu_slave_sdb : t_sdb_device := (
  abi_class     => x"0000", -- undocumented device
  abi_ver_major => x"01",
  abi_ver_minor => x"00",
  wbd_endian    => c_sdb_endian_big,
  wbd_width     => x"7", -- 8/16/32-bit port granularity
  sdb_component => (
  addr_first    => x"0000000000000000",
  addr_last     => x"000000000000001f",
  product => (
  vendor_id     => x"0000000000000651",
  device_id     => x"7c82afbc",
  version       => x"00000020",
  date          => x"20160415",
  name          => "ECA_UNIT:TLU       ")));

end eca_tlu_auto_pkg;
package body eca_tlu_auto_pkg is
end eca_tlu_auto_pkg;
