lbk_wishbone_controller

WRF Loopback

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Main Control Register
3.2. Forced Destination MAC [3:0]
3.3. Forced Destination MAC [5:4]
3.4. Received frames counter
3.5. Dropped frames counter
3.6. Forwarded frames counter

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Main Control Register lbk_mcr MCR
0x1 REG Forced Destination MAC [3:0] lbk_dmac_l DMAC_L
0x2 REG Forced Destination MAC [5:4] lbk_dmac_h DMAC_H
0x3 REG Received frames counter lbk_rcv_cnt RCV_CNT
0x4 REG Dropped frames counter lbk_drp_cnt DRP_CNT
0x5 REG Forwarded frames counter lbk_fwd_cnt FWD_CNT

2. HDL symbol

→ rst_n_i Main Control Register:
→ clk_sys_i lbk_mcr_ena_o →
⇒ wb_adr_i[2:0] lbk_mcr_clr_o →
⇒ wb_dat_i[31:0] lbk_mcr_fdmac_o →
⇐ wb_dat_o[31:0]  
→ wb_cyc_i Forced Destination MAC [3:0]:
⇒ wb_sel_i[3:0] lbk_dmac_l_o[31:0] ⇒
→ wb_stb_i lbk_dmac_l_i[31:0] ⇐
→ wb_we_i lbk_dmac_l_load_o →
← wb_ack_o  
← wb_stall_o Forced Destination MAC [5:4]:
lbk_dmac_h_o[15:0] ⇒
lbk_dmac_h_i[15:0] ⇐
lbk_dmac_h_load_o →
 
Received frames counter:
lbk_rcv_cnt_o[31:0] ⇒
lbk_rcv_cnt_i[31:0] ⇐
lbk_rcv_cnt_load_o →
 
Dropped frames counter:
lbk_drp_cnt_o[31:0] ⇒
lbk_drp_cnt_i[31:0] ⇐
lbk_drp_cnt_load_o →
 
Forwarded frames counter:
lbk_fwd_cnt_o[31:0] ⇒
lbk_fwd_cnt_i[31:0] ⇐
lbk_fwd_cnt_load_o →

3. Register description

3.1. Main Control Register

HW prefix: lbk_mcr
HW address: 0x0
C prefix: MCR
C offset: 0x0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - FDMAC CLR ENA

3.2. Forced Destination MAC [3:0]

HW prefix: lbk_dmac_l
HW address: 0x1
C prefix: DMAC_L
C offset: 0x4
31 30 29 28 27 26 25 24
DMAC_L[31:24]
23 22 21 20 19 18 17 16
DMAC_L[23:16]
15 14 13 12 11 10 9 8
DMAC_L[15:8]
7 6 5 4 3 2 1 0
DMAC_L[7:0]

3.3. Forced Destination MAC [5:4]

HW prefix: lbk_dmac_h
HW address: 0x2
C prefix: DMAC_H
C offset: 0x8
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
DMAC_H[15:8]
7 6 5 4 3 2 1 0
DMAC_H[7:0]

3.4. Received frames counter

HW prefix: lbk_rcv_cnt
HW address: 0x3
C prefix: RCV_CNT
C offset: 0xc
31 30 29 28 27 26 25 24
RCV_CNT[31:24]
23 22 21 20 19 18 17 16
RCV_CNT[23:16]
15 14 13 12 11 10 9 8
RCV_CNT[15:8]
7 6 5 4 3 2 1 0
RCV_CNT[7:0]

3.5. Dropped frames counter

HW prefix: lbk_drp_cnt
HW address: 0x4
C prefix: DRP_CNT
C offset: 0x10
31 30 29 28 27 26 25 24
DRP_CNT[31:24]
23 22 21 20 19 18 17 16
DRP_CNT[23:16]
15 14 13 12 11 10 9 8
DRP_CNT[15:8]
7 6 5 4 3 2 1 0
DRP_CNT[7:0]

3.6. Forwarded frames counter

HW prefix: lbk_fwd_cnt
HW address: 0x5
C prefix: FWD_CNT
C offset: 0x14
31 30 29 28 27 26 25 24
FWD_CNT[31:24]
23 22 21 20 19 18 17 16
FWD_CNT[23:16]
15 14 13 12 11 10 9 8
FWD_CNT[15:8]
7 6 5 4 3 2 1 0
FWD_CNT[7:0]