#   ---------------------------------------------------------------------------`
#   -- Clocks/resets
#   ---------------------------------------------------------------------------

#   -- Local oscillators
NET "clk_125m_dmtd_p_i" LOC = J19  | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V -- CVPD-922-124.992 MHz PLL reference
NET "clk_125m_dmtd_n_i" LOC = H19  | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V
#NET "clk_125m_dmtd_p_i" LOC = K18  | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V -- FRETHE025 5x25 MHz PLL reference
#NET "clk_125m_dmtd_n_i" LOC = K19  | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V
NET "clk_125m_dmtd_p_i" TNM_NET = clk_125m_dmtd_p_i;
TIMESPEC TS_dmtd_clk_p_i = PERIOD "clk_125m_dmtd_p_i" 8 ns HIGH 50%;
NET "clk_125m_dmtd_n_i" TNM_NET = clk_125m_dmtd_n_i;
TIMESPEC TS_dmtd_clk_n_i = PERIOD "clk_125m_dmtd_n_i" 8 ns HIGH 50%;

NET "clk_125m_gtp_p_i"  LOC = F6   | IOSTANDARD = "LVDS_25"; #Bank 216 -- 125.000 MHz GTP reference
NET "clk_125m_gtp_n_i"  LOC = E6   | IOSTANDARD = "LVDS_25"; #Bank 216
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;

#   ---------------------------------------------------------------------------
#   -- SPI interface to DACs
#   ---------------------------------------------------------------------------

NET "dac_dmtd_din_o"    LOC = G21  | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_dmtd_sclk_o"   LOC = G22  | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_dmtd_cs_n_o"   LOC = D22  | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_din_o"  LOC = E21  | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_sclk_o" LOC = D21  | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_cs_n_o" LOC = B22  | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- SFP I/O for transceiver
#   ---------------------------------------------------------------------------

NET "sfp_txp_o"             LOC = B4;                           #Bank 216
NET "sfp_txn_o"             LOC = A4;                           #Bank 216
NET "sfp_rxp_i"             LOC = B8;                           #Bank 216
NET "sfp_rxn_i"             LOC = A8;                           #Bank 216
NET "sfp_mod_def0_i"        LOC = W17  | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V  -- sfp detect
NET "sfp_mod_def1_b"        LOC = AA18 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V  -- scl
NET "sfp_mod_def2_b"        LOC = AB18 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V  -- sda
NET "sfp_rate_select_o"     LOC = AB20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_fault_i"        LOC = R19  | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_disable_o"      LOC = P19  | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_los_i"             LOC = V17  | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- Onewire interface
#   ---------------------------------------------------------------------------

NET "onewire_b" LOC = P16 | IOSTANDARD = LVCMOS33;    #Bank 14 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- UART
#   ---------------------------------------------------------------------------

#TEST & DEBUG
# Signal USB_TX is an output in the design and must be connected to pin 20/12 (RXD_I) of U26 (CP2105GM)
# Signal USB_RX is an input in the design and must be connected to pin 21/13 (TXD_O) of U26 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
NET "uart_rxd_i"            LOC = W6   | IOSTANDARD = LVCMOS25 | PULLDOWN;           #Bank 34 VCCO - 1.8 V
NET "uart_txd_o"            LOC = W5   | IOSTANDARD = LVCMOS25;                      #Bank 34 VCCO - 1.8 V
#NET "USB_RX2"               LOC = U6   | IOSTANDARD = LVCMOS25 | PULLDOWN;           #Bank 34 VCCO - 1.8 V
#NET "USB_TX2"               LOC = V5   | IOSTANDARD = LVCMOS25;                      #Bank 34 VCCO - 1.8 V
#USB Connection on Test&Debug Connector (J20)
#NET "USBEXT_RX1"            LOC = D19  | IOSTANDARD = LVCMOS33 | PULLDOWN;           #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX1"            LOC = E19  | IOSTANDARD = LVCMOS33;                      #Bank 16 VCCO - 3.3 V
#NET "USBEXT_RX2"            LOC = F19  | IOSTANDARD = LVCMOS33 | PULLDOWN;           #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX2"            LOC = F20  | IOSTANDARD = LVCMOS33;                      #Bank 16 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- Flash memory SPI interface
#   ---------------------------------------------------------------------------

#    flash_sclk_o : out std_logic;
#    flash_ncs_o  : out std_logic;
#    flash_mosi_o : out std_logic;
#    flash_miso_i : in  std_logic;

#   ---------------------------------------------------------------------------
#   -- Miscellanous CLBv3 pins
#   ---------------------------------------------------------------------------

#NET "GPIO_LED[0]" LOC = T20  | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V
NET "led_act_o"   LOC = T20  | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[1]" LOC = W21  | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[2]" LOC = W22  | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[3]" LOC = Y21  | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[4]" LOC = AA21 | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[5]" LOC = AA20 | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V
NET "led_link_o"  LOC = AA20 | IOSTANDARD = LVCMOS33;  #Bank 14 VCCO - 3.3 V


NET "reset_i"     LOC = C18  | IOSTANDARD = LVCMOS33;  #Bank 16 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- Digital I/O FMC Pins
#   -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
#   -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
#   ---------------------------------------------------------------------------

#   -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
#   -- external reference input.
NET "dio_clk_p_i" LOC = R4       | IOSTANDARD=LVDS_25;  #CLK1_M2C_P
NET "dio_clk_n_i" LOC = T4       | IOSTANDARD=LVDS_25;  #CLK1_M2C_N

#   -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
#   -- the mezzanine front panel.
NET "dio_p_i[4]" LOC = J22        | IOSTANDARD=LVDS_25;  #LA00_P 
NET "dio_n_i[4]" LOC = H22        | IOSTANDARD=LVDS_25;  #LA00_N 
NET "dio_p_i[3]" LOC = M13        | IOSTANDARD=LVDS_25;  #LA03_P 
NET "dio_n_i[3]" LOC = L13        | IOSTANDARD=LVDS_25;  #LA03_N 
NET "dio_p_i[2]" LOC = T16        | IOSTANDARD=LVDS_25;  #LA16_P 
NET "dio_n_i[2]" LOC = U16        | IOSTANDARD=LVDS_25;  #LA16_N 
NET "dio_p_i[1]" LOC = AA10       | IOSTANDARD=LVDS_25;  #LA20_P 
NET "dio_n_i[1]" LOC = AA11       | IOSTANDARD=LVDS_25;  #LA20_N 
NET "dio_p_i[0]" LOC = R6         | IOSTANDARD=LVDS_25;  #LA33_P 
NET "dio_n_i[0]" LOC = T6         | IOSTANDARD=LVDS_25;  #LA33_N 

#   -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
#   -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
#   -- of I/O (N+1) on the front panel of the mezzanine
NET "dio_p_o[4]" LOC = M18        | IOSTANDARD=LVDS_25;  #LA04_P
NET "dio_n_o[4]" LOC = L18        | IOSTANDARD=LVDS_25;  #LA04_N
NET "dio_p_o[3]" LOC = N20        | IOSTANDARD=LVDS_25;  #LA07_P
NET "dio_n_o[3]" LOC = M20        | IOSTANDARD=LVDS_25;  #LA07_N
NET "dio_p_o[2]" LOC = N22        | IOSTANDARD=LVDS_25;  #LA08_P
NET "dio_n_o[2]" LOC = M22        | IOSTANDARD=LVDS_25;  #LA08_N
NET "dio_p_o[1]" LOC = AA9        | IOSTANDARD=LVDS_25;  #LA28_P
NET "dio_n_o[1]" LOC = AB10       | IOSTANDARD=LVDS_25;  #LA28_N
NET "dio_p_o[0]" LOC = W11        | IOSTANDARD=LVDS_25;  #LA29_P
NET "dio_n_o[0]" LOC = W12        | IOSTANDARD=LVDS_25;  #LA29_N

#   -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
#   -- panel is configured as an output.
NET "dio_oe_n_o[4]" LOC = V10     | IOSTANDARD=LVCMOS25; #LA05_P
NET "dio_oe_n_o[3]" LOC = M15     | IOSTANDARD=LVCMOS25; #LA11_P
NET "dio_oe_n_o[2]" LOC = W16     | IOSTANDARD=LVCMOS25; #LA15_N
NET "dio_oe_n_o[1]" LOC = AB13    | IOSTANDARD=LVCMOS25; #LA24_N
NET "dio_oe_n_o[0]" LOC = G17     | IOSTANDARD=LVCMOS25; #LA30_P

#   -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
#   -- panel is 50-ohm terminated
NET "dio_term_en_o[4]" LOC = V14  | IOSTANDARD=LVCMOS25; #LA09_N
NET "dio_term_en_o[3]" LOC = V13  | IOSTANDARD=LVCMOS25; #LA09_P
NET "dio_term_en_o[2]" LOC = W10  | IOSTANDARD=LVCMOS25; #LA05_N
NET "dio_term_en_o[1]" LOC = Y12  | IOSTANDARD=LVCMOS25; #LA06_N
NET "dio_term_en_o[0]" LOC = G18  | IOSTANDARD=LVCMOS25; #LA30_N

#    -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
#    -- blink 1-PPS.
NET "dio_led_top_o" LOC = AB11     | IOSTANDARD=LVCMOS25; #LA01_P
NET "dio_led_bot_o" LOC = AB12     | IOSTANDARD=LVCMOS25; #LA01_N

#   -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
#   -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
NET "dio_scl_b" LOC = P17         | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "dio_sda_b" LOC = N17         | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- Bulls-eye connector outputs
#   ---------------------------------------------------------------------------

NET "txts_p_o" LOC = H13          | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 1
NET "txts_n_o" LOC = G13          | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 2

NET "rxts_p_o" LOC = G15          | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 3
NET "rxts_n_o" LOC = G16          | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 4

NET "pps_p_o" LOC = J15           | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 5
NET "pps_n_o" LOC = H15           | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 6

NET "clk_ref_62m5_p_o" LOC = H17  | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 7
NET "clk_ref_62m5_n_o" LOC = H18  | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 8

NET "clk_dmtd_62m5_p_o" LOC = K21 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 12
NET "clk_dmtd_62m5_n_o" LOC = K22 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 13

#   ---------------------------------------------------------------------------
#   -- GPIO connector
#   ---------------------------------------------------------------------------
#NET "GPIO[1]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[2]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[3]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[4]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[5]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[6]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[7]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[8]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[9]"  LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[10]" LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[11]" LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[12]" LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[13]" LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[14]" LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[15]" LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V
#NET "GPIO[16]" LOC =  | IOSTANDARD = LVCMOS??;    #Bank ?? VCCO - ?.? V

#FMC SIGNALS CLK LPC
#NET "FMC_CLK0_M2C_P" LOC = T5    | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK0_M2C_N" LOC = U5    | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_P" LOC = R4    | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_N" LOC = T4    | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 34 VCCO - 2.5 V
#NET "FMC_LA00_CC_P"  LOC = J22   | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 1
#NET "FMC_LA00_CC_N"  LOC = H22   | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 3
#NET "FMC_LA01_CC_P"  LOC = AB11  | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 5
#NET "FMC_LA01_CC_N"  LOC = AB12  | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 7
#NET "FMC_LA17_CC_P"  LOC = J20   | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 30
#NET "FMC_LA17_CC_N"  LOC = J21   | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 32 *
#NET "FMC_LA18_CC_P"  LOC = L19   | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 34 *
#NET "FMC_LA18_CC_N"  LOC = L20   | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 36 *

########################################################

#FMC SIGNALS LPC
#NET "FMC_PRSNT_B"    LOC = W20   | IOSTANDARD = LVCMOS33;                        #Bank 14 VCCO - 3.3 V
#NET "FMC_LA02_P"     LOC = K17   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 9 *
#NET "FMC_LA02_N"     LOC = J17   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 11 *
#NET "FMC_LA03_P"     LOC = M13   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 13
#NET "FMC_LA03_N"     LOC = L13   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 15
#NET "FMC_LA04_P"     LOC = M18   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 17
#NET "FMC_LA04_N"     LOC = L18   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 19
#NET "FMC_LA05_P"     LOC = V10   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 21
#NET "FMC_LA05_N"     LOC = W10   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 23
#NET "FMC_LA06_P"     LOC = Y11   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 25 *
#NET "FMC_LA06_N"     LOC = Y12   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 27
#NET "FMC_LA07_P"     LOC = N20   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 29
#NET "FMC_LA07_N"     LOC = M20   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 31
#NET "FMC_LA08_P"     LOC = N22   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 33
#NET "FMC_LA08_N"     LOC = M22   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 35
#NET "FMC_LA09_P"     LOC = V13   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 37
#NET "FMC_LA09_N"     LOC = V14   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 39
#NET "FMC_LA10_P"     LOC = W14   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 2 *
#NET "FMC_LA10_N"     LOC = Y14   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 4 *
#NET "FMC_LA11_P"     LOC = M15   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 6
#NET "FMC_LA11_N"     LOC = M16   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 8 *
#NET "FMC_LA12_P"     LOC = N18   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 10 *
#NET "FMC_LA12_N"     LOC = N19   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V  FMC_XM105 J1 pin 12 *
#NET "FMC_LA13_P"     LOC = U15   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 14 *
#NET "FMC_LA13_N"     LOC = V15   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 16 *
#NET "FMC_LA14_P"     LOC = T14   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 18 *
#NET "FMC_LA14_N"     LOC = T15   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 20 *
#NET "FMC_LA15_P"     LOC = W15   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 22 *
#NET "FMC_LA15_N"     LOC = W16   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 24
#NET "FMC_LA16_P"     LOC = T16   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 26
#NET "FMC_LA16_N"     LOC = U16   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 28
#NET "FMC_LA19_P"     LOC = Y16   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 38 *
#NET "FMC_LA19_N"     LOC = AA16  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 40 *
#NET "FMC_LA20_P"     LOC = AA10  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA20_N"     LOC = AA11  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_P"     LOC = Y13   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_N"     LOC = AA14  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_P"     LOC = AB16  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_N"     LOC = AB17  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA23_P"     LOC = K13   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA23_N"     LOC = K14   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA24_P"     LOC = AA13  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_N"     LOC = AB13  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_P"     LOC = AA15  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_N"     LOC = AB15  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_P"     LOC = L14   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA26_N"     LOC = L15   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA27_P"     LOC = L16   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA27_N"     LOC = K16   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA28_P"     LOC = AA9   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA28_N"     LOC = AB10  | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_P"     LOC = W11   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_N"     LOC = W12   | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_P"     LOC = G17   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA30_N"     LOC = G18   | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA31_P"     LOC = R3    | IOSTANDARD = LVCMOS25;    #Bank 34 VCCO - 2.5 V
#NET "FMC_LA31_N"     LOC = R2    | IOSTANDARD = LVCMOS25;    #Bank 34 VCCO - 2.5 V
#NET "FMC_LA32_P"     LOC = W2    | IOSTANDARD = LVCMOS25;    #Bank 34 VCCO - 2.5 V
#NET "FMC_LA32_N"     LOC = Y2    | IOSTANDARD = LVCMOS25;    #Bank 34 VCCO - 2.5 V
#NET "FMC_LA33_P"     LOC = R6    | IOSTANDARD = LVCMOS25;    #Bank 34 VCCO - 2.5 V
#NET "FMC_LA33_N"     LOC = T6    | IOSTANDARD = LVCMOS25;    #Bank 34 VCCO - 2.5 V

#OCTOPUS SMALL
#NET "IIC1_SDA"       LOC =       | IOSTANDARD = LVCMOS33;    #Bank ?? VCCO - ?.? V
#NET "IIC1_SCL"       LOC =       | IOSTANDARD = LVCMOS33;    #Bank ?? VCCO - ?.? V
#NET "EN_SCLK"        LOC =       | IOSTANDARD = LVCMOS33;    #Bank ?? VCCO - ?.? V
#NET "PMT_P[0]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[0]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[1]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[1]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[2]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[2]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[3]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[3]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[4]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[4]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[5]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[5]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[6]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[6]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[7]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[7]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[8]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[8]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[9]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[9]"       LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[10]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[10]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_P[11]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "PMT_N[11]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA0P"     LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA0N"     LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA1P"     LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA1N"     LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA2P"     LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V
#NET "SPMT_SPA2N"     LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank ?? VCCO - ?.? V

#OCTOPUS LARGE
#NET "IIC2_SDA"       LOC =       | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - ?.? V
#NET "IIC2_SCL"       LOC =       | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - ?.? V
#NET "EN_LCLK"        LOC =       | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - ?.? V
#NET "PMT_P[12]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[12]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[13]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[13]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[14]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[14]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[15]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[15]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[16]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[16]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[17]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[17]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[18]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[18]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[19]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[19]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[20]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[20]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[21]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[21]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[22]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[22]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[23]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[23]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[24]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[24]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[25]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[25]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[26]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[26]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[27]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[27]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[28]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[28]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[29]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[29]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_P[30]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
#NET "PMT_N[30]"      LOC =       | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank ?? VCCO - ?.? V
                                                                        