<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>CERN</spirit:vendor>
  <spirit:library>white_rabbit</spirit:library>
  <spirit:name>wrc_board_fasec</spirit:name>
  <spirit:version>4.2</spirit:version>
  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>s00_axi</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="s00_axi"/>
      </spirit:slave>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_awaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_awvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_awready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_wdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WSTRB</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_wstrb</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_wvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_wready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_bresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_bvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_bready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_araddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_arvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ARREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_arready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_rdata</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RRESP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_rresp</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_rlast</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_rvalid</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_rready</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:description>Clock frequency (Hertz)</spirit:description>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ">62500000</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>s00_axi_aresetn</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_aresetn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>s00_axi_aclk_o</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>s00_axi_aclk_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ACLK_O.ASSOCIATED_BUSIF">s00_axi</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ACLK_O.FREQ_HZ">62500000</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ACLK_O.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>SFP</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="sfp" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="sfp_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TX_DISABLE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_tx_disable_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RX_LOS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_los_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RXN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_rx_n_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TXN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_tx_n_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RXP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_rx_p_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TX_FAULT</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_tx_fault_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>MOD_ABS</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_det_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TXP</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_tx_p_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>UART</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TxD</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>uart_txd_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RxD</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>uart_rxd_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>sfp_i2c</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_scl_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_sda_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_sda_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_sda_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_scl_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sfp_scl_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>eeprom_i2c</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>eeprom_scl_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>eeprom_sda_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>eeprom_sda_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>eeprom_sda_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>eeprom_scl_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>eeprom_scl_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>thermo_id</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TRI_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>thermo_id_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TRI_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>thermo_id_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TRI_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>thermo_id_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
  </spirit:busInterfaces>
  <spirit:memoryMaps>
    <spirit:memoryMap>
      <spirit:name>s00_axi</spirit:name>
      <spirit:addressBlock>
        <spirit:name>reg0</spirit:name>
        <spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
        <spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">135168</spirit:range>
        <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
        <spirit:usage>register</spirit:usage>
      </spirit:addressBlock>
    </spirit:memoryMap>
  </spirit:memoryMaps>
  <spirit:model>
    <spirit:views>
      <spirit:view>
        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
        <spirit:displayName>Synthesis</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
        <spirit:language>VHDL</spirit:language>
        <spirit:modelName>wrc_board_fasec</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
            <spirit:value>1f7cf57a</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
        <spirit:displayName>Simulation</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
        <spirit:language>VHDL</spirit:language>
        <spirit:modelName>wrc_board_fasec</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
            <spirit:value>9505b84d</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_xpgui</spirit:name>
        <spirit:displayName>UI Layout</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
            <spirit:value>939d4b1a</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
    </spirit:views>
    <spirit:ports>
      <spirit:port>
        <spirit:name>areset_n_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_20m_vcxo_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_125m_pllref_p_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_125m_pllref_n_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_125m_gtp_n_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_125m_gtp_p_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_10m_ext_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>pps_ext_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_sys_62m5_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk_ref_125m_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>rst_sys_62m5_n_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>rst_ref_125m_n_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>plldac_sclk_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>plldac_din_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>pll25dac_cs_n_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>pll20dac_cs_n_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_tx_p_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_tx_n_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_rx_p_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_rx_n_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_det_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_sda_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_sda_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_sda_t</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_scl_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_scl_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_scl_t</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_rate_select_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_tx_fault_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_tx_disable_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sfp_los_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eeprom_sda_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eeprom_sda_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eeprom_sda_t</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eeprom_scl_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eeprom_scl_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eeprom_scl_t</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>thermo_id_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>thermo_id_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>thermo_id_t</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>uart_rxd_i</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>uart_txd_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_aclk_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_aresetn</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_awaddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_awvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_awready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_wdata</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_wstrb</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">3</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_wvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_wready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_bresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_bvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_bready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_araddr</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_arvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_arready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_rdata</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_rresp</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_rvalid</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_rready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>s00_axi_rlast</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>axi_int_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led_act_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led_link_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>pps_p_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>pps_led_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>link_ok_o</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
    </spirit:ports>
    <spirit:modelParameters>
      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
        <spirit:name>g_simulation</spirit:name>
        <spirit:displayName>G Simulation</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_simulation">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>g_with_external_clock_input</spirit:name>
        <spirit:displayName>G With External Clock Input</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_with_external_clock_input">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>g_aux_clks</spirit:name>
        <spirit:displayName>G Aux Clks</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_aux_clks">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>g_fabric_iface</spirit:name>
        <spirit:displayName>G Fabric Iface</spirit:displayName>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_fabric_iface">plainfbrc</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="string">
        <spirit:name>g_dpram_initf</spirit:name>
        <spirit:displayName>G Dpram Initf</spirit:displayName>
        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_dpram_initf">../../../../bin/wrpc/wrc_phy16.bram</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>g_diag_id</spirit:name>
        <spirit:displayName>G Diag Id</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_id">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>g_diag_ver</spirit:name>
        <spirit:displayName>G Diag Ver</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_ver">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>g_diag_ro_vector_width</spirit:name>
        <spirit:displayName>G Diag Ro Vector Width</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_ro_vector_width">0</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>g_diag_rw_vector_width</spirit:name>
        <spirit:displayName>G Diag Rw Vector Width</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_rw_vector_width">0</spirit:value>
      </spirit:modelParameter>
    </spirit:modelParameters>
  </spirit:model>
  <spirit:choices>
    <spirit:choice>
      <spirit:name>choice_list_9d8b0d81</spirit:name>
      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
    </spirit:choice>
  </spirit:choices>
  <spirit:fileSets>
    <spirit:fileSet>
      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>board/fasec/wrc_board_fasec_ip.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/genram_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/wr_fabric_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/endpoint_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_registers_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_sync_register.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_sync_ffs.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gencores_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/endpoint_private_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_crc_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_sync_detect.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_crc32_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_sync_detect_16bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_extend_pulse.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rtu_header_extract.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/timing/dmtd_with_deglitcher.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_status_reg_insert.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_autonegotiation.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_crc_inserter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_ts_counter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_packet_filter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_pcs_16bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_crc_size_check.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_wb_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_pcs_8bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_vlan_unit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/spll_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_clock_alignment_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_inject_ctrl.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_oob_insert.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_header_processor.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_pcs_8bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_early_address_match.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_diags_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_vlan_unit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_syscon_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_pcs_16bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_packet_injection.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/minic_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_buffer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/softpll_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_wishbone_controller.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/spll_aligner.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/timing/dmtd_phase_meas.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrcore_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/spll_wb_slave.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_leds_controller.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_path.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/minic_wb_slave.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_path.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_syscon_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_diags_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_1000basex_pcs.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_frequency_meter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_timestamping_unit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_pps_gen/pps_gen_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_pps_gen/wr_pps_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/wr_endpoint.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/streamers_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/xwrc_diags_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/wr_softpll_ng.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/wr_mini_nic.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xtx_streamers_stats.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/escape_detector.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_periph.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xrx_streamers_stats.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/xwr_softpll_ng.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/xwb_fabric_sink.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_pps_gen/xwr_pps_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/escape_inserter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/xwb_fabric_source.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/dropping_buffer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/xwr_mini_nic.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/timing/pulse_stamper.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/xwrf_mux.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/xwr_endpoint.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/streamers_priv_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wr_core.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xrtx_streamers_stats.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_tbi_phy/disparity_gen_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xtx_streamer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/wr_streamers_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xrx_streamer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_xilinx_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/xwr_core.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_dacs/spec_serial_dac.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/common/wr_board_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xwr_streamers.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_dacs/spec_serial_dac_arb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/common/xwrc_board_common.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/fasec/wr_fasec_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/xwrc_platform_xilinx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_reset.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/fasec/xwrc_board_fasec.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/fasec/wrc_board_fasec.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>CHECKSUM_56627f08</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/genram_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/wr_fabric_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/endpoint_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_registers_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_sync_register.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_sync_ffs.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gencores_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/endpoint_private_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_crc_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_sync_detect.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_crc32_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_sync_detect_16bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_extend_pulse.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rtu_header_extract.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/timing/dmtd_with_deglitcher.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_status_reg_insert.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_autonegotiation.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_crc_inserter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_ts_counter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_packet_filter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_pcs_16bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_crc_size_check.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_wb_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_pcs_8bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_vlan_unit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/spll_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_clock_alignment_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_inject_ctrl.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_oob_insert.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_header_processor.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_pcs_8bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_early_address_match.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_diags_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_vlan_unit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_syscon_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_pcs_16bit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_packet_injection.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/minic_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_buffer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/softpll_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_wishbone_controller.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/spll_aligner.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/timing/dmtd_phase_meas.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrcore_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/spll_wb_slave.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_leds_controller.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_tx_path.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/minic_wb_slave.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_rx_path.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_syscon_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_diags_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_1000basex_pcs.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_frequency_meter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/ep_timestamping_unit.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_pps_gen/pps_gen_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_pps_gen/wr_pps_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/wr_endpoint.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/streamers_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/xwrc_diags_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/wr_softpll_ng.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/wr_mini_nic.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xtx_streamers_stats.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/escape_detector.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wrc_periph.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xrx_streamers_stats.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_softpll_ng/xwr_softpll_ng.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/xwb_fabric_sink.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_pps_gen/xwr_pps_gen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/escape_inserter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/xwb_fabric_source.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/dropping_buffer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_mini_nic/xwr_mini_nic.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/timing/pulse_stamper.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/fabric/xwrf_mux.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_endpoint/xwr_endpoint.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/streamers_priv_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/wr_core.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xrtx_streamers_stats.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_tbi_phy/disparity_gen_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xtx_streamer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/wr_streamers_wb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xrx_streamer.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_xilinx_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wrc_core/xwr_core.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_dacs/spec_serial_dac.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/common/wr_board_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/xwr_streamers.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_dacs/spec_serial_dac_arb.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/common/xwrc_board_common.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/fasec/wr_fasec_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>platform/xilinx/xwrc_platform_xilinx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/common/gc_reset.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/fasec/xwrc_board_fasec.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>board/fasec/wrc_board_fasec.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>xgui/wrc_board_fasec_v4_1.tcl</spirit:name>
        <spirit:fileType>tclSource</spirit:fileType>
        <spirit:userFileType>CHECKSUM_3bc04777</spirit:userFileType>
        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
  </spirit:fileSets>
  <spirit:description>wrc_board_fasec_v4_2</spirit:description>
  <spirit:parameters>
    <spirit:parameter>
      <spirit:name>g_simulation</spirit:name>
      <spirit:displayName>G Simulation</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_simulation">0</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_with_external_clock_input</spirit:name>
      <spirit:displayName>G With External Clock Input</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_with_external_clock_input">0</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_aux_clks</spirit:name>
      <spirit:displayName>G Aux Clks</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_aux_clks">0</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_fabric_iface</spirit:name>
      <spirit:displayName>G Fabric Iface</spirit:displayName>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.g_fabric_iface">plainfbrc</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_dpram_initf</spirit:name>
      <spirit:displayName>G Dpram Initf</spirit:displayName>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.g_dpram_initf">../../../../bin/wrpc/wrc_phy16.bram</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_diag_id</spirit:name>
      <spirit:displayName>G Diag Id</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_id">0</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_diag_ver</spirit:name>
      <spirit:displayName>G Diag Ver</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_ver">0</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_diag_ro_vector_width</spirit:name>
      <spirit:displayName>G Diag Ro Vector Width</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_ro_vector_width">0</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>g_diag_rw_vector_width</spirit:name>
      <spirit:displayName>G Diag Rw Vector Width</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_rw_vector_width">0</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>Component_Name</spirit:name>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">wrc_board_fasec_v1_0</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
  <spirit:vendorExtensions>
    <xilinx:coreExtensions>
      <xilinx:supportedFamilies>
        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Beta">kintex7</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Beta">kintex7l</xilinx:family>
      </xilinx:supportedFamilies>
      <xilinx:taxonomies>
        <xilinx:taxonomy>/Communication_&amp;_Networking/Ethernet</xilinx:taxonomy>
        <xilinx:taxonomy>/Communication_&amp;_Networking/Networking</xilinx:taxonomy>
      </xilinx:taxonomies>
      <xilinx:displayName>wrc_board_fasec_v4_2</xilinx:displayName>
      <xilinx:definitionSource>package_project</xilinx:definitionSource>
      <xilinx:vendorDisplayName>CERN BE-CO-HT</xilinx:vendorDisplayName>
      <xilinx:vendorURL>https://www.ohwr.org/projects/wr-cores/wiki/wrpc_core</xilinx:vendorURL>
      <xilinx:coreRevision>6</xilinx:coreRevision>
      <xilinx:coreCreationDateTime>2017-12-13T15:47:09Z</xilinx:coreCreationDateTime>
      <xilinx:tags>
        <xilinx:tag xilinx:name="user.org:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
        <xilinx:tag xilinx:name="CERN:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
        <xilinx:tag xilinx:name="CERN:white_rabbit:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
        <xilinx:tag xilinx:name="CERN:white_rabbit:wrc_board_fasec:4.1_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
        <xilinx:tag xilinx:name="CERN:white_rabbit:wrc_board_fasec:4.2_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
      </xilinx:tags>
    </xilinx:coreExtensions>
    <xilinx:packagingInfo>
      <xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8250889b"/>
      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="115d9c61"/>
      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e4064f8e"/>
      <xilinx:checksum xilinx:scope="ports" xilinx:value="bd589f87"/>
      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c3b40ce5"/>
      <xilinx:checksum xilinx:scope="parameters" xilinx:value="5460d5ef"/>
    </xilinx:packagingInfo>
  </spirit:vendorExtensions>
</spirit:component>
