#   ---------------------------------------------------------------------------`
#   -- Clocks/resets
#   ---------------------------------------------------------------------------

#   -- Local oscillators
NET "clk_20m_vcxo_i" LOC = F22 | IOSTANDARD = LVCMOS33;    #Bank 14 VCCO - 3.3 V -- 20MHz VCXO clock
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;

#NET "clk_125m_pllref_p_i" LOC = F6 | IOSTANDARD = "LVDS_25";    #Bank 116 -- 125 MHz PLL reference
#NET "clk_125m_pllref_n_i" LOC = F5 | IOSTANDARD = "LVDS_25";    #Bank 116 -- 125 MHz PLL reference
#NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
#TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
#NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
#TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;

NET "clk_125m_gtx_p_i" LOC = D6    | IOSTANDARD = "LVDS_25";    #Bank 116 -- 125 MHz GTX reference
NET "clk_125m_gtx_n_i" LOC = D5    | IOSTANDARD = "LVDS_25";    #Bank 116 -- 125 MHz GTX reference
NET "clk_125m_gtx_p_i" TNM_NET = clk_125m_gtx_p_i;
TIMESPEC TS_clk_125m_gtx_p_i = PERIOD "clk_125m_gtx_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtx_n_i" TNM_NET = clk_125m_gtx_n_i;
TIMESPEC TS_clk_125m_gtx_n_i = PERIOD "clk_125m_gtx_n_i" 8 ns HIGH 50%;

#   ---------------------------------------------------------------------------
#   -- SPI interface to DACs
#   ---------------------------------------------------------------------------

NET "pll25dac_cs_n_o" LOC = A14 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V -- cs1
NET "pll20dac_cs_n_o" LOC = A15 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V -- cs2
NET "plldac_din_o"    LOC = A13 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
NET "plldac_sclk_o"   LOC = A12 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- SFP I/O for transceiver
#   ---------------------------------------------------------------------------

NET "sfp_txp_o" LOC = A4;                                  #Bank 116
NET "sfp_txn_o" LOC = A3;                                  #Bank 116
NET "sfp_rxp_i" LOC = B6;                                  #Bank 116
NET "sfp_rxn_i" LOC = B5;                                  #Bank 116
NET "sfp_mod_def0_i" LOC = E26    | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V  -- sfp detect
NET "sfp_mod_def1_b" LOC = J26    | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- scl
NET "sfp_mod_def2_b" LOC = H26    | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sda
NET "sfp_rate_select_o" LOC = G26 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_fault_i" LOC = C26    | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_disable_o" LOC = D26  | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_los_i" LOC = F25         | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- Onewire interface
#   ---------------------------------------------------------------------------

NET "onewire_b" LOC = L23 | IOSTANDARD = LVCMOS33;    #Bank 14 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- UART
#   ---------------------------------------------------------------------------

#TEST & DEBUG
# Signal uart_txd_o is an output in the design and must be connected to pin 20/12 (RXD_I) of U34 (CP2105GM)
# Signal uart_rxd_i is an input in the design and must be connected to pin 21/13 (TXD_O) of U34 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
NET "uart_rxd_i" LOC = D19 | IOSTANDARD = LVCMOS25 | PULLDOWN;    #Bank 15 VCCO - 2.5 V
NET "uart_txd_o" LOC = D20 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "USB_RX2" LOC = C19 | IOSTANDARD = LVCMOS25 | PULLDOWN;    #Bank 15 VCCO - 2.5 V
#NET "USB_TX2" LOC = B19 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#USB Connection on Test&Debug Connector (J35)
#NET "USBEXT_RX1" LOC = F14 | IOSTANDARD = LVCMOS33 | PULLDOWN;    #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX1" LOC = F13 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "USBEXT_RX2" LOC = C14 | IOSTANDARD = LVCMOS33 | PULLDOWN;    #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX2" LOC = C13 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- Flash memory SPI interface
#   ---------------------------------------------------------------------------

#    flash_sclk_o : out std_logic;
#    flash_ncs_o  : out std_logic;
#    flash_mosi_o : out std_logic;
#    flash_miso_i : in  std_logic;

#   ---------------------------------------------------------------------------
#   -- Miscellanous CLBv2 pins
#   ---------------------------------------------------------------------------
#NET "GPIO_LED[0]" LOC = C16 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
NET "led_act_o"    LOC = C16 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V -- LED D2: blinking indicates that packets are being transferred.
#NET "GPIO_LED[1]" LOC = B16 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[2]" LOC = B17 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[3]" LOC = A17 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[4]" LOC = A18 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
#NET "GPIO_LED[5]" LOC = A19 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V
NET "led_link_o"   LOC = A19 | IOSTANDARD = LVCMOS25;    #Bank 15 VCCO - 2.5 V -- LED D7: indicates if the link is up.

NET "reset_i"      LOC = E11 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V --Reset

#   ---------------------------------------------------------------------------
#   -- Digital I/O FMC Pins
#   -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
#   -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
#   ---------------------------------------------------------------------------

#   -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
#   -- external reference input.
NET "dio_clk_p_i" LOC = Y22       | IOSTANDARD=LVDS_25;  #CLK1_M2C_P
NET "dio_clk_n_i" LOC = AA22      | IOSTANDARD=LVDS_25;  #CLK1_M2C_N

#   -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
#   -- the mezzanine front panel.
NET "dio_p_i[4]" LOC = N21        | IOSTANDARD=LVDS_25;  #LA00_P
NET "dio_n_i[4]" LOC = N22        | IOSTANDARD=LVDS_25;  #LA00_N
NET "dio_p_i[3]" LOC = P16        | IOSTANDARD=LVDS_25;  #LA03_P
NET "dio_n_i[3]" LOC = N17        | IOSTANDARD=LVDS_25;  #LA03_N
NET "dio_p_i[2]" LOC = AB26       | IOSTANDARD=LVDS_25;  #LA16_P
NET "dio_n_i[2]" LOC = AC26       | IOSTANDARD=LVDS_25;  #LA16_N
NET "dio_p_i[1]" LOC = K20        | IOSTANDARD=LVDS_25;  #LA20_P
NET "dio_n_i[1]" LOC = J20        | IOSTANDARD=LVDS_25;  #LA20_N
NET "dio_p_i[0]" LOC = P19        | IOSTANDARD=LVDS_25;  #LA33_P
NET "dio_n_i[0]" LOC = P20        | IOSTANDARD=LVDS_25;  #LA33_N

#   -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
#   -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
#   -- of I/O (N+1) on the front panel of the mezzanine
NET "dio_p_o[4]" LOC = N18        | IOSTANDARD=LVDS_25;  #LA04_P
NET "dio_n_o[4]" LOC = M19        | IOSTANDARD=LVDS_25;  #LA04_N
NET "dio_p_o[3]" LOC = U19        | IOSTANDARD=LVDS_25;  #LA07_P
NET "dio_n_o[3]" LOC = U20        | IOSTANDARD=LVDS_25;  #LA07_N
NET "dio_p_o[2]" LOC = W20        | IOSTANDARD=LVDS_25;  #LA08_P
NET "dio_n_o[2]" LOC = Y21        | IOSTANDARD=LVDS_25;  #LA08_N
NET "dio_p_o[1]" LOC = M21        | IOSTANDARD=LVDS_25;  #LA28_P
NET "dio_n_o[1]" LOC = M22        | IOSTANDARD=LVDS_25;  #LA28_N
NET "dio_p_o[0]" LOC = N19        | IOSTANDARD=LVDS_25;  #LA29_P
NET "dio_n_o[0]" LOC = M20        | IOSTANDARD=LVDS_25;  #LA29_N

#   -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
#   -- panel is configured as an output.
NET "dio_oe_n_o[4]" LOC = AE22    | IOSTANDARD=LVCMOS25; #LA05_P
NET "dio_oe_n_o[3]" LOC = U26     | IOSTANDARD=LVCMOS25; #LA11_P
NET "dio_oe_n_o[2]" LOC = AB25    | IOSTANDARD=LVCMOS25; #LA15_N
NET "dio_oe_n_o[1]" LOC = N23     | IOSTANDARD=LVCMOS25; #LA24_N
NET "dio_oe_n_o[0]" LOC = P24     | IOSTANDARD=LVCMOS25; #LA30_P

#   -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
#   -- panel is 50-ohm terminated
NET "dio_term_en_o[4]" LOC = P25  | IOSTANDARD=LVCMOS25; #LA09_N
NET "dio_term_en_o[3]" LOC = R25  | IOSTANDARD=LVCMOS25; #LA09_P
NET "dio_term_en_o[2]" LOC = AF22 | IOSTANDARD=LVCMOS25; #LA05_N
NET "dio_term_en_o[1]" LOC = AF25 | IOSTANDARD=LVCMOS25; #LA06_N
NET "dio_term_en_o[0]" LOC = N24  | IOSTANDARD=LVCMOS25; #LA30_N

#    -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
#    -- blink 1-PPS.
NET "dio_led_top_o" LOC = R21     | IOSTANDARD=LVCMOS25; #LA01_P
NET "dio_led_bot_o" LOC = P21     | IOSTANDARD=LVCMOS25; #LA01_N

#   -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
#   -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
NET "dio_scl_b" LOC = D24         | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "dio_sda_b" LOC = D23         | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V

#   ---------------------------------------------------------------------------
#   -- GPIO connector
#   ---------------------------------------------------------------------------
#NET "GPIO[1]" LOC = H8 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[2]" LOC = J8 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[3]" LOC = G9 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[4]" LOC = H9 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[5]" LOC = F8 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[6]" LOC = G10 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[7]" LOC = F9 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[8]" LOC = F10 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[9]" LOC = D9 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[10]" LOC = D8 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[11]" LOC = B9 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[12]" LOC = C9 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[13]" LOC = A9 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[14]" LOC = A8 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[15]" LOC = A10 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "GPIO[16]" LOC = B10 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V

#FMC SIGNALS CLK LPC
#NET "FMC_CLK0_M2C_P" LOC = Y23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK0_M2C_N" LOC = AA24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_P" LOC = Y22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_N" LOC = AA22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA00_CC_P" LOC = N21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA00_CC_N" LOC = N22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA01_CC_P" LOC = R21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA01_CC_N" LOC = P21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA17_CC_P" LOC = R22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA17_CC_N" LOC = R23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA18_CC_P" LOC = AA23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA18_CC_N" LOC = AB24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V

#FMC SIGNALS CLK HPC
#NET "FMC_HA00_CC_P" LOC = AC23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA00_CC_N" LOC = AC24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA01_CC_P" LOC = F17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA01_CC_N" LOC = E17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA17_CC_P" LOC = E18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA17_CC_N" LOC = D18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V

########################################################

#FMC SIGNALS LPC
#NET "FMC_PRSNT_B" LOC = K21 | IOSTANDARD = LVCMOS33;    #Bank 14 VCCO - 3.3 V
#NET "FMC_LA02_P" LOC = H19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA02_N" LOC = G20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA03_P" LOC = P16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA03_N" LOC = N17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA04_P" LOC = N18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA04_N" LOC = M19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA05_P" LOC = AE22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA05_N" LOC = AF22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 23
#NET "FMC_LA06_P" LOC = AF24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 25
#NET "FMC_LA06_N" LOC = AF25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 27
#NET "FMC_LA07_P" LOC = U19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 29
#NET "FMC_LA07_N" LOC = U20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 31
#NET "FMC_LA08_P" LOC = W20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 33
#NET "FMC_LA08_N" LOC = Y21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 35
#NET "FMC_LA09_P" LOC = R25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 37
#NET "FMC_LA09_N" LOC = P25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 39
#NET "FMC_LA10_P" LOC = U24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA10_N" LOC = U25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA11_P" LOC = U26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA11_N" LOC = V26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA12_P" LOC = R26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA12_N" LOC = P26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA13_P" LOC = AE23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA13_N" LOC = AF23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA14_P" LOC = AD23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA14_N" LOC = AD24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA15_P" LOC = AA25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA15_N" LOC = AB25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA16_P" LOC = AB26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA16_N" LOC = AC26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA19_P" LOC = W23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 38
#NET "FMC_LA19_N" LOC = W24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 40
#NET "FMC_LA20_P" LOC = K20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA20_N" LOC = J20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA21_P" LOC = M25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_N" LOC = L25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_P" LOC = L19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA22_N" LOC = L20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_LA23_P" LOC = K25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA23_N" LOC = K26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_P" LOC = P23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_N" LOC = N23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_P" LOC = N26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_N" LOC = M26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_P" LOC = T22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_N" LOC = T23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA27_P" LOC = V23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA27_N" LOC = V24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_LA28_P" LOC = M21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA28_N" LOC = M22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_P" LOC = N19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_N" LOC = M20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_P" LOC = P24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_N" LOC = N24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA31_P" LOC = M24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA31_N" LOC = L24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA32_P" LOC = T20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA32_N" LOC = R20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA33_P" LOC = P19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_LA33_N" LOC = P20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V

#FMC SIGNALS HPC
#NET "FMC_HA02_P" LOC = J18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA02_N" LOC = J19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA03_P" LOC = G19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA03_N" LOC = F20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA04_P" LOC = F19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA04_N" LOC = E20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA05_P" LOC = H17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA05_N" LOC = H18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA06_P" LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA06_N" LOC = K17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA07_P" LOC = M17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA07_N" LOC = L18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA08_P" LOC = R16 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA08_N" LOC = R17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA09_P" LOC = R18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA09_N" LOC = P18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA10_P" LOC = T18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA10_N" LOC = T19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA11_P" LOC = U17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA11_N" LOC = T17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA12_P" LOC = AB21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA12_N" LOC = AC21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA13_P" LOC = AD21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA13_N" LOC = AE21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA14_P" LOC = V21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA14_N" LOC = W21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA15_P" LOC = U22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA15_N" LOC = V22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA16_P" LOC = T24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA16_N" LOC = T25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
#NET "FMC_HA18_P" LOC = W25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA18_N" LOC = W26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA19_P" LOC = AD26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA19_N" LOC = AE26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA20_P" LOC = AD25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA20_N" LOC = AE25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA21_P" LOC = Y25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA21_N" LOC = Y26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA22_P" LOC = AB22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA22_N" LOC = AC22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
#NET "FMC_HA23_P" LOC = L17 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V
#NET "FMC_HA23_N" LOC = K18 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 15 VCCO - 2.5 V

#OCTOPUS SMALL
#NET "IIC1_SDA" LOC = J13 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "IIC1_SCL" LOC = H13 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "EN_SCLK"  LOC = H12 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "PMT_P[0]"   LOC = AD16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[0]"   LOC = AE16 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[1]"   LOC = Y17  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[1]"   LOC = Y18  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[2]"   LOC = W18  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[2]"   LOC = W19  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[3]"   LOC = AD15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[3]"   LOC = AE15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[4]"   LOC = AA17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[4]"   LOC = AA18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[5]"   LOC = AA19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[5]"   LOC = AA20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[6]"   LOC = AC14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[6]"   LOC = AD14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[7]"   LOC = AC18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[7]"   LOC = AD18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[8]"   LOC = AB19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[8]"   LOC = AB20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[9]"   LOC = AF14 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[9]"   LOC = AF15 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[10]"  LOC = AB17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[10]"  LOC = AC17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_P[11]"  LOC = AD20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "PMT_N[11]"  LOC = AE20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA0P" LOC = AE17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA0N" LOC = AF17 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA1P" LOC = AE18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA1N" LOC = AF18 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA2P" LOC = AF19 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V
#NET "SPMT_SPA2N" LOC = AF20 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";    #Bank 32 VCCO - 1.8 V

#OCTOPUS LARGE
#NET "IIC2_SDA" LOC = H14 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "IIC2_SCL" LOC = G14 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "EN_LCLK"  LOC = H11 | IOSTANDARD = LVCMOS33;    #Bank 16 VCCO - 3.3 V
#NET "PMT_P[12]" LOC = AE7  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_N[12]" LOC = AF7  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_P[13]" LOC = AF5  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[13]" LOC = AF4  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[14]" LOC = AD1  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[14]" LOC = AE1  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[15]" LOC = AE8  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_N[15]" LOC = AF8  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_P[16]" LOC = AE6  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[16]" LOC = AE5  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[17]" LOC = AF3  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[17]" LOC = AF2  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[18]" LOC = AC8  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_N[18]" LOC = AD8  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_P[19]" LOC = AD4  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[19]" LOC = AD3  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[20]" LOC = AE3  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[20]" LOC = AE2  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[21]" LOC = AB7  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_N[21]" LOC = AC7  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_P[22]" LOC = AD6  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[22]" LOC = AD5  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[23]" LOC = AB1  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[23]" LOC = AC1  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[24]" LOC = AF10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_N[24]" LOC = AF9  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_P[25]" LOC = AC4  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[25]" LOC = AC3  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[26]" LOC = AB2  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[26]" LOC = AC2  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[27]" LOC = AC9  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_N[27]" LOC = AD9  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_P[28]" LOC = AA4  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[28]" LOC = AB4  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[29]" LOC = AA3  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_N[29]" LOC = AA2  | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 34 VCCO - 1.8 V
#NET "PMT_P[30]" LOC = AD10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
#NET "PMT_N[30]" LOC = AE10 | IOSTANDARD = LVDS | DIFF_TERM = "TRUE";     #Bank 33 VCCO - 1.8 V
                                                                        