| File | Description |
|---|
| ddr3_mem.vhd | A MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. |
| ddr3_mem.cmp | A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function. |
| ddr3_mem.qip | Contains Quartus II project information for your MegaCore function variation. |
| ddr3_mem.html | The MegaCore function report file. |
| ddr3_mem_example_driver.vhdl | Example self-checking test generator that matches your variation. |
| ddr3_mem_example_top.vhdl | Example top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller. |
| ddr3_mem_example_top.sdc | Example Synopsys Design Constraints file for paths in the example top level. |
| ddr3_mem_ex_lfsr8.vhdl | Example linear feedback shift register that is used to generate the pseudo-random test data for the example driver. |
| testbench | ddr3_mem_example_top_tb.vhdl | Example testbench that instantiates the example top level design file and the example memory model. |
| testbench | ddr3_mem_mem_model.vhdl | A simple example memory model that matches your variation. |
| testbench | ddr3_mem_full_mem_model.vhdl | Memory model that allocates memory for all available addresses. |
| ddr3_mem_pin_assignments.tcl | TCL script |
| ddr3_mem_advisor.ipa | IP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software. |
| ddr3_mem_phy.qip | Generated ALTMEMPHY QIP file. |