/*
  Register definitions for slave core: WR Core System Controller

  * File           : wrc_syscon_regs.h
  * Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
  * Created        : Mon Jul 11 14:59:51 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
#define __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Syscon reset register */

/* definitions for field: Reset trigger in reg: Syscon reset register */
#define SYSC_RSTR_TRIG_MASK                   WBGEN2_GEN_MASK(0, 28)
#define SYSC_RSTR_TRIG_SHIFT                  0
#define SYSC_RSTR_TRIG_W(value)               WBGEN2_GEN_WRITE(value, 0, 28)
#define SYSC_RSTR_TRIG_R(reg)                 WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: Reset line state value in reg: Syscon reset register */
#define SYSC_RSTR_RST                         WBGEN2_GEN_MASK(28, 1)

/* definitions for register: GPIO Set/Readback Register */

/* definitions for field: Status LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_LED_STAT                    WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Link LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_LED_LINK                    WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_FMC_SCL                     WBGEN2_GEN_MASK(2, 1)

/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_FMC_SDA                     WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Network AP reset in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_NET_RST                     WBGEN2_GEN_MASK(4, 1)

/* definitions for field: SPEC Pushbutton 1 state in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_BTN1                        WBGEN2_GEN_MASK(5, 1)

/* definitions for field: SPEC Pushbutton 2 state in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_BTN2                        WBGEN2_GEN_MASK(6, 1)

/* definitions for field: SFP detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_DET                     WBGEN2_GEN_MASK(7, 1)

/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SCL                     WBGEN2_GEN_MASK(8, 1)

/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SDA                     WBGEN2_GEN_MASK(9, 1)

/* definitions for field: SPI bitbanged SCLK in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_SCLK                    WBGEN2_GEN_MASK(10, 1)

/* definitions for field: SPI bitbanged NCS in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_NCS                     WBGEN2_GEN_MASK(11, 1)

/* definitions for field: SPI bitbanged MOSI in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MOSI                    WBGEN2_GEN_MASK(12, 1)

/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO                    WBGEN2_GEN_MASK(13, 1)

/* definitions for register: GPIO Clear Register */

/* definitions for field: Status LED in reg: GPIO Clear Register */
#define SYSC_GPCR_LED_STAT                    WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Link LED in reg: GPIO Clear Register */
#define SYSC_GPCR_LED_LINK                    WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_FMC_SCL                     WBGEN2_GEN_MASK(2, 1)

/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_FMC_SDA                     WBGEN2_GEN_MASK(3, 1)

/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SCL                     WBGEN2_GEN_MASK(8, 1)

/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SDA                     WBGEN2_GEN_MASK(9, 1)

/* definitions for field: SPI bitbanged SCLK in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_SCLK                    WBGEN2_GEN_MASK(10, 1)

/* definitions for field: SPI bitbanged CS in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_CS                      WBGEN2_GEN_MASK(11, 1)

/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI                    WBGEN2_GEN_MASK(12, 1)

/* definitions for register: Hardware Feature Register */

/* definitions for field: Memory size in reg: Hardware Feature Register */
#define SYSC_HWFR_MEMSIZE_MASK                WBGEN2_GEN_MASK(0, 4)
#define SYSC_HWFR_MEMSIZE_SHIFT               0
#define SYSC_HWFR_MEMSIZE_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define SYSC_HWFR_MEMSIZE_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for register: Timer Control Register */

/* definitions for field: Timer Divider in reg: Timer Control Register */
#define SYSC_TCR_TDIV_MASK                    WBGEN2_GEN_MASK(0, 12)
#define SYSC_TCR_TDIV_SHIFT                   0
#define SYSC_TCR_TDIV_W(value)                WBGEN2_GEN_WRITE(value, 0, 12)
#define SYSC_TCR_TDIV_R(reg)                  WBGEN2_GEN_READ(reg, 0, 12)

/* definitions for field: Timer Enable in reg: Timer Control Register */
#define SYSC_TCR_ENABLE                       WBGEN2_GEN_MASK(31, 1)

/* definitions for register: Timer Counter Value Register */

/* definitions for register: User Diag: version register */

/* definitions for field: Ver in reg: User Diag: version register */
#define SYSC_DIAG_INFO_VER_MASK               WBGEN2_GEN_MASK(0, 16)
#define SYSC_DIAG_INFO_VER_SHIFT              0
#define SYSC_DIAG_INFO_VER_W(value)           WBGEN2_GEN_WRITE(value, 0, 16)
#define SYSC_DIAG_INFO_VER_R(reg)             WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Id in reg: User Diag: version register */
#define SYSC_DIAG_INFO_ID_MASK                WBGEN2_GEN_MASK(16, 16)
#define SYSC_DIAG_INFO_ID_SHIFT               16
#define SYSC_DIAG_INFO_ID_W(value)            WBGEN2_GEN_WRITE(value, 16, 16)
#define SYSC_DIAG_INFO_ID_R(reg)              WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: User Diag: number of words */

/* definitions for field: Read/write words in reg: User Diag: number of words */
#define SYSC_DIAG_NW_RW_MASK                  WBGEN2_GEN_MASK(0, 16)
#define SYSC_DIAG_NW_RW_SHIFT                 0
#define SYSC_DIAG_NW_RW_W(value)              WBGEN2_GEN_WRITE(value, 0, 16)
#define SYSC_DIAG_NW_RW_R(reg)                WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Read-only words in reg: User Diag: number of words */
#define SYSC_DIAG_NW_RO_MASK                  WBGEN2_GEN_MASK(16, 16)
#define SYSC_DIAG_NW_RO_SHIFT                 16
#define SYSC_DIAG_NW_RO_W(value)              WBGEN2_GEN_WRITE(value, 16, 16)
#define SYSC_DIAG_NW_RO_R(reg)                WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: User Diag: Control Register */

/* definitions for field: Address in reg: User Diag: Control Register */
#define SYSC_DIAG_CR_ADR_MASK                 WBGEN2_GEN_MASK(0, 16)
#define SYSC_DIAG_CR_ADR_SHIFT                0
#define SYSC_DIAG_CR_ADR_W(value)             WBGEN2_GEN_WRITE(value, 0, 16)
#define SYSC_DIAG_CR_ADR_R(reg)               WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: R/W in reg: User Diag: Control Register */
#define SYSC_DIAG_CR_RW                       WBGEN2_GEN_MASK(31, 1)

/* definitions for register: User Diag: data to read/write */
/* [0x0]: REG Syscon reset register */
#define SYSC_REG_RSTR 0x00000000
/* [0x4]: REG GPIO Set/Readback Register */
#define SYSC_REG_GPSR 0x00000004
/* [0x8]: REG GPIO Clear Register */
#define SYSC_REG_GPCR 0x00000008
/* [0xc]: REG Hardware Feature Register */
#define SYSC_REG_HWFR 0x0000000c
/* [0x10]: REG Timer Control Register */
#define SYSC_REG_TCR 0x00000010
/* [0x14]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x00000014
/* [0x18]: REG User Diag: version register */
#define SYSC_REG_DIAG_INFO 0x00000018
/* [0x1c]: REG User Diag: number of words */
#define SYSC_REG_DIAG_NW 0x0000001c
/* [0x20]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_CR 0x00000020
/* [0x24]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x00000024
#endif
