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-- Title          : Wishbone slave core for Mock Turtle CPU Control/Status registers block
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-- File           : wrc_cpu_csr_wb.vhd
-- Author         : auto-generated by wbgen2 from wrc_cpu_csr.wb
-- Created        : Fri Feb 19 19:31:37 2021
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_cpu_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

use work.wrc_cpu_csr_wbgen2_pkg.all;


entity wrc_cpu_csr_wb_slave is
port (
  rst_n_i                                  : in     std_logic;
  clk_sys_i                                : in     std_logic;
  slave_i                                  : in     t_wishbone_slave_in;
  slave_o                                  : out    t_wishbone_slave_out;
  int_o                                    : out    std_logic;
  regs_i                                   : in     t_wrc_cpu_csr_in_registers;
  regs_o                                   : out    t_wrc_cpu_csr_out_registers
);
end wrc_cpu_csr_wb_slave;

architecture syn of wrc_cpu_csr_wb_slave is

signal wrc_cpu_csr_reset_int                    : std_logic_vector(7 downto 0);
signal wrc_cpu_csr_uaddr_addr_int               : std_logic_vector(19 downto 0);
signal wrc_cpu_csr_dbg_force_int                : std_logic_vector(7 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(5 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
-- 
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
  if (rst_n_i = '0') then 
    ack_sreg <= "0000000000";
    ack_in_progress <= '0';
    rddata_reg <= "00000000000000000000000000000000";
    wrc_cpu_csr_reset_int <= "00000000";
    wrc_cpu_csr_uaddr_addr_int <= "00000000000000000000";
    regs_o.udata_load_o <= '0';
    wrc_cpu_csr_dbg_force_int <= "00000000";
    regs_o.dbg_core0_insn_wr_o <= '0';
    regs_o.dbg_core0_mbx_load_o <= '0';
  elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
    ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
    ack_sreg(9) <= '0';
    if (ack_in_progress = '1') then
      if (ack_sreg(0) = '1') then
        regs_o.udata_load_o <= '0';
        regs_o.dbg_core0_insn_wr_o <= '0';
        regs_o.dbg_core0_mbx_load_o <= '0';
        ack_in_progress <= '0';
      else
        regs_o.udata_load_o <= '0';
        regs_o.dbg_core0_insn_wr_o <= '0';
        regs_o.dbg_core0_mbx_load_o <= '0';
      end if;
    else
      if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
        case rwaddr_reg(5 downto 0) is
        when "000000" => 
          if (slave_i.we = '1') then
            wrc_cpu_csr_reset_int <= wrdata_reg(7 downto 0);
          end if;
          rddata_reg(7 downto 0) <= wrc_cpu_csr_reset_int;
          rddata_reg(8) <= '0';
          rddata_reg(9) <= '0';
          rddata_reg(10) <= '0';
          rddata_reg(11) <= '0';
          rddata_reg(12) <= '0';
          rddata_reg(13) <= '0';
          rddata_reg(14) <= '0';
          rddata_reg(15) <= '0';
          rddata_reg(16) <= '0';
          rddata_reg(17) <= '0';
          rddata_reg(18) <= '0';
          rddata_reg(19) <= '0';
          rddata_reg(20) <= '0';
          rddata_reg(21) <= '0';
          rddata_reg(22) <= '0';
          rddata_reg(23) <= '0';
          rddata_reg(24) <= '0';
          rddata_reg(25) <= '0';
          rddata_reg(26) <= '0';
          rddata_reg(27) <= '0';
          rddata_reg(28) <= '0';
          rddata_reg(29) <= '0';
          rddata_reg(30) <= '0';
          rddata_reg(31) <= '0';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "000001" => 
          if (slave_i.we = '1') then
            wrc_cpu_csr_uaddr_addr_int <= wrdata_reg(19 downto 0);
          end if;
          rddata_reg(19 downto 0) <= wrc_cpu_csr_uaddr_addr_int;
          rddata_reg(20) <= '0';
          rddata_reg(21) <= '0';
          rddata_reg(22) <= '0';
          rddata_reg(23) <= '0';
          rddata_reg(24) <= '0';
          rddata_reg(25) <= '0';
          rddata_reg(26) <= '0';
          rddata_reg(27) <= '0';
          rddata_reg(28) <= '0';
          rddata_reg(29) <= '0';
          rddata_reg(30) <= '0';
          rddata_reg(31) <= '0';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "000010" => 
          if (slave_i.we = '1') then
            regs_o.udata_load_o <= '1';
          end if;
          rddata_reg(31 downto 0) <= regs_i.udata_i;
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "100000" => 
          if (slave_i.we = '1') then
          end if;
          rddata_reg(7 downto 0) <= regs_i.dbg_status_i;
          rddata_reg(8) <= '0';
          rddata_reg(9) <= '0';
          rddata_reg(10) <= '0';
          rddata_reg(11) <= '0';
          rddata_reg(12) <= '0';
          rddata_reg(13) <= '0';
          rddata_reg(14) <= '0';
          rddata_reg(15) <= '0';
          rddata_reg(16) <= '0';
          rddata_reg(17) <= '0';
          rddata_reg(18) <= '0';
          rddata_reg(19) <= '0';
          rddata_reg(20) <= '0';
          rddata_reg(21) <= '0';
          rddata_reg(22) <= '0';
          rddata_reg(23) <= '0';
          rddata_reg(24) <= '0';
          rddata_reg(25) <= '0';
          rddata_reg(26) <= '0';
          rddata_reg(27) <= '0';
          rddata_reg(28) <= '0';
          rddata_reg(29) <= '0';
          rddata_reg(30) <= '0';
          rddata_reg(31) <= '0';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "100001" => 
          if (slave_i.we = '1') then
            wrc_cpu_csr_dbg_force_int <= wrdata_reg(7 downto 0);
          end if;
          rddata_reg(7 downto 0) <= wrc_cpu_csr_dbg_force_int;
          rddata_reg(8) <= '0';
          rddata_reg(9) <= '0';
          rddata_reg(10) <= '0';
          rddata_reg(11) <= '0';
          rddata_reg(12) <= '0';
          rddata_reg(13) <= '0';
          rddata_reg(14) <= '0';
          rddata_reg(15) <= '0';
          rddata_reg(16) <= '0';
          rddata_reg(17) <= '0';
          rddata_reg(18) <= '0';
          rddata_reg(19) <= '0';
          rddata_reg(20) <= '0';
          rddata_reg(21) <= '0';
          rddata_reg(22) <= '0';
          rddata_reg(23) <= '0';
          rddata_reg(24) <= '0';
          rddata_reg(25) <= '0';
          rddata_reg(26) <= '0';
          rddata_reg(27) <= '0';
          rddata_reg(28) <= '0';
          rddata_reg(29) <= '0';
          rddata_reg(30) <= '0';
          rddata_reg(31) <= '0';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "100010" => 
          if (slave_i.we = '1') then
          end if;
          rddata_reg(7 downto 0) <= regs_i.dbg_insn_ready_i;
          rddata_reg(8) <= '0';
          rddata_reg(9) <= '0';
          rddata_reg(10) <= '0';
          rddata_reg(11) <= '0';
          rddata_reg(12) <= '0';
          rddata_reg(13) <= '0';
          rddata_reg(14) <= '0';
          rddata_reg(15) <= '0';
          rddata_reg(16) <= '0';
          rddata_reg(17) <= '0';
          rddata_reg(18) <= '0';
          rddata_reg(19) <= '0';
          rddata_reg(20) <= '0';
          rddata_reg(21) <= '0';
          rddata_reg(22) <= '0';
          rddata_reg(23) <= '0';
          rddata_reg(24) <= '0';
          rddata_reg(25) <= '0';
          rddata_reg(26) <= '0';
          rddata_reg(27) <= '0';
          rddata_reg(28) <= '0';
          rddata_reg(29) <= '0';
          rddata_reg(30) <= '0';
          rddata_reg(31) <= '0';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "100011" => 
          if (slave_i.we = '1') then
            regs_o.dbg_core0_insn_wr_o <= '1';
          end if;
          rddata_reg(0) <= '0';
          rddata_reg(1) <= '0';
          rddata_reg(2) <= '0';
          rddata_reg(3) <= '0';
          rddata_reg(4) <= '0';
          rddata_reg(5) <= '0';
          rddata_reg(6) <= '0';
          rddata_reg(7) <= '0';
          rddata_reg(8) <= '0';
          rddata_reg(9) <= '0';
          rddata_reg(10) <= '0';
          rddata_reg(11) <= '0';
          rddata_reg(12) <= '0';
          rddata_reg(13) <= '0';
          rddata_reg(14) <= '0';
          rddata_reg(15) <= '0';
          rddata_reg(16) <= '0';
          rddata_reg(17) <= '0';
          rddata_reg(18) <= '0';
          rddata_reg(19) <= '0';
          rddata_reg(20) <= '0';
          rddata_reg(21) <= '0';
          rddata_reg(22) <= '0';
          rddata_reg(23) <= '0';
          rddata_reg(24) <= '0';
          rddata_reg(25) <= '0';
          rddata_reg(26) <= '0';
          rddata_reg(27) <= '0';
          rddata_reg(28) <= '0';
          rddata_reg(29) <= '0';
          rddata_reg(30) <= '0';
          rddata_reg(31) <= '0';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "100100" => 
          if (slave_i.we = '1') then
            regs_o.dbg_core0_mbx_load_o <= '1';
          end if;
          rddata_reg(31 downto 0) <= regs_i.dbg_core0_mbx_i;
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when others =>
-- prevent the slave from hanging the bus on invalid address
          ack_in_progress <= '1';
          ack_sreg(0) <= '1';
        end case;
      end if;
    end if;
  end if;
end process;


-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Core reset lines
regs_o.reset_o <= wrc_cpu_csr_reset_int;
-- Address to access in selected core's local memory.
regs_o.uaddr_addr_o <= wrc_cpu_csr_uaddr_addr_int;
-- Read/Write data from/to selected core's local memory.
regs_o.udata_o <= wrdata_reg(31 downto 0);
-- Per Core debug mode bit
-- Core debug force
regs_o.dbg_force_o <= wrc_cpu_csr_dbg_force_int;
-- Core instruction ready
-- Instruction to be executed
-- pass-through field: Instruction to be executed in register: Debug Interface Core[0] Instruction Register
regs_o.dbg_core0_insn_o <= wrdata_reg(31 downto 0);
-- Mailbox data
regs_o.dbg_core0_mbx_o <= wrdata_reg(31 downto 0);
rwaddr_reg <= slave_i.adr(7 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
