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//------------------------------------------------------------------------------


`timescale 1ps/1ps

// =====================================================================================================================
// This example design checking module checks PRBS31 data at the appropriate parallel data width from the receiver,
// along with performing any data manipulation or sideband signaling necessary for the selected data decoding. This
// module instance checks data from a single transceiver channel for data reception demonstration purposes.
// =====================================================================================================================

module wr_gth_wrapper_example_checking_8b10b (
  input  wire         gtwiz_reset_all_in,
  input  wire         gtwiz_userclk_rx_usrclk2_in,
  input  wire         gtwiz_userclk_rx_active_in,
  input  wire  [15:0] rxctrl0_in,
  input  wire  [15:0] rxctrl1_in,
  input  wire   [7:0] rxctrl2_in,
  input  wire   [7:0] rxctrl3_in,
  input  wire [15:0] rxdata_in,
  output reg          prbs_match_out = 1'b0
);


  // -------------------------------------------------------------------------------------------------------------------
  // Reset synchronizer
  // -------------------------------------------------------------------------------------------------------------------

  // Synchronize the example stimulus reset condition into the rxusrclk2 domain
  wire example_checking_reset_int = gtwiz_reset_all_in || ~gtwiz_userclk_rx_active_in;
  wire example_checking_reset_sync;

  (* DONT_TOUCH = "TRUE" *)
  wr_gth_wrapper_example_reset_synchronizer example_checking_reset_synchronizer_inst (
    .clk_in  (gtwiz_userclk_rx_usrclk2_in),
    .rst_in  (example_checking_reset_int),
    .rst_out (example_checking_reset_sync)
  );


  // -------------------------------------------------------------------------------------------------------------------
  // PRBS checker enable and sideband control generation
  // -------------------------------------------------------------------------------------------------------------------

  // For 8B/10B mode data reception, the PRBS checker is always enabled
  wire prbs_any_chk_en_int = 1'b1;


  // -------------------------------------------------------------------------------------------------------------------
  // PRBS checker block
  // -------------------------------------------------------------------------------------------------------------------

  // The prbs_any block, described in Xilinx Application Note 884 (XAPP884), "An Attribute-Programmable PRBS Generator
  // and Checker", generates or checks a parameterizable PRBS sequence. Instantiate and parameterize a prbs_any block
  // to check a PRBS31 sequence with parallel data sized to the receiver user data width.
  wire [15:0] prbs_any_chk_error_int;

  wr_gth_wrapper_prbs_any # (
    .CHK_MODE    (1),
    .INV_PATTERN (1),
    .POLY_LENGHT (31),
    .POLY_TAP    (28),
    .NBITS       (16)
  ) prbs_any_chk_inst (
    .RST      (example_checking_reset_sync),
    .CLK      (gtwiz_userclk_rx_usrclk2_in),
    .DATA_IN  (rxdata_in),
    .EN       (prbs_any_chk_en_int),
    .DATA_OUT (prbs_any_chk_error_int)
  );

  // The prbs_any block indicates a match of the parallel PRBS data when all DATA_OUT bits are 0. Register the result
  // of the NOR function as the PRBS match indicator.
  always @(posedge gtwiz_userclk_rx_usrclk2_in) begin
    if (example_checking_reset_sync)
      prbs_match_out <= 1'b0;
    else
      prbs_match_out <= ~(|prbs_any_chk_error_int);
  end


endmodule
