wb_BuTiSclock

BuTis clock generator

Generates BuTis clock T0 and C2 in phase with White Rabbit 125MHz clock and PPS signal

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. TimeStamp data Low word
3.2. TimeStamp data High word
3.3. BuTis clock generator control
3.4. BuTis clock generator Status

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG TimeStamp data Low word wbbutis_timestamp TIMESTAMP
0x1 REG TimeStamp data High word wbbutis_timestamp TIMESTAMP
0x2 REG BuTis clock generator control wbbutis_control CONTROL
0x3 REG BuTis clock generator Status wbbutis_status STATUS

2. HDL symbol

rst_n_i TimeStamp data Low word:
wb_clk_i wbbutis_timestamp_lw_o[31:0]
wb_addr_i[1:0]  
wb_data_i[31:0] TimeStamp data High word:
wb_data_o[31:0] wbbutis_timestamp_hw_o[31:0]
wb_cyc_i  
wb_sel_i[3:0] BuTis clock generator control:
wb_stb_i wbbutis_control_set_o
wb_we_i wbbutis_control_set_wr_o
wb_ack_o wbbutis_control_sync_o
wbbutis_control_sync_wr_o
wbbutis_control_reset_o
wbbutis_control_reset_wr_o
wbbutis_control_unused_o[4:0]
wbbutis_control_phase_o[7:0]
 
BuTis clock generator Status:
wbbutis_status_set_i
wbbutis_status_ppsphase_i

3. Register description

3.1. TimeStamp data Low word

HW prefix: wbbutis_timestamp
HW address: 0x0
C prefix: TIMESTAMP
C offset: 0x0

TimeStamp data Low word

31 30 29 28 27 26 25 24
LW[31:24]
23 22 21 20 19 18 17 16
LW[23:16]
15 14 13 12 11 10 9 8
LW[15:8]
7 6 5 4 3 2 1 0
LW[7:0]

3.2. TimeStamp data High word

HW prefix: wbbutis_timestamp
HW address: 0x1
C prefix: TIMESTAMP
C offset: 0x4

TimeStamp data High word

31 30 29 28 27 26 25 24
HW[31:24]
23 22 21 20 19 18 17 16
HW[23:16]
15 14 13 12 11 10 9 8
HW[15:8]
7 6 5 4 3 2 1 0
HW[7:0]

3.3. BuTis clock generator control

HW prefix: wbbutis_control
HW address: 0x2
C prefix: CONTROL
C offset: 0x8

BuTis clock generator control

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
PHASE[7:0]
7 6 5 4 3 2 1 0
UNUSED[4:0] RESET SYNC SET

3.4. BuTis clock generator Status

HW prefix: wbbutis_status
HW address: 0x3
C prefix: STATUS
C offset: 0xc

BuTis clock generator Status

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - PPSPHASE SET