wr_fec_dummy_pck_gen_if

WB Intreface to dummy pck generator.

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	Dummy paylaod size (bytes)	wr_fec_dummy_pck_gen_payload_size	PAYLOAD_SIZE
0x1	REG	Paylaod increment step size (bytes)	wr_fec_dummy_pck_gen_increment_size	INCREMENT_SIZE
0x2	REG	Number of frames to be generated	wr_fec_dummy_pck_gen_gen_frame_number	GEN_FRAME_NUMBER
0x3	REG	Control register	wr_fec_dummy_pck_gen_ctrl	CTRL
0x4	REG	Status register	wr_fec_dummy_pck_gen_status	STATUS

2. HDL symbol

→	rst_n_i	Dummy paylaod size (bytes):
→	wb_clk_i	wr_fec_dummy_pck_gen_payload_size_o[15:0]	⇒
⇒	wb_addr_i[2:0]
⇒	wb_data_i[31:0]	Paylaod increment step size (bytes):
⇐	wb_data_o[31:0]	wr_fec_dummy_pck_gen_increment_size_o[7:0]	⇒
→	wb_cyc_i
⇒	wb_sel_i[3:0]	Number of frames to be generated:
→	wb_stb_i	wr_fec_dummy_pck_gen_gen_frame_number_o[15:0]	⇒
→	wb_we_i
←	wb_ack_o	Control register:
		wr_fec_dummy_pck_gen_ctrl_start_o	→
		wr_fec_dummy_pck_gen_ctrl_stop_o	→
		wr_fec_dummy_pck_gen_ctrl_fec_o	→
		wr_fec_dummy_pck_gen_ctrl_continuous_o	→
		wr_fec_dummy_pck_gen_ctrl_vlan_o	→

		Status register:
		wr_fec_dummy_pck_gen_status_i[15:0]	⇐

3. Register description

3.1. Dummy paylaod size (bytes)

HW prefix:	wr_fec_dummy_pck_gen_payload_size
HW address:	0x0
C prefix:	PAYLOAD_SIZE
C offset:	0x0

This is the size of the payload generated. If we define incrementation step, this is
the size of the first frame's payload.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
PAYLOAD_SIZE[15:8]

7	6	5	4	3	2	1	0
PAYLOAD_SIZE[7:0]

PAYLOAD_SIZE [read/write]: Payload Value

3.2. Paylaod increment step size (bytes)

HW prefix:	wr_fec_dummy_pck_gen_increment_size
HW address:	0x1
C prefix:	INCREMENT_SIZE
C offset:	0x4

Defines the incremental step of the subsequently generated frames.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
INCREMENT_SIZE[7:0]

INCREMENT_SIZE [read/write]: Increment Value

3.3. Number of frames to be generated

HW prefix:	wr_fec_dummy_pck_gen_gen_frame_number
HW address:	0x2
C prefix:	GEN_FRAME_NUMBER
C offset:	0x8

It defines how many frames shall be generated in one cycle.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
GEN_FRAME_NUMBER[15:8]

7	6	5	4	3	2	1	0
GEN_FRAME_NUMBER[7:0]

GEN_FRAME_NUMBER [read/write]: Generate Number Value

3.4. Control register

HW prefix:	wr_fec_dummy_pck_gen_ctrl
HW address:	0x3
C prefix:	CTRL
C offset:	0xc

This register is used to control the dummy frame generateor

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	VLAN	CONTINUOUS	FEC	STOP	START

START [read/write]: Start generation
Writing one to this bit will start generation of frames
STOP [read/write]: Stop generation
Once the generation is complete or indicates error, it needs to be stopped
by writing 1 to this field. The generatio needs to be stopped
also when we want to start it again. In continuous mode, this is the only way to stop
the generation
FEC [read/write]: Enable FEC
This fileds indicate whether the frames shall be destined to be encoded by FEC.
This is done by writing the first word (16 bits) to the special FEC address.
0: Do not send frames for FECing,
1: Do send frames for FECing.
CONTINUOUS [read/write]: Continuous mode
Enables/disables continous generation mode:.
0: Only one cycle is performed (given number of frames defined in settings or increment up to max size),
1: Continuous mode: if the max number of frames is generated, or max size reached, we start from the beginning.
VLAN [read/write]: VLAN-tagging enable
Enables generation of VLAN-tagged frames.
0: Standard Ethernet header,
1: Ethernet Header with VLAN-tagging (priority, VLAN ID) as defined in IEEE 802.1Q.

3.5. Status register

HW prefix:	wr_fec_dummy_pck_gen_status
HW address:	0x4
C prefix:	STATUS
C offset:	0x10

Status register

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
STATUS[15:8]

7	6	5	4	3	2	1	0
STATUS[7:0]

STATUS [read-only]: Status Register Value

wr_fec_dummy_pck_gen_if

WB Intreface to dummy pck generator.

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