wr_arria10_e3p1_cmu_pll

2019.06.19.10:54:26 Datasheet
Overview

Memory Map

xcvr_cdr_pll_a10_0

altera_xcvr_cdr_pll_a10 v18.1


Parameters

rcfg_debug 0
enable_pll_reconfig 0
enable_advanced_avmm_options 0
rcfg_jtag_enable 0
rcfg_separate_avmm_busy 0
rcfg_enable_avmm_busy_port 0
set_capability_reg_enable 0
set_user_identifier 0
set_csr_soft_logic_enable 0
dbg_embedded_debug_enable 0
dbg_capability_reg_enable 0
dbg_user_identifier 0
dbg_stat_soft_logic_enable 0
dbg_ctrl_soft_logic_enable 0
rcfg_file_prefix altera_xcvr_cdr_pll_a10
rcfg_sv_file_enable 0
rcfg_h_file_enable 0
rcfg_txt_file_enable 0
rcfg_mif_file_enable 0
cdr_pll_silicon_rev 20nm5
cdr_pll_pma_width 8
cdr_pll_cgb_div 1
cdr_pll_is_cascaded_pll false
cdr_pll_bandwidth_range_high 0 hz
cdr_pll_bandwidth_range_low 0 hz
cdr_pll_datarate 5000000000 bps
cdr_pll_f_max_pfd 350000000 Hz
cdr_pll_f_max_ref 800000000 Hz
cdr_pll_f_max_vco 9800000000 Hz
cdr_pll_f_min_gt_channel 8700000000 Hz
cdr_pll_f_min_pfd 50000000 Hz
cdr_pll_f_min_ref 50000000 Hz
cdr_pll_f_min_vco 4900000000 Hz
cdr_pll_lpd_counter 0
cdr_pll_lpfd_counter 2
cdr_pll_n_counter_scratch 1
cdr_pll_output_clock_frequency 2500000000 Hz
cdr_pll_reference_clock_frequency 125000000 Hz
cdr_pll_set_cdr_vco_speed 3
cdr_pll_set_cdr_vco_speed_fix 60
cdr_pll_vco_freq 5000000000 Hz
cdr_pll_atb_select_control atb_off
cdr_pll_auto_reset_on auto_reset_off
cdr_pll_bbpd_data_pattern_filter_select bbpd_data_pat_off
cdr_pll_bw_sel medium
cdr_pll_cdr_odi_select sel_cdr
cdr_pll_cdr_phaselock_mode no_ignore_lock
cdr_pll_cdr_powerdown_mode power_up
cdr_pll_chgpmp_current_pd cp_current_pd_setting0
cdr_pll_chgpmp_current_pfd cp_current_pfd_setting3
cdr_pll_chgpmp_replicate false
cdr_pll_chgpmp_testmode cp_test_disable
cdr_pll_clklow_mux_select clklow_mux_cdr_fbclk
cdr_pll_diag_loopback_enable false
cdr_pll_disable_up_dn true
cdr_pll_fref_clklow_div 1
cdr_pll_fref_mux_select fref_mux_cdr_refclk
cdr_pll_gpon_lck2ref_control gpon_lck2ref_off
cdr_pll_initial_settings true
cdr_pll_lck2ref_delay_control lck2ref_delay_2
cdr_pll_lf_resistor_pd lf_pd_setting0
cdr_pll_lf_resistor_pfd lf_pfd_setting2
cdr_pll_lf_ripple_cap lf_no_ripple
cdr_pll_loop_filter_bias_select lpflt_bias_7
cdr_pll_loopback_mode loopback_disabled
cdr_pll_ltd_ltr_micro_controller_select ltd_ltr_pcs
cdr_pll_m_counter 20
cdr_pll_n_counter 1
cdr_pll_optimal false
cdr_pll_pd_fastlock_mode false
cdr_pll_pd_l_counter 0
cdr_pll_pfd_l_counter 2
cdr_pll_position position_unknown
cdr_pll_power_mode low_power
cdr_pll_primary_use cmu
cdr_pll_prot_mode unused
cdr_pll_requires_gt_capable_channel false
cdr_pll_reverse_serial_loopback no_loopback
cdr_pll_set_cdr_v2i_enable true
cdr_pll_set_cdr_vco_reset false
cdr_pll_set_cdr_vco_speed_pciegen3 cdr_vco_max_speedbin_pciegen3
cdr_pll_side side_unknown
cdr_pll_pm_speed_grade i2
cdr_pll_sup_mode user_mode
cdr_pll_top_or_bottom tb_unknown
cdr_pll_tx_pll_prot_mode txpll_enable
cdr_pll_txpll_hclk_driver_enable false
cdr_pll_vco_overrange_voltage vco_overrange_off
cdr_pll_vco_underrange_voltage vco_underange_off
cdr_pll_fb_select direct_fb
cdr_pll_uc_ro_cal uc_ro_cal_on
cdr_pll_uc_ro_cal_status uc_ro_cal_notdone
cdr_pll_iqclk_mux_sel power_down
cdr_pll_uc_cru_rstb cdr_lf_reset_off
cdr_pll_pcie_gen non_pcie
cdr_pll_analog_mode user_custom
cdr_pll_f_max_m_counter 1
cdr_pll_chgpmp_vccreg vreg_fw0
cdr_pll_set_cdr_input_freq_range 0
cdr_pll_chgpmp_current_dn_trim cp_current_trimming_dn_setting0
cdr_pll_chgpmp_up_pd_trim_double normal_up_trim_current
cdr_pll_chgpmp_current_up_pd cp_current_pd_up_setting0
cdr_pll_f_max_cmu_out_freq 1
cdr_pll_chgpmp_current_up_trim cp_current_trimming_up_setting0
cdr_pll_chgpmp_dn_pd_trim_double normal_dn_trim_current
cdr_pll_cal_vco_count_length sel_8b_count
cdr_pll_chgpmp_current_dn_pd cp_current_pd_dn_setting0
cdr_pll_enable_idle_rx_channel_support false
enable_advanced_options 0
generate_docs 0
generate_add_hdl_instance_example 0
enable_analog_resets 0
device_family ARRIA10
base_device NIGHTFURY5
device 10AX115S2F45I1SG
message_level error
speed_grade i2
bw_sel Medium
refclk_cnt 1
refclk_index 0
bw_sel_atom medium
device_revision 20nm5
support_mode user_mode
select_manual_config false
reference_clock_frequency 125.0
output_clock_frequency 2500
cdr_pll_out_clock_frequency 2500 MHz
cdr_pll_ref_clock_frequency 125.0 MHz
cdr_pll_mcounter 20
cdr_pll_ncounter 1
cdr_pll_pfd_lcounter 2
cdr_pll_pd_lcounter 0
manual_counters
auto_counters refclk 125.000000 m_cnt 20 n_cnt 1 lpfd_cnt 2 lpd_cnt 0 fvco 5000
vco_freq 5000 MHz
datarate 5000 Mbps
primary_use cmu
gui_tx_pll_prot_mode Basic
diag_loopback_enable false
loopback_mode loopback_disabled
tx_pll_prot_mode txpll_enable
refclk_select_mux_powerdown_mode powerup
dummy_embedded_debug_warning 0
set_altera_xcvr_cdr_pll_a10_calibration_en 1
calibration_en enable
pma_cdr_refclk_select_mux_silicon_rev 20nm5
pma_cdr_refclk_select_mux_refclk_select ref_iqclk0
pma_cdr_refclk_select_mux_powerdown_mode powerup
pma_cdr_refclk_select_mux_inclk0_logical_to_physical_mapping ref_iqclk0
pma_cdr_refclk_select_mux_inclk1_logical_to_physical_mapping power_down
pma_cdr_refclk_select_mux_inclk2_logical_to_physical_mapping power_down
pma_cdr_refclk_select_mux_inclk3_logical_to_physical_mapping power_down
pma_cdr_refclk_select_mux_inclk4_logical_to_physical_mapping power_down
cmu_refclk_select 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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