rcfg_debug |
0 |
enable_pll_reconfig |
0 |
enable_advanced_avmm_options |
0 |
rcfg_jtag_enable |
0 |
rcfg_separate_avmm_busy |
0 |
rcfg_enable_avmm_busy_port |
0 |
set_capability_reg_enable |
0 |
set_user_identifier |
0 |
set_csr_soft_logic_enable |
0 |
dbg_embedded_debug_enable |
0 |
dbg_capability_reg_enable |
0 |
dbg_user_identifier |
0 |
dbg_stat_soft_logic_enable |
0 |
dbg_ctrl_soft_logic_enable |
0 |
rcfg_file_prefix |
altera_xcvr_fpll_a10 |
rcfg_sv_file_enable |
0 |
rcfg_h_file_enable |
0 |
rcfg_txt_file_enable |
0 |
rcfg_mif_file_enable |
0 |
system_info_device_family |
ARRIA10 |
cmu_fpll_silicon_rev |
20nm5 |
cmu_fpll_bandwidth_range_high |
1 |
cmu_fpll_bandwidth_range_low |
1 |
cmu_fpll_is_otn |
false |
cmu_fpll_is_sdi |
false |
cmu_fpll_bonding |
pll_bonding |
cmu_fpll_f_max_band_0 |
3861860000 |
cmu_fpll_f_max_band_1 |
4287223000 |
cmu_fpll_f_max_band_2 |
4688476000 |
cmu_fpll_f_max_band_3 |
5072700000 |
cmu_fpll_f_max_band_4 |
5423191000 |
cmu_fpll_f_max_band_5 |
5762211000 |
cmu_fpll_f_max_band_6 |
6075045000 |
cmu_fpll_f_max_band_7 |
6374148000 |
cmu_fpll_f_max_band_8 |
14025000000 |
cmu_fpll_f_max_pfd |
800000000 |
cmu_fpll_f_max_vco |
12500000000 |
cmu_fpll_f_min_band_0 |
7000000000 |
cmu_fpll_f_min_band_1 |
3861860000 |
cmu_fpll_f_min_band_2 |
4287223000 |
cmu_fpll_f_min_band_3 |
4688476000 |
cmu_fpll_f_min_band_4 |
5072700000 |
cmu_fpll_f_min_band_5 |
5423191000 |
cmu_fpll_f_min_band_6 |
5762211000 |
cmu_fpll_f_min_band_7 |
6075045000 |
cmu_fpll_f_min_band_8 |
6374148000 |
cmu_fpll_f_min_pfd |
50000000 |
cmu_fpll_f_min_vco |
6000000000 |
cmu_fpll_feedback |
normal |
cmu_fpll_fpll_cas_out_enable |
fpll_cas_out_disable |
cmu_fpll_fpll_hclk_out_enable |
fpll_hclk_out_disable |
cmu_fpll_fpll_iqtxrxclk_out_enable |
fpll_iqtxrxclk_out_disable |
cmu_fpll_l_counter |
8 |
cmu_fpll_m_counter |
40 |
cmu_fpll_n_counter |
1 |
cmu_fpll_out_freq_hz |
0 hz |
cmu_fpll_out_freq |
000000100101010000001011111001000000 |
cmu_fpll_pll_vco_freq_band_0 |
pll_freq_band0 |
cmu_fpll_pll_vco_freq_band_1 |
pll_freq_band0_1 |
cmu_fpll_primary_use |
tx |
cmu_fpll_prot_mode |
basic_tx |
cmu_fpll_reference_clock_frequency_scratch |
0 hz |
cmu_fpll_side |
side_unknown |
cmu_fpll_top_or_bottom |
tb_unknown |
cmu_fpll_vco_freq_hz |
10000000000 |
cmu_fpll_vco_freq |
001001010100000010111110010000000000 |
cmu_fpll_pll_bw_mode |
hi_bw |
cmu_fpll_datarate |
1250000000 bps |
cmu_fpll_pll_device_variant |
device1 |
cmu_fpll_pll_cal_status |
false |
cmu_fpll_pll_calibration |
true |
cmu_fpll_pll_cmu_rstn_value |
true |
cmu_fpll_pll_lpf_rstn_value |
lpf_normal |
cmu_fpll_pll_ppm_clk0_src |
ppm_clk0_vss |
cmu_fpll_pll_ppm_clk1_src |
ppm_clk1_vss |
cmu_fpll_pll_rstn_override |
false |
cmu_fpll_pll_op_mode |
false |
cmu_fpll_pll_optimal |
true |
cmu_fpll_is_pa_core |
false |
cmu_fpll_power_mode |
low_power |
cmu_fpll_power_rail_et |
0 |
cmu_fpll_pll_powerdown_mode |
false |
cmu_fpll_pm_speed_grade |
e2 |
cmu_fpll_pll_sup_mode |
user_mode |
cmu_fpll_pll_c0_pllcout_enable |
false |
cmu_fpll_pll_c_counter_0 |
1 |
cmu_fpll_pll_c_counter_0_min_tco_enable |
false |
cmu_fpll_pll_c_counter_0_in_src |
m_cnt_in_src_test_clk |
cmu_fpll_pll_c_counter_0_ph_mux_prst |
0 |
cmu_fpll_pll_c_counter_0_prst |
1 |
cmu_fpll_pll_c_counter_0_coarse_dly |
0 ps |
cmu_fpll_pll_c_counter_0_fine_dly |
0 ps |
cmu_fpll_pll_c1_pllcout_enable |
false |
cmu_fpll_pll_c_counter_1 |
1 |
cmu_fpll_pll_c_counter_1_min_tco_enable |
false |
cmu_fpll_pll_c_counter_1_in_src |
m_cnt_in_src_test_clk |
cmu_fpll_pll_c_counter_1_ph_mux_prst |
0 |
cmu_fpll_pll_c_counter_1_prst |
1 |
cmu_fpll_pll_c_counter_1_coarse_dly |
0 ps |
cmu_fpll_pll_c_counter_1_fine_dly |
0 ps |
cmu_fpll_pll_c2_pllcout_enable |
false |
cmu_fpll_pll_c_counter_2 |
1 |
cmu_fpll_pll_c_counter_2_min_tco_enable |
false |
cmu_fpll_pll_c_counter_2_in_src |
m_cnt_in_src_test_clk |
cmu_fpll_pll_c_counter_2_ph_mux_prst |
0 |
cmu_fpll_pll_c_counter_2_prst |
1 |
cmu_fpll_pll_c_counter_2_coarse_dly |
0 ps |
cmu_fpll_pll_c_counter_2_fine_dly |
0 ps |
cmu_fpll_pll_c3_pllcout_enable |
false |
cmu_fpll_pll_c_counter_3 |
1 |
cmu_fpll_pll_c_counter_3_min_tco_enable |
false |
cmu_fpll_pll_c_counter_3_in_src |
m_cnt_in_src_test_clk |
cmu_fpll_pll_c_counter_3_ph_mux_prst |
0 |
cmu_fpll_pll_c_counter_3_prst |
1 |
cmu_fpll_pll_c_counter_3_coarse_dly |
0 ps |
cmu_fpll_pll_c_counter_3_fine_dly |
0 ps |
cmu_fpll_pll_core_cali_ref_off |
true |
cmu_fpll_pll_core_cali_vco_off |
true |
cmu_fpll_pll_core_vccdreg_fb |
vreg_fb5 |
cmu_fpll_pll_core_vccdreg_fw |
vreg_fw5 |
cmu_fpll_pll_core_vreg0_atbsel |
atb_disabled |
cmu_fpll_pll_core_vreg1_atbsel |
atb_disabled1 |
cmu_fpll_pll_atb |
atb_selectdisable |
cmu_fpll_pll_cmp_buf_dly |
0 ps |
cmu_fpll_pll_fbclk_mux_1 |
pll_fbclk_mux_1_glb |
cmu_fpll_pll_fbclk_mux_2 |
pll_fbclk_mux_2_m_cnt |
cmu_fpll_pll_iqclk_mux_sel |
power_down |
cmu_fpll_pll_cp_compensation |
true |
cmu_fpll_pll_cp_current_setting |
cp_current_setting26 |
cmu_fpll_pll_cp_testmode |
cp_normal |
cmu_fpll_pll_cp_lf_3rd_pole_freq |
lf_3rd_pole_setting0 |
cmu_fpll_pll_lf_cbig |
lf_cbig_setting4 |
cmu_fpll_pll_cp_lf_order |
lf_2nd_order |
cmu_fpll_pll_lf_resistance |
lf_res_setting1 |
cmu_fpll_pll_lf_ripplecap |
lf_no_ripple |
cmu_fpll_pll_vco_ph0_en |
true |
cmu_fpll_pll_vco_ph0_value |
pll_vco_ph0_vss |
cmu_fpll_pll_vco_ph1_en |
false |
cmu_fpll_pll_vco_ph1_value |
pll_vco_ph1_vss |
cmu_fpll_pll_vco_ph2_en |
false |
cmu_fpll_pll_vco_ph2_value |
pll_vco_ph2_vss |
cmu_fpll_pll_vco_ph3_en |
false |
cmu_fpll_pll_vco_ph3_value |
pll_vco_ph3_vss |
cmu_fpll_pll_dsm_mode |
dsm_mode_integer |
cmu_fpll_pll_dsm_out_sel |
pll_dsm_disable |
cmu_fpll_pll_dsm_ecn_bypass |
false |
cmu_fpll_pll_dsm_ecn_test_en |
false |
cmu_fpll_pll_dsm_fractional_division |
1 |
cmu_fpll_pll_dsm_fractional_value_ready |
pll_k_ready |
cmu_fpll_pll_l_counter_bypass |
false |
cmu_fpll_pll_l_counter |
8 |
cmu_fpll_pll_l_counter_enable |
true |
cmu_fpll_pll_lock_fltr_cfg |
25 |
cmu_fpll_pll_lock_fltr_test |
pll_lock_fltr_nrm |
cmu_fpll_pll_unlock_fltr_cfg |
2 |
cmu_fpll_pll_m_counter |
40 |
cmu_fpll_pll_m_counter_min_tco_enable |
false |
cmu_fpll_pll_m_counter_in_src |
m_cnt_in_src_ph_mux_clk |
cmu_fpll_pll_m_counter_ph_mux_prst |
0 |
cmu_fpll_pll_m_counter_prst |
1 |
cmu_fpll_pll_m_counter_coarse_dly |
0 ps |
cmu_fpll_pll_m_counter_fine_dly |
0 ps |
cmu_fpll_pll_n_counter |
1 |
cmu_fpll_pll_n_counter_coarse_dly |
0 ps |
cmu_fpll_pll_n_counter_fine_dly |
0 ps |
cmu_fpll_pll_ref_buf_dly |
0 ps |
cmu_fpll_pll_tclk_mux_en |
false |
cmu_fpll_pll_tclk_sel |
pll_tclk_m_src |
cmu_fpll_pll_dprio_base_addr |
256 |
cmu_fpll_pll_dprio_broadcast_en |
false |
cmu_fpll_pll_dprio_clk_vreg_boost |
clk_fpll_vreg_no_voltage_boost |
cmu_fpll_pll_dprio_cvp_inter_sel |
false |
cmu_fpll_pll_dprio_force_inter_sel |
false |
cmu_fpll_pll_dprio_fpll_vreg_boost |
fpll_vreg_boost_1_step |
cmu_fpll_pll_dprio_fpll_vreg1_boost |
fpll_vreg1_boost_1_step |
cmu_fpll_pll_dprio_power_iso_en |
false |
cmu_fpll_pll_dprio_status_select |
dprio_normal_status |
cmu_fpll_pll_extra_csr |
0 |
cmu_fpll_pll_nreset_invert |
false |
cmu_fpll_pll_ctrl_override_setting |
true |
cmu_fpll_pll_enable |
true |
cmu_fpll_pll_self_reset |
false |
cmu_fpll_pll_test_enable |
false |
cmu_fpll_pll_ctrl_plniotri_override |
false |
cmu_fpll_pll_vccr_pd_en |
true |
cmu_fpll_bw_sel |
high |
cmu_fpll_compensation_mode |
direct |
cmu_fpll_duty_cycle_0 |
50 |
cmu_fpll_duty_cycle_1 |
50 |
cmu_fpll_duty_cycle_2 |
50 |
cmu_fpll_duty_cycle_3 |
50 |
cmu_fpll_hssi_output_clock_frequency |
625.0 MHz |
cmu_fpll_is_cascaded_pll |
false |
cmu_fpll_output_clock_frequency_0 |
0 ps |
cmu_fpll_output_clock_frequency_1 |
0 ps |
cmu_fpll_output_clock_frequency_2 |
0 ps |
cmu_fpll_output_clock_frequency_3 |
0 ps |
cmu_fpll_phase_shift_0 |
0 ps |
cmu_fpll_phase_shift_1 |
0 ps |
cmu_fpll_phase_shift_2 |
0 ps |
cmu_fpll_phase_shift_3 |
0 ps |
cmu_fpll_reference_clock_frequency |
125.0 MHz |
cmu_fpll_vco_frequency |
10000.0 MHz |
cmu_fpll_cgb_div |
1 |
cmu_fpll_pma_width |
64 |
cmu_fpll_f_out_c3_hz |
0 hz |
cmu_fpll_f_out_c1_hz |
0 hz |
cmu_fpll_f_out_c0_hz |
0 hz |
cmu_fpll_f_out_c2_hz |
0 hz |
cmu_fpll_f_out_c3 |
000000000000000000000000000000000000 |
cmu_fpll_f_out_c1 |
000000000000000000000000000000000000 |
cmu_fpll_f_out_c0 |
000000000000000000000000000000000000 |
cmu_fpll_f_out_c2 |
000000000000000000000000000000000000 |
cmu_fpll_output_tolerance |
0 |
cmu_fpll_f_min_band_9 |
1 |
cmu_fpll_initial_settings |
true |
cmu_fpll_f_max_band_9 |
1 |
cmu_fpll_analog_mode |
user_custom |
cmu_fpll_min_fractional_percentage |
1 |
cmu_fpll_max_fractional_percentage |
99 |
cmu_fpll_f_max_vco_fractional |
14025000000 |
cmu_fpll_input_tolerance |
0 |
cmu_fpll_m_counter_c2 |
1 |
cmu_fpll_m_counter_c3 |
1 |
cmu_fpll_m_counter_c0 |
1 |
cmu_fpll_m_counter_c1 |
1 |
cmu_fpll_pfd_freq |
000000000111011100110101100101000000 |
cmu_fpll_f_max_pfd_fractional |
800000000 |
cmu_fpll_pll_vco_freq_band_0_fix_high |
pll_vco_freq_band_0_fix_high_0 |
cmu_fpll_pll_vco_freq_band_1_fix_high |
pll_vco_freq_band_1_fix_high_0 |
cmu_fpll_xpm_cmu_fpll_core_cal_vco_count_length |
sel_8b_count |
cmu_fpll_xpm_cmu_fpll_core_pfd_pulse_width |
pulse_width_setting0 |
cmu_fpll_xpm_cmu_fpll_core_fpll_vco_div_by_2_sel |
bypass_divide_by_2 |
cmu_fpll_pll_vco_freq_band_1_dyn_high_bits |
0 |
cmu_fpll_set_fpll_input_freq_range |
0 |
cmu_fpll_f_max_pfd_integer |
800000000 |
cmu_fpll_pll_vco_freq_band_0_fix |
1 |
cmu_fpll_f_max_pfd_bonded |
600000000 |
cmu_fpll_pll_vco_freq_band_0_dyn_high_bits |
0 |
cmu_fpll_pll_vco_freq_band_1_fix |
1 |
cmu_fpll_xpm_cmu_fpll_core_xpm_cpvco_fpll_xpm_chgpmplf_fpll_cp_current_boost |
normal_setting |
cmu_fpll_xpm_cmu_fpll_core_fpll_refclk_source |
normal_refclk |
cmu_fpll_fpll_cal_test_sel |
sel_cal_out_7_to_0 |
cmu_fpll_pll_vco_freq_band_0_dyn_low_bits |
0 |
cmu_fpll_f_max_div_two_bypass |
1 |
cmu_fpll_xpm_cmu_fpll_core_pfd_delay_compensation |
normal_delay |
cmu_fpll_pll_vco_freq_band_1_dyn_low_bits |
0 |
cmu_fpll_enable_idle_fpll_support |
idle_none |
cmu_fpll_refclk_select_mux_pll_clk_sel_override |
normal |
cmu_fpll_refclk_select_mux_pll_clk_sel_override_value |
select_clk0 |
cmu_fpll_refclk_select_mux_pll_clkin_0_scratch0_src |
pll_clkin_0_scratch0_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_0_scratch1_src |
pll_clkin_0_scratch1_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_0_scratch2_src |
pll_clkin_0_scratch2_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_0_scratch3_src |
pll_clkin_0_scratch3_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_0_scratch4_src |
pll_clkin_0_scratch4_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_1_scratch0_src |
pll_clkin_1_scratch0_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_1_scratch1_src |
pll_clkin_1_scratch1_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_1_scratch2_src |
pll_clkin_1_scratch2_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_1_scratch3_src |
pll_clkin_1_scratch3_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_1_scratch4_src |
pll_clkin_1_scratch4_src_vss |
cmu_fpll_refclk_select_mux_pll_powerdown_mode |
false |
cmu_fpll_refclk_select_mux_pll_sup_mode |
user_mode |
cmu_fpll_refclk_select_mux_pll_clkin_0_src |
pll_clkin_0_src_vss |
cmu_fpll_refclk_select_mux_pll_clkin_1_src |
pll_clkin_1_src_vss |
cmu_fpll_refclk_select_mux_pll_auto_clk_sw_en |
false |
cmu_fpll_refclk_select_mux_pll_clk_loss_edge |
pll_clk_loss_both_edges |
cmu_fpll_refclk_select_mux_pll_clk_loss_sw_en |
false |
cmu_fpll_refclk_select_mux_pll_clk_sw_dly |
0 |
cmu_fpll_refclk_select_mux_pll_manu_clk_sw_en |
false |
cmu_fpll_refclk_select_mux_pll_sw_refclk_src |
pll_sw_refclk_src_clk_0 |
cmu_fpll_refclk_select_mux_xpm_iqref_mux0_iqclk_sel |
power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux0_scratch0_src |
scratch0_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux0_scratch1_src |
scratch1_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux0_scratch2_src |
scratch2_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux0_scratch3_src |
scratch3_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux0_scratch4_src |
scratch4_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux1_iqclk_sel |
power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux1_scratch0_src |
scratch0_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux1_scratch1_src |
scratch1_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux1_scratch2_src |
scratch2_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux1_scratch3_src |
scratch3_power_down |
cmu_fpll_refclk_select_mux_xpm_iqref_mux1_scratch4_src |
scratch4_power_down |
cmu_fpll_refclk_select_mux_silicon_rev |
20nm5es |
cmu_fpll_refclk_select_mux_refclk_select0 |
lvpecl |
cmu_fpll_refclk_select_mux_refclk_select1 |
ref_iqclk0 |
cmu_fpll_refclk_select_mux_mux0_inclk0_logical_to_physical_mapping |
lvpecl |
cmu_fpll_refclk_select_mux_mux0_inclk1_logical_to_physical_mapping |
power_down |
cmu_fpll_refclk_select_mux_mux0_inclk2_logical_to_physical_mapping |
power_down |
cmu_fpll_refclk_select_mux_mux0_inclk3_logical_to_physical_mapping |
power_down |
cmu_fpll_refclk_select_mux_mux0_inclk4_logical_to_physical_mapping |
power_down |
cmu_fpll_refclk_select_mux_mux1_inclk0_logical_to_physical_mapping |
lvpecl |
cmu_fpll_refclk_select_mux_mux1_inclk1_logical_to_physical_mapping |
power_down |
cmu_fpll_refclk_select_mux_mux1_inclk2_logical_to_physical_mapping |
power_down |
cmu_fpll_refclk_select_mux_mux1_inclk3_logical_to_physical_mapping |
power_down |
cmu_fpll_refclk_select_mux_mux1_inclk4_logical_to_physical_mapping |
power_down |
gui_pll_set_hssi_m_counter |
8 |
gui_pll_set_hssi_n_counter |
1 |
gui_pll_set_hssi_l_counter |
1 |
gui_pll_set_hssi_k_counter |
1 |
device_family |
Arria 10 |
device |
10AX115S2F45I2SG |
base_device |
NIGHTFURY5 |
device_revision |
20nm5 |
device_speed_grade |
i2 |
numeric_speed_grade |
1 |
gui_fpll_mode |
2 |
primary_use |
tx |
gui_hssi_prot_mode |
0 |
prot_mode |
basic_tx |
gui_refclk_switch |
false |
gui_refclk1_frequency |
100.0 |
gui_switchover_mode |
Automatic Switchover |
gui_switchover_delay |
0 |
gui_enable_active_clk |
false |
gui_enable_clk_bad |
false |
gui_enable_extswitch |
false |
enable_advanced_options |
0 |
enable_hip_options |
0 |
generate_docs |
0 |
generate_add_hdl_instance_example |
0 |
gui_bw_sel |
high |
temp_bw_sel |
high |
pll_cp_lf_3rd_pole_freq |
lf_3rd_pole_setting0 |
gui_self_reset_enabled |
false |
gui_enable_low_f_support |
false |
gui_is_downstream_cascaded_pll |
false |
gui_enable_50G_support |
false |
silicon_rev |
false |
gui_silicon_rev |
20nm5es |
gui_reference_clock_frequency |
100.0 |
gui_desired_refclk_frequency |
125.0 |
gui_actual_refclk_frequency |
100.0 |
full_actual_refclk_frequency |
125.0 |
reference_clock_frequency |
125.0 MHz |
gui_operation_mode |
0 |
compensation_mode |
direct |
feedback |
normal |
gui_enable_iqtxrxclk_mode |
false |
gui_iqtxrxclk_outclk_index |
0 |
gui_refclk_cnt |
1 |
gui_refclk_index |
0 |
gui_enable_fractional |
false |
gui_enable_manual_hssi_counters |
false |
enable_cascade_in |
0 |
enable_analog_resets |
0 |
gui_enable_pld_cal_busy_port |
1 |
gui_enable_hip_cal_done_port |
0 |
gui_hip_cal_en |
0 |
hip_cal_en |
disable |
gui_enable_cascade_out |
false |
gui_cascade_outclk_index |
0 |
gui_enable_dps |
false |
gui_enable_manual_config |
false |
gui_hssi_calc_output_clock_frequency |
1250.0 |
gui_hssi_output_clock_frequency |
625.0 |
hssi_output_clock_frequency |
625.0 MHz |
gui_pll_datarate |
1250.0 |
pll_datarate |
1250000000 bps |
gui_pll_m_counter |
1 |
gui_pll_n_counter |
1 |
gui_fractional_x |
32 |
gui_pll_dsm_fractional_division |
1 |
gui_fractional_f |
0.0 |
gui_pll_c_counter_0 |
1 |
gui_pll_c_counter_1 |
1 |
gui_pll_c_counter_2 |
1 |
gui_pll_c_counter_3 |
1 |
gui_number_of_output_clocks |
1 |
gui_enable_phase_alignment |
false |
phase_alignment_check_var |
false |
gui_pfd_frequency |
100.0 |
core_vco_frequency_basic |
10000.0 |
core_vco_frequency_adv |
300.0 MHz |
hssi_vco_frequency |
10000.0 |
hssi_cascade_vco_frequency |
300.0 MHz |
vco_frequency |
10000.0 MHz |
core_pfd_frequency |
300.0 MHz |
hssi_pfd_frequency |
125.0 |
hssi_cascade_pfd_frequency |
300.0 MHz |
pfd_frequency |
125.0 MHz |
gui_desired_outclk0_frequency |
100.0 |
gui_actual_outclk0_frequency |
100.0 |
full_actual_outclk0_frequency |
|
output_clock_frequency_0 |
0 ps |
gui_outclk0_phase_shift_unit |
0 |
gui_outclk0_desired_phase_shift |
0.0 |
gui_outclk0_actual_phase_shift |
0.0 |
gui_outclk0_actual_phase_shift_deg |
0.0 |
full_outclk0_actual_phase_shift |
|
phase_shift_0 |
0 ps |
gui_desired_outclk1_frequency |
100.0 |
gui_actual_outclk1_frequency |
100.0 |
full_actual_outclk1_frequency |
|
output_clock_frequency_1 |
0 ps |
gui_outclk1_phase_shift_unit |
0 |
gui_outclk1_desired_phase_shift |
0 |
gui_outclk1_actual_phase_shift |
0.0 |
gui_outclk1_actual_phase_shift_deg |
0.0 |
full_outclk1_actual_phase_shift |
|
phase_shift_1 |
0 ps |
gui_desired_outclk2_frequency |
100.0 |
gui_actual_outclk2_frequency |
100.0 |
full_actual_outclk2_frequency |
|
output_clock_frequency_2 |
0 ps |
gui_outclk2_phase_shift_unit |
0 |
gui_outclk2_desired_phase_shift |
0 |
gui_outclk2_actual_phase_shift |
0 ps |
gui_outclk2_actual_phase_shift_deg |
0 deg |
full_outclk2_actual_phase_shift |
|
phase_shift_2 |
0 ps |
gui_desired_outclk3_frequency |
100.0 |
gui_actual_outclk3_frequency |
100.0 |
full_actual_outclk3_frequency |
|
output_clock_frequency_3 |
0 ps |
gui_outclk3_phase_shift_unit |
0 |
gui_outclk3_desired_phase_shift |
0 |
gui_outclk3_actual_phase_shift |
0.0 |
gui_outclk3_actual_phase_shift_deg |
0.0 |
full_outclk3_actual_phase_shift |
|
phase_shift_3 |
0 ps |
gui_desired_hssi_cascade_frequency |
100.0 |
refclk_select0 |
lvpecl |
refclk_select1 |
ref_iqclk0 |
core_c_counter_0 |
1 |
core_c_counter_0_in_src |
m_cnt_in_src_ph_mux_clk |
core_c_counter_0_ph_mux_prst |
0 |
core_c_counter_0_prst |
1 |
core_c_counter_0_coarse_dly |
0 ps |
core_c_counter_0_fine_dly |
0 ps |
core_c_counter_1 |
1 |
core_c_counter_1_in_src |
m_cnt_in_src_ph_mux_clk |
core_c_counter_1_ph_mux_prst |
0 |
core_c_counter_1_prst |
1 |
core_c_counter_1_coarse_dly |
0 ps |
core_c_counter_1_fine_dly |
0 ps |
core_c_counter_2 |
1 |
core_c_counter_2_in_src |
m_cnt_in_src_ph_mux_clk |
core_c_counter_2_ph_mux_prst |
0 |
core_c_counter_2_prst |
1 |
core_c_counter_2_coarse_dly |
0 ps |
core_c_counter_2_fine_dly |
0 ps |
core_c_counter_3 |
1 |
core_c_counter_3_in_src |
m_cnt_in_src_ph_mux_clk |
core_c_counter_3_ph_mux_prst |
0 |
core_c_counter_3_prst |
1 |
core_c_counter_3_coarse_dly |
0 ps |
core_c_counter_3_fine_dly |
0 ps |
hssi_l_counter |
8 |
hssi_l_counter_in_src |
m_cnt_in_src_ph_mux_clk |
hssi_l_counter_ph_mux_prst |
0 |
hssi_l_counter_bypass |
0 |
hssi_l_counter_enable |
true |
hssi_pcie_c_counter_0 |
1 |
hssi_pcie_c_counter_0_in_src |
m_cnt_in_src_ph_mux_clk |
hssi_pcie_c_counter_0_ph_mux_prst |
0 |
hssi_pcie_c_counter_0_prst |
1 |
hssi_pcie_c_counter_0_coarse_dly |
0 ps |
hssi_pcie_c_counter_0_fine_dly |
0 ps |
hssi_cascade_c_counter |
1 |
hssi_cascade_c_counter_in_src |
m_cnt_in_src_ph_mux_clk |
hssi_cascade_c_counter_ph_mux_prst |
0 |
hssi_cascade_c_counter_prst |
1 |
hssi_cascade_c_counter_coarse_dly |
0 ps |
hssi_cascade_c_counter_fine_dly |
0 ps |
pll_m_counter_in_src |
m_cnt_in_src_ph_mux_clk |
pll_c_counter_0 |
1 |
pll_c_counter_0_in_src |
m_cnt_in_src_test_clk |
pll_c_counter_0_ph_mux_prst |
0 |
pll_c_counter_0_prst |
1 |
pll_c_counter_0_coarse_dly |
0 ps |
pll_c_counter_0_fine_dly |
0 ps |
pll_c_counter_1 |
1 |
pll_c_counter_1_in_src |
m_cnt_in_src_test_clk |
pll_c_counter_1_ph_mux_prst |
0 |
pll_c_counter_1_prst |
1 |
pll_c_counter_1_coarse_dly |
0 ps |
pll_c_counter_1_fine_dly |
0 ps |
pll_c_counter_2 |
1 |
pll_c_counter_2_in_src |
m_cnt_in_src_test_clk |
pll_c_counter_2_ph_mux_prst |
0 |
pll_c_counter_2_prst |
1 |
pll_c_counter_2_coarse_dly |
0 ps |
pll_c_counter_2_fine_dly |
0 ps |
pll_c_counter_3 |
1 |
pll_c_counter_3_in_src |
m_cnt_in_src_test_clk |
pll_c_counter_3_ph_mux_prst |
0 |
pll_c_counter_3_prst |
1 |
pll_c_counter_3_coarse_dly |
0 ps |
pll_c_counter_3_fine_dly |
0 ps |
pll_iqclk_mux_sel |
power_down |
pll_l_counter |
8 |
core_actual_using_fractional |
false |
hssi_actual_using_fractional |
false |
hssi_cascade_actual_using_fractional |
false |
pll_actual_using_fractional |
false |
core_dsm_fractional_division |
1 |
hssi_dsm_fractional_division |
0 |
hssi_cascade_dsm_fractional_division |
1 |
pll_dsm_fractional_division |
1 |
pll_dsm_mode |
dsm_mode_integer |
pll_dsm_out_sel |
pll_dsm_disable |
core_m_counter |
11 |
hssi_m_counter |
40 |
hssi_cascade_m_counter |
11 |
core_n_counter |
1 |
hssi_n_counter |
1 |
hssi_cascade_n_counter |
1 |
pll_m_counter |
40 |
pll_n_counter |
1 |
refclk_freq_bitvec |
000000000111011100110101100101000000 |
vco_freq_bitvec |
001001010100000010111110010000000000 |
pfd_freq_bitvec |
000000000111011100110101100101000000 |
output_freq_bitvec |
000000100101010000001011111001000000 |
f_out_c0_bitvec |
000000000000000000000000000000000000 |
f_out_c1_bitvec |
000000000000000000000000000000000000 |
f_out_c2_bitvec |
000000000000000000000000000000000000 |
f_out_c3_bitvec |
000000000000000000000000000000000000 |
l_counter_bitvec |
8 |
n_counter_bitvec |
1 |
m_counter_bitvec |
40 |
c_counter0_bitvec |
1 |
c_counter1_bitvec |
1 |
c_counter2_bitvec |
1 |
c_counter3_bitvec |
1 |
pma_width_bitvec |
64 |
cgb_div_bitvec |
1 |
pll_auto_clk_sw_en |
false |
pll_clk_loss_edge |
pll_clk_loss_both_edges |
pll_clk_loss_sw_en |
false |
pll_clk_sw_dly |
0 |
pll_manu_clk_sw_en |
false |
pll_sw_refclk_src |
pll_sw_refclk_src_clk_0 |
set_altera_xcvr_fpll_a10_calibration_en |
1 |
calibration_en |
enable |
support_mode |
user_mode |
enable_ext_lockdetect_ports |
0 |
is_c10 |
0 |
cmu_fpll_reconfig_en |
0 |
cmu_fpll_dps_en |
false |
cmu_fpll_calibration_en |
enable |
cmu_fpll_refclk_freq |
000000000111011100110101100101000000 |
fpll_refclk_select |
0 |
enable_mcgb |
0 |
mcgb_div |
1 |
mcgb_div_fnl |
1 |
enable_hfreq_clk |
0 |
enable_mcgb_pcie_clksw |
0 |
mcgb_aux_clkin_cnt |
0 |
mcgb_in_clk_freq |
625.0 |
mcgb_out_datarate |
1250.0 |
enable_bonding_clks |
0 |
enable_fb_comp_bonding |
0 |
mcgb_enable_iqtxrxclk |
disable_iqtxrxclk |
pma_width |
64 |
enable_mcgb_debug_ports_parameters |
0 |
enable_pld_mcgb_cal_busy_port |
0 |
check_output_ports_mcgb |
0 |
is_protocol_PCIe |
0 |
mapped_output_clock_frequency |
625.0 MHz |
mapped_primary_pll_buffer |
N/A |
mapped_hip_cal_done_port |
0 |
hssi_pma_cgb_master_prot_mode |
basic_tx |
hssi_pma_cgb_master_silicon_rev |
20nm5 |
hssi_pma_cgb_master_x1_div_m_sel |
divbypass |
hssi_pma_cgb_master_cgb_enable_iqtxrxclk |
disable_iqtxrxclk |
hssi_pma_cgb_master_ser_mode |
sixty_four_bit |
hssi_pma_cgb_master_datarate |
1250000000 bps |
hssi_pma_cgb_master_cgb_power_down |
normal_cgb |
hssi_pma_cgb_master_observe_cgb_clocks |
observe_nothing |
hssi_pma_cgb_master_op_mode |
enabled |
hssi_pma_cgb_master_tx_ucontrol_reset_pcie |
pcscorehip_controls_mcgb |
hssi_pma_cgb_master_vccdreg_output |
vccdreg_nominal |
hssi_pma_cgb_master_input_select |
fpll_top |
hssi_pma_cgb_master_input_select_gen3 |
unused |
gui_parameter_list |
C-counter-0,C-counter-1,C-counter-2,C-counter-3,L-counter,M-counter,N-counter,VCO Frequency,pll_dsm_fractional_division |
gui_parameter_values |
1,1,1,1,8,40,1,10000.0 MHz,1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |