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White Rabbit core collection
Commit 011b2c06 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'greg-sdbfs' into proposed_master

parents 26aea641 1cf866cc
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Showing with 30112 additions and 30015 deletions
bin/wrpc/wrc_phy8.bram
View file @ 011b2c06
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bin/wrpc/wrc_phy8.mif
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board/common/wr_board_pkg.vhd
View file @ 011b2c06
......@@ -64,6 +64,8 @@ package wr_board_pkg is
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for M25P128
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for M25P128
g_phys_uart : boolean := TRUE;
g_virtual_uart : boolean := TRUE;
g_aux_clks : integer := 0;
......
board/common/xwrc_board_common.vhd
View file @ 011b2c06
......@@ -54,6 +54,8 @@ entity xwrc_board_common is
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for M25P128
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for M25P128
g_phys_uart : boolean := TRUE;
g_virtual_uart : boolean := TRUE;
g_aux_clks : integer := 0;
......@@ -323,6 +325,8 @@ begin -- architecture struct
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => g_board_name,
g_flash_secsz_kb => g_flash_secsz_kb,
g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_aux_clks => g_aux_clks,
......
board/spec/xwrc_board_spec.vhd
View file @ 011b2c06
......@@ -420,6 +420,8 @@ begin -- architecture struct
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SPEC",
g_flash_secsz_kb => 64, -- sector size for M25P32
g_flash_sdbfs_baddr => 16#2e0000#, -- sdbfs after multiboot bitstream
g_phys_uart => TRUE,
g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks,
......
board/svec/xwrc_board_svec.vhd
View file @ 011b2c06
......@@ -426,6 +426,8 @@ begin -- architecture struct
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SVEC",
g_flash_secsz_kb => 256; -- default for M25P128
g_flash_sdbfs_baddr => 16#600000#; -- default for M25P128
g_phys_uart => TRUE,
g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks,
......
modules/wrc_core/wr_core.vhd
View file @ 011b2c06
......@@ -78,6 +78,8 @@ entity wr_core is
g_with_external_clock_input : boolean := true;
--
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
g_phys_uart : boolean := true;
g_virtual_uart : boolean := true;
g_aux_clks : integer := 0;
......@@ -876,6 +878,8 @@ begin
PERIPH : wrc_periph
generic map(
g_board_name => g_board_name,
g_flash_secsz_kb => g_flash_secsz_kb,
g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_mem_words => g_dpram_size,
......
modules/wrc_core/wrc_diags_pkg.vhd
View file @ 011b2c06
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_diags_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Mon Jul 3 13:40:08 2017
-- Created : Mon Nov 27 13:37:56 2017
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......
modules/wrc_core/wrc_diags_wb.vhd
View file @ 011b2c06
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_diags_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Tue Jun 20 09:59:03 2017
-- Created : Mon Nov 27 13:37:56 2017
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......
modules/wrc_core/wrc_periph.vhd
View file @ 011b2c06
......@@ -49,6 +49,8 @@ use work.wrc_diags_wbgen2_pkg.all;
entity wrc_periph is
generic(
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_cntr_period : integer := 62500;
......@@ -191,9 +193,12 @@ begin
sysc_regs_i.hwfr_memsize_i(3 downto 0) <= f_cnt_memsize(g_mem_words);
-------------------------------------
-- BOARD NAME
-- BOARD NAME and Flash info
-------------------------------------
sysc_regs_i.hwir_name_i <= f_board_name_conv(g_board_name);
sysc_regs_i.hwir_name_i <= f_board_name_conv(g_board_name);
sysc_regs_i.hwfr_storage_sec_i <= std_logic_vector(to_unsigned(g_flash_secsz_kb, 16));
sysc_regs_i.hwfr_storage_type_i <= "00"; -- for now these parameters are only for Flash
sysc_regs_i.sdbfs_baddr_i <= std_logic_vector(to_unsigned(g_flash_sdbfs_baddr, 32));
-------------------------------------
-- TIMER
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 011b2c06
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Mon Jul 3 13:40:08 2017
-- Created : Mon Nov 27 13:37:56 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -32,7 +32,10 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_i : std_logic;
gpsr_spi_miso_i : std_logic;
hwfr_memsize_i : std_logic_vector(3 downto 0);
hwfr_storage_type_i : std_logic_vector(1 downto 0);
hwfr_storage_sec_i : std_logic_vector(15 downto 0);
hwir_name_i : std_logic_vector(31 downto 0);
sdbfs_baddr_i : std_logic_vector(31 downto 0);
tcr_tdiv_i : std_logic_vector(11 downto 0);
tvr_i : std_logic_vector(31 downto 0);
diag_info_ver_i : std_logic_vector(15 downto 0);
......@@ -57,7 +60,10 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_i => '0',
gpsr_spi_miso_i => '0',
hwfr_memsize_i => (others => '0'),
hwfr_storage_type_i => (others => '0'),
hwfr_storage_sec_i => (others => '0'),
hwir_name_i => (others => '0'),
sdbfs_baddr_i => (others => '0'),
tcr_tdiv_i => (others => '0'),
tvr_i => (others => '0'),
diag_info_ver_i => (others => '0'),
......@@ -229,7 +235,10 @@ tmp.gpsr_spi_ncs_i := f_x_to_zero(left.gpsr_spi_ncs_i) or f_x_to_zero(right.gpsr
tmp.gpsr_spi_mosi_i := f_x_to_zero(left.gpsr_spi_mosi_i) or f_x_to_zero(right.gpsr_spi_mosi_i);
tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gpsr_spi_miso_i);
tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
tmp.hwfr_storage_type_i := f_x_to_zero(left.hwfr_storage_type_i) or f_x_to_zero(right.hwfr_storage_type_i);
tmp.hwfr_storage_sec_i := f_x_to_zero(left.hwfr_storage_sec_i) or f_x_to_zero(right.hwfr_storage_sec_i);
tmp.hwir_name_i := f_x_to_zero(left.hwir_name_i) or f_x_to_zero(right.hwir_name_i);
tmp.sdbfs_baddr_i := f_x_to_zero(left.sdbfs_baddr_i) or f_x_to_zero(right.sdbfs_baddr_i);
tmp.tcr_tdiv_i := f_x_to_zero(left.tcr_tdiv_i) or f_x_to_zero(right.tcr_tdiv_i);
tmp.tvr_i := f_x_to_zero(left.tvr_i) or f_x_to_zero(right.tvr_i);
tmp.diag_info_ver_i := f_x_to_zero(left.diag_info_ver_i) or f_x_to_zero(right.diag_info_ver_i);
......
modules/wrc_core/wrc_syscon_regs.h
View file @ 011b2c06
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Mon Jul 3 13:40:08 2017
* Created : Mon Nov 27 13:37:56 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -127,6 +127,18 @@
#define SYSC_HWFR_MEMSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define SYSC_HWFR_MEMSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Storage type in reg: Hardware Feature Register */
#define SYSC_HWFR_STORAGE_TYPE_MASK WBGEN2_GEN_MASK(8, 2)
#define SYSC_HWFR_STORAGE_TYPE_SHIFT 8
#define SYSC_HWFR_STORAGE_TYPE_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define SYSC_HWFR_STORAGE_TYPE_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Storage sector size in reg: Hardware Feature Register */
#define SYSC_HWFR_STORAGE_SEC_MASK WBGEN2_GEN_MASK(16, 16)
#define SYSC_HWFR_STORAGE_SEC_SHIFT 16
#define SYSC_HWFR_STORAGE_SEC_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define SYSC_HWFR_STORAGE_SEC_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Hardware Info Register */
/* definitions for field: Board name in reg: Hardware Info Register */
......@@ -135,6 +147,14 @@
#define SYSC_HWIR_NAME_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SYSC_HWIR_NAME_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Storage SDBFS info */
/* definitions for field: Base address in reg: Storage SDBFS info */
#define SYSC_SDBFS_BADDR_MASK WBGEN2_GEN_MASK(0, 32)
#define SYSC_SDBFS_BADDR_SHIFT 0
#define SYSC_SDBFS_BADDR_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SYSC_SDBFS_BADDR_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Timer Control Register */
/* definitions for field: Timer Divider in reg: Timer Control Register */
......@@ -269,54 +289,56 @@
#define SYSC_REG_HWFR 0x0000000c
/* [0x10]: REG Hardware Info Register */
#define SYSC_REG_HWIR 0x00000010
/* [0x14]: REG Timer Control Register */
#define SYSC_REG_TCR 0x00000014
/* [0x18]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x00000018
/* [0x1c]: REG User Diag: version register */
#define SYSC_REG_DIAG_INFO 0x0000001c
/* [0x20]: REG User Diag: number of words */
#define SYSC_REG_DIAG_NW 0x00000020
/* [0x24]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_CR 0x00000024
/* [0x28]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x00000028
/* [0x2c]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_CTRL 0x0000002c
/* [0x30]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_SSTAT 0x00000030
/* [0x34]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PSTAT 0x00000034
/* [0x38]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_PTPSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_ASTAT 0x0000003c
/* [0x40]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_TXFCNT 0x00000040
/* [0x44]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000044
/* [0x48]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_MSB 0x00000048
/* [0x4c]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x0000004c
/* [0x50]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_NS 0x00000050
/* [0x54]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000054
/* [0x58]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x00000058
/* [0x5c]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x0000005c
/* [0x60]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x00000060
/* [0x64]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000064
/* [0x68]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_CKO 0x00000068
/* [0x6c]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_SETP 0x0000006c
/* [0x70]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_UCNT 0x00000070
/* [0x74]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000074
/* [0x14]: REG Storage SDBFS info */
#define SYSC_REG_SDBFS 0x00000014
/* [0x18]: REG Timer Control Register */
#define SYSC_REG_TCR 0x00000018
/* [0x1c]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x0000001c
/* [0x20]: REG User Diag: version register */
#define SYSC_REG_DIAG_INFO 0x00000020
/* [0x24]: REG User Diag: number of words */
#define SYSC_REG_DIAG_NW 0x00000024
/* [0x28]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_CR 0x00000028
/* [0x2c]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x0000002c
/* [0x30]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_CTRL 0x00000030
/* [0x34]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_SSTAT 0x00000034
/* [0x38]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_PTPSTAT 0x0000003c
/* [0x40]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_ASTAT 0x00000040
/* [0x44]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_TXFCNT 0x00000044
/* [0x48]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000048
/* [0x4c]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_MSB 0x0000004c
/* [0x50]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x00000050
/* [0x54]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_NS 0x00000054
/* [0x58]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000058
/* [0x5c]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x0000005c
/* [0x60]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x00000060
/* [0x64]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x00000064
/* [0x68]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000068
/* [0x6c]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_CKO 0x0000006c
/* [0x70]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_SETP 0x00000070
/* [0x74]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_UCNT 0x00000074
/* [0x78]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000078
#endif
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 011b2c06
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Mon Jul 3 13:40:08 2017
-- Created : Mon Nov 27 13:37:56 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -337,34 +337,18 @@ begin
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.hwfr_memsize_i;
rddata_reg(9 downto 8) <= regs_i.hwfr_storage_type_i;
rddata_reg(31 downto 16) <= regs_i.hwfr_storage_sec_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
......@@ -374,6 +358,12 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.sdbfs_baddr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
sysc_tcr_enable_int <= wrdata_reg(31);
end if;
......@@ -400,27 +390,27 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
when "00111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tvr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
when "01000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.diag_info_ver_i;
rddata_reg(31 downto 16) <= regs_i.diag_info_id_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
when "01001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.diag_nw_rw_i;
rddata_reg(31 downto 16) <= regs_i.diag_nw_ro_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
when "01010" =>
if (wb_we_i = '1') then
regs_o.diag_cr_adr_load_o <= '1';
sysc_diag_cr_rw_int <= wrdata_reg(31);
......@@ -444,14 +434,14 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
when "01011" =>
if (wb_we_i = '1') then
regs_o.diag_dat_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.diag_dat_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
when "01100" =>
if (wb_we_i = '1') then
sysc_wdiag_ctrl_data_valid_int <= wrdata_reg(0);
end if;
......@@ -489,7 +479,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
when "01101" =>
if (wb_we_i = '1') then
sysc_wdiag_sstat_wr_mode_int <= wrdata_reg(0);
sysc_wdiag_sstat_servostate_int <= wrdata_reg(11 downto 8);
......@@ -525,7 +515,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
when "01110" =>
if (wb_we_i = '1') then
sysc_wdiag_pstat_link_int <= wrdata_reg(0);
sysc_wdiag_pstat_locked_int <= wrdata_reg(1);
......@@ -564,7 +554,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
when "01111" =>
if (wb_we_i = '1') then
sysc_wdiag_ptpstat_ptpstate_int <= wrdata_reg(7 downto 0);
end if;
......@@ -595,7 +585,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
when "10000" =>
if (wb_we_i = '1') then
sysc_wdiag_astat_aux_int <= wrdata_reg(7 downto 0);
end if;
......@@ -626,98 +616,98 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
when "10001" =>
if (wb_we_i = '1') then
sysc_wdiag_txfcnt_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_txfcnt_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
when "10010" =>
if (wb_we_i = '1') then
sysc_wdiag_rxfcnt_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_rxfcnt_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
when "10011" =>
if (wb_we_i = '1') then
sysc_wdiag_sec_msb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_sec_msb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
when "10100" =>
if (wb_we_i = '1') then
sysc_wdiag_sec_lsb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_sec_lsb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
when "10101" =>
if (wb_we_i = '1') then
sysc_wdiag_ns_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_ns_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10101" =>
when "10110" =>
if (wb_we_i = '1') then
sysc_wdiag_mu_msb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_mu_msb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
when "10111" =>
if (wb_we_i = '1') then
sysc_wdiag_mu_lsb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_mu_lsb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
when "11000" =>
if (wb_we_i = '1') then
sysc_wdiag_dms_msb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_dms_msb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11000" =>
when "11001" =>
if (wb_we_i = '1') then
sysc_wdiag_dms_lsb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_dms_lsb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11001" =>
when "11010" =>
if (wb_we_i = '1') then
sysc_wdiag_asym_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_asym_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11010" =>
when "11011" =>
if (wb_we_i = '1') then
sysc_wdiag_cko_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_cko_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11011" =>
when "11100" =>
if (wb_we_i = '1') then
sysc_wdiag_setp_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_setp_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11100" =>
when "11101" =>
if (wb_we_i = '1') then
sysc_wdiag_ucnt_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= sysc_wdiag_ucnt_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11101" =>
when "11110" =>
if (wb_we_i = '1') then
sysc_wdiag_temp_int <= wrdata_reg(31 downto 0);
end if;
......@@ -917,7 +907,10 @@ begin
-- Memory size
-- Storage type
-- Storage sector size
-- Board name
-- Base address
-- Timer Divider
-- Timer Enable
regs_o.tcr_enable_o <= sysc_tcr_enable_int;
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ 011b2c06
......@@ -267,6 +267,29 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Storage type";
prefix = "STORAGE_TYPE";
size = 2;
description = "Storage memory type (0 - Flash, 1 - I2C EEPROM, 2 - 1-Wire EEPROM)";
type = SLV;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Storage sector size";
prefix = "STORAGE_SEC";
size = 16;
description = "Storage sector size in KB";
type = SLV;
align = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......@@ -283,6 +306,20 @@ peripheral {
};
};
reg {
name = "Storage SDBFS info";
prefix = "SDBFS";
field {
name = "Base address";
prefix = "BADDR";
size = 32;
description = "Default base address in storage, where WRPC should write SDBFS image";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Timer Control Register";
prefix = "TCR";
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 011b2c06
......@@ -260,6 +260,8 @@ package wrcore_pkg is
component wrc_periph is
generic(
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 64;
g_flash_sdbfs_baddr : integer := 16#2e0000#;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_cntr_period : integer := 62500;
......@@ -376,6 +378,8 @@ package wrcore_pkg is
generic(
g_simulation : integer := 0;
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
g_phys_uart : boolean := true;
g_virtual_uart : boolean := true;
g_with_external_clock_input : boolean := true;
......@@ -517,6 +521,8 @@ package wrcore_pkg is
g_with_external_clock_input : boolean := true;
--
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
g_phys_uart : boolean := true;
g_virtual_uart : boolean := true;
g_aux_clks : integer := 0;
......
modules/wrc_core/xwr_core.vhd
View file @ 011b2c06
......@@ -77,6 +77,8 @@ entity xwr_core is
g_with_external_clock_input : boolean := true;
--
g_board_name : string := "NA ";
g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128)
g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128)
g_phys_uart : boolean := true;
g_virtual_uart : boolean := true;
g_aux_clks : integer := 0;
......@@ -274,6 +276,8 @@ begin
generic map(
g_simulation => g_simulation,
g_board_name => g_board_name,
g_flash_secsz_kb => g_flash_secsz_kb,
g_flash_sdbfs_baddr => g_flash_sdbfs_baddr,
g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart,
g_rx_buffer_size => g_ep_rxbuf_size,
......
sim/wrc_syscon_regs.vh
View file @ 011b2c06
......@@ -54,63 +54,70 @@
`define ADDR_SYSC_HWFR 7'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
`define SYSC_HWFR_STORAGE_TYPE_OFFSET 8
`define SYSC_HWFR_STORAGE_TYPE 32'h00000300
`define SYSC_HWFR_STORAGE_SEC_OFFSET 16
`define SYSC_HWFR_STORAGE_SEC 32'hffff0000
`define ADDR_SYSC_HWIR 7'h10
`define SYSC_HWIR_NAME_OFFSET 0
`define SYSC_HWIR_NAME 32'hffffffff
`define ADDR_SYSC_TCR 7'h14
`define ADDR_SYSC_SDBFS 7'h14
`define SYSC_SDBFS_BADDR_OFFSET 0
`define SYSC_SDBFS_BADDR 32'hffffffff
`define ADDR_SYSC_TCR 7'h18
`define SYSC_TCR_TDIV_OFFSET 0
`define SYSC_TCR_TDIV 32'h00000fff
`define SYSC_TCR_ENABLE_OFFSET 31
`define SYSC_TCR_ENABLE 32'h80000000
`define ADDR_SYSC_TVR 7'h18
`define ADDR_SYSC_DIAG_INFO 7'h1c
`define ADDR_SYSC_TVR 7'h1c
`define ADDR_SYSC_DIAG_INFO 7'h20
`define SYSC_DIAG_INFO_VER_OFFSET 0
`define SYSC_DIAG_INFO_VER 32'h0000ffff
`define SYSC_DIAG_INFO_ID_OFFSET 16
`define SYSC_DIAG_INFO_ID 32'hffff0000
`define ADDR_SYSC_DIAG_NW 7'h20
`define ADDR_SYSC_DIAG_NW 7'h24
`define SYSC_DIAG_NW_RW_OFFSET 0
`define SYSC_DIAG_NW_RW 32'h0000ffff
`define SYSC_DIAG_NW_RO_OFFSET 16
`define SYSC_DIAG_NW_RO 32'hffff0000
`define ADDR_SYSC_DIAG_CR 7'h24
`define ADDR_SYSC_DIAG_CR 7'h28
`define SYSC_DIAG_CR_ADR_OFFSET 0
`define SYSC_DIAG_CR_ADR 32'h0000ffff
`define SYSC_DIAG_CR_RW_OFFSET 31
`define SYSC_DIAG_CR_RW 32'h80000000
`define ADDR_SYSC_DIAG_DAT 7'h28
`define ADDR_SYSC_WDIAG_CTRL 7'h2c
`define ADDR_SYSC_DIAG_DAT 7'h2c
`define ADDR_SYSC_WDIAG_CTRL 7'h30
`define SYSC_WDIAG_CTRL_DATA_VALID_OFFSET 0
`define SYSC_WDIAG_CTRL_DATA_VALID 32'h00000001
`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT_OFFSET 8
`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT 32'h00000100
`define ADDR_SYSC_WDIAG_SSTAT 7'h30
`define ADDR_SYSC_WDIAG_SSTAT 7'h34
`define SYSC_WDIAG_SSTAT_WR_MODE_OFFSET 0
`define SYSC_WDIAG_SSTAT_WR_MODE 32'h00000001
`define SYSC_WDIAG_SSTAT_SERVOSTATE_OFFSET 8
`define SYSC_WDIAG_SSTAT_SERVOSTATE 32'h00000f00
`define ADDR_SYSC_WDIAG_PSTAT 7'h34
`define ADDR_SYSC_WDIAG_PSTAT 7'h38
`define SYSC_WDIAG_PSTAT_LINK_OFFSET 0
`define SYSC_WDIAG_PSTAT_LINK 32'h00000001
`define SYSC_WDIAG_PSTAT_LOCKED_OFFSET 1
`define SYSC_WDIAG_PSTAT_LOCKED 32'h00000002
`define ADDR_SYSC_WDIAG_PTPSTAT 7'h38
`define ADDR_SYSC_WDIAG_PTPSTAT 7'h3c
`define SYSC_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0
`define SYSC_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff
`define ADDR_SYSC_WDIAG_ASTAT 7'h3c
`define ADDR_SYSC_WDIAG_ASTAT 7'h40
`define SYSC_WDIAG_ASTAT_AUX_OFFSET 0
`define SYSC_WDIAG_ASTAT_AUX 32'h000000ff
`define ADDR_SYSC_WDIAG_TXFCNT 7'h40
`define ADDR_SYSC_WDIAG_RXFCNT 7'h44
`define ADDR_SYSC_WDIAG_SEC_MSB 7'h48
`define ADDR_SYSC_WDIAG_SEC_LSB 7'h4c
`define ADDR_SYSC_WDIAG_NS 7'h50
`define ADDR_SYSC_WDIAG_MU_MSB 7'h54
`define ADDR_SYSC_WDIAG_MU_LSB 7'h58
`define ADDR_SYSC_WDIAG_DMS_MSB 7'h5c
`define ADDR_SYSC_WDIAG_DMS_LSB 7'h60
`define ADDR_SYSC_WDIAG_ASYM 7'h64
`define ADDR_SYSC_WDIAG_CKO 7'h68
`define ADDR_SYSC_WDIAG_SETP 7'h6c
`define ADDR_SYSC_WDIAG_UCNT 7'h70
`define ADDR_SYSC_WDIAG_TEMP 7'h74
`define ADDR_SYSC_WDIAG_TXFCNT 7'h44
`define ADDR_SYSC_WDIAG_RXFCNT 7'h48
`define ADDR_SYSC_WDIAG_SEC_MSB 7'h4c
`define ADDR_SYSC_WDIAG_SEC_LSB 7'h50
`define ADDR_SYSC_WDIAG_NS 7'h54
`define ADDR_SYSC_WDIAG_MU_MSB 7'h58
`define ADDR_SYSC_WDIAG_MU_LSB 7'h5c
`define ADDR_SYSC_WDIAG_DMS_MSB 7'h60
`define ADDR_SYSC_WDIAG_DMS_LSB 7'h64
`define ADDR_SYSC_WDIAG_ASYM 7'h68
`define ADDR_SYSC_WDIAG_CKO 7'h6c
`define ADDR_SYSC_WDIAG_SETP 7'h70
`define ADDR_SYSC_WDIAG_UCNT 7'h74
`define ADDR_SYSC_WDIAG_TEMP 7'h78
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