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White Rabbit core collection
Commit 0407e284 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_streamers: added software controlled reset to the wishbone i/f

parent fa6e7288
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modules/wr_streamers/wr_streamers_wb.vhd
View file @ 0407e284
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modules/wr_streamers/wr_streamers_wb.wb
View file @ 0407e284
...@@ -77,6 +77,7 @@ peripheral { ...@@ -77,6 +77,7 @@ peripheral {
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
reg { reg {
name = "Statistics status and ctrl register"; name = "Statistics status and ctrl register";
prefix = "SSCR2"; prefix = "SSCR2";
...@@ -615,6 +616,7 @@ peripheral { ...@@ -615,6 +616,7 @@ peripheral {
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
reg { reg {
name = "Test value"; name = "Test value";
prefix = "DUMMY"; prefix = "DUMMY";
...@@ -627,4 +629,16 @@ peripheral { ...@@ -627,4 +629,16 @@ peripheral {
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
reg {
name = "Reset Register";
prefix = "RSTR";
field {
name = "Software reset streamers";
prefix = "RST_SW";
description = "Writing 1 triggers a full software reset of the streamers.";
type = MONOSTABLE;
};
};
}; };
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ 0407e284
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd -- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb -- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed Aug 16 22:45:12 2017 -- Created : Fri Oct 19 19:28:20 2018
-- Version : 0x00000001 -- Version : 0x00000001
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -101,6 +101,7 @@ package wr_streamers_wbgen2_pkg is ...@@ -101,6 +101,7 @@ package wr_streamers_wbgen2_pkg is
cfg_or_rx_fix_lat_o : std_logic; cfg_or_rx_fix_lat_o : std_logic;
dbg_ctrl_mux_o : std_logic; dbg_ctrl_mux_o : std_logic;
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0); dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
rstr_rst_sw_o : std_logic;
end record; end record;
constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := ( constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := (
...@@ -135,57 +136,83 @@ package wr_streamers_wbgen2_pkg is ...@@ -135,57 +136,83 @@ package wr_streamers_wbgen2_pkg is
cfg_or_rx_ftr_remote_o => '0', cfg_or_rx_ftr_remote_o => '0',
cfg_or_rx_fix_lat_o => '0', cfg_or_rx_fix_lat_o => '0',
dbg_ctrl_mux_o => '0', dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0') dbg_ctrl_start_byte_o => (others => '0'),
rstr_rst_sw_o => '0'
); );
function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector; function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component wr_streamers_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wr_streamers_in_registers;
regs_o : out t_wr_streamers_out_registers
);
end component;
end package; end package;
package body wr_streamers_wbgen2_pkg is package body wr_streamers_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is function f_x_to_zero (x:std_logic) return std_logic is
begin begin
if x = '1' then if x = '1' then
return '1'; return '1';
else else
return '0'; return '0';
end if; end if;
end function; end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0); variable tmp: std_logic_vector(x'length-1 downto 0);
begin begin
for i in 0 to x'length-1 loop for i in 0 to x'length-1 loop
if x(i) = '1' then if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '1'; tmp(i):= '0';
else else
tmp(i):= '0'; tmp(i):=x(i);
end if; end if;
end loop; end loop;
return tmp; return tmp;
end function; end function;
function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers is function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers is
variable tmp: t_wr_streamers_in_registers; variable tmp: t_wr_streamers_in_registers;
begin begin
tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i); tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i);
tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i); tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i);
tmp.sscr2_rst_ts_tai_lsb_i := f_x_to_zero(left.sscr2_rst_ts_tai_lsb_i) or f_x_to_zero(right.sscr2_rst_ts_tai_lsb_i); tmp.sscr2_rst_ts_tai_lsb_i := f_x_to_zero(left.sscr2_rst_ts_tai_lsb_i) or f_x_to_zero(right.sscr2_rst_ts_tai_lsb_i);
tmp.sscr3_rst_ts_tai_msb_i := f_x_to_zero(left.sscr3_rst_ts_tai_msb_i) or f_x_to_zero(right.sscr3_rst_ts_tai_msb_i); tmp.sscr3_rst_ts_tai_msb_i := f_x_to_zero(left.sscr3_rst_ts_tai_msb_i) or f_x_to_zero(right.sscr3_rst_ts_tai_msb_i);
tmp.rx_stat0_rx_latency_max_i := f_x_to_zero(left.rx_stat0_rx_latency_max_i) or f_x_to_zero(right.rx_stat0_rx_latency_max_i); tmp.rx_stat0_rx_latency_max_i := f_x_to_zero(left.rx_stat0_rx_latency_max_i) or f_x_to_zero(right.rx_stat0_rx_latency_max_i);
tmp.rx_stat1_rx_latency_min_i := f_x_to_zero(left.rx_stat1_rx_latency_min_i) or f_x_to_zero(right.rx_stat1_rx_latency_min_i); tmp.rx_stat1_rx_latency_min_i := f_x_to_zero(left.rx_stat1_rx_latency_min_i) or f_x_to_zero(right.rx_stat1_rx_latency_min_i);
tmp.tx_stat2_tx_sent_cnt_lsb_i := f_x_to_zero(left.tx_stat2_tx_sent_cnt_lsb_i) or f_x_to_zero(right.tx_stat2_tx_sent_cnt_lsb_i); tmp.tx_stat2_tx_sent_cnt_lsb_i := f_x_to_zero(left.tx_stat2_tx_sent_cnt_lsb_i) or f_x_to_zero(right.tx_stat2_tx_sent_cnt_lsb_i);
tmp.tx_stat3_tx_sent_cnt_msb_i := f_x_to_zero(left.tx_stat3_tx_sent_cnt_msb_i) or f_x_to_zero(right.tx_stat3_tx_sent_cnt_msb_i); tmp.tx_stat3_tx_sent_cnt_msb_i := f_x_to_zero(left.tx_stat3_tx_sent_cnt_msb_i) or f_x_to_zero(right.tx_stat3_tx_sent_cnt_msb_i);
tmp.rx_stat4_rx_rcvd_cnt_lsb_i := f_x_to_zero(left.rx_stat4_rx_rcvd_cnt_lsb_i) or f_x_to_zero(right.rx_stat4_rx_rcvd_cnt_lsb_i); tmp.rx_stat4_rx_rcvd_cnt_lsb_i := f_x_to_zero(left.rx_stat4_rx_rcvd_cnt_lsb_i) or f_x_to_zero(right.rx_stat4_rx_rcvd_cnt_lsb_i);
tmp.rx_stat5_rx_rcvd_cnt_msb_i := f_x_to_zero(left.rx_stat5_rx_rcvd_cnt_msb_i) or f_x_to_zero(right.rx_stat5_rx_rcvd_cnt_msb_i); tmp.rx_stat5_rx_rcvd_cnt_msb_i := f_x_to_zero(left.rx_stat5_rx_rcvd_cnt_msb_i) or f_x_to_zero(right.rx_stat5_rx_rcvd_cnt_msb_i);
tmp.rx_stat6_rx_loss_cnt_lsb_i := f_x_to_zero(left.rx_stat6_rx_loss_cnt_lsb_i) or f_x_to_zero(right.rx_stat6_rx_loss_cnt_lsb_i); tmp.rx_stat6_rx_loss_cnt_lsb_i := f_x_to_zero(left.rx_stat6_rx_loss_cnt_lsb_i) or f_x_to_zero(right.rx_stat6_rx_loss_cnt_lsb_i);
tmp.rx_stat7_rx_loss_cnt_msb_i := f_x_to_zero(left.rx_stat7_rx_loss_cnt_msb_i) or f_x_to_zero(right.rx_stat7_rx_loss_cnt_msb_i); tmp.rx_stat7_rx_loss_cnt_msb_i := f_x_to_zero(left.rx_stat7_rx_loss_cnt_msb_i) or f_x_to_zero(right.rx_stat7_rx_loss_cnt_msb_i);
tmp.rx_stat8_rx_lost_block_cnt_lsb_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_lsb_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_lsb_i); tmp.rx_stat8_rx_lost_block_cnt_lsb_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_lsb_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_lsb_i);
tmp.rx_stat9_rx_lost_block_cnt_msb_i := f_x_to_zero(left.rx_stat9_rx_lost_block_cnt_msb_i) or f_x_to_zero(right.rx_stat9_rx_lost_block_cnt_msb_i); tmp.rx_stat9_rx_lost_block_cnt_msb_i := f_x_to_zero(left.rx_stat9_rx_lost_block_cnt_msb_i) or f_x_to_zero(right.rx_stat9_rx_lost_block_cnt_msb_i);
tmp.rx_stat10_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat10_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat10_rx_latency_acc_lsb_i); tmp.rx_stat10_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat10_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat10_rx_latency_acc_lsb_i);
tmp.rx_stat11_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat11_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat11_rx_latency_acc_msb_i); tmp.rx_stat11_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat11_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat11_rx_latency_acc_msb_i);
tmp.rx_stat12_rx_latency_acc_cnt_lsb_i := f_x_to_zero(left.rx_stat12_rx_latency_acc_cnt_lsb_i) or f_x_to_zero(right.rx_stat12_rx_latency_acc_cnt_lsb_i); tmp.rx_stat12_rx_latency_acc_cnt_lsb_i := f_x_to_zero(left.rx_stat12_rx_latency_acc_cnt_lsb_i) or f_x_to_zero(right.rx_stat12_rx_latency_acc_cnt_lsb_i);
tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i); tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i);
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i); tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i); tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
return tmp; return tmp;
end function; end function;
end package body; end package body;
modules/wr_streamers/xwr_streamers.vhd
View file @ 0407e284
...@@ -488,4 +488,9 @@ begin ...@@ -488,4 +488,9 @@ begin
rx_streamer_cfg_i.filter_remote; rx_streamer_cfg_i.filter_remote;
rx_streamer_cfg.fixed_latency <= from_wb.rx_cfg5_fixed_latency_o when (from_wb.cfg_or_rx_fix_lat_o='1') else rx_streamer_cfg.fixed_latency <= from_wb.rx_cfg5_fixed_latency_o when (from_wb.cfg_or_rx_fix_lat_o='1') else
rx_streamer_cfg_i.fixed_latency; rx_streamer_cfg_i.fixed_latency;
rx_streamer_cfg.reset_sw <= from_wb.rstr_rst_sw_o;
tx_streamer_cfg.reset_sw <= from_wb.rstr_rst_sw_o;
end rtl; end rtl;
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