Commit 0618fbe4 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

wrcore: instantiate wrc_syscon directly, wrapper is not needed

parent 639129fb
......@@ -5,7 +5,6 @@ files = [ "xwr_core.vhd",
"wrc_periph.vhd",
"wrc_syscon_wb.vhd",
"wrc_syscon_pkg.vhd",
"xwr_syscon_wb.vhd",
"wrc_diags_wb.vhd",
"wrc_diags_pkg.vhd",
"xwrc_diags_wb.vhd"];
......
......@@ -397,21 +397,25 @@ begin
----------------------------------------
-- SYSCON
----------------------------------------
SYSCON : xwr_syscon_wb
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
slave_i => slave_i(0),
slave_o => slave_o(0),
regs_i => sysc_regs_i,
regs_o => sysc_regs_o
);
SYSCON : entity work.wrc_syscon_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i(0).adr(6 downto 2), -- shift address for word addressing
wb_dat_i => slave_i(0).dat,
wb_dat_o => slave_o(0).dat,
wb_cyc_i => slave_i(0).cyc,
wb_sel_i => slave_i(0).sel,
wb_stb_i => slave_i(0).stb,
wb_we_i => slave_i(0).we,
wb_ack_o => slave_o(0).ack,
wb_stall_o => slave_o(0).stall,
regs_i => sysc_regs_i,
regs_o => sysc_regs_o);
slave_o(0).err <= '0';
slave_o(0).rty <= '0';
slave_o(0).int <= '0';
--------------------------------------
-- UART
......
......@@ -142,23 +142,6 @@ package wrcore_pkg is
-----------------------------------------------------------------------------
-- PERIPHERIALS
-----------------------------------------------------------------------------
component xwr_syscon_wb
generic(
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end component;
component xwr_diags_wb is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
......
-------------------------------------------------------------------------------
-- Title : WhiteRabbit Syscon
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : xwr_syscon_wb.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN(BE-CO-HT), Elproma
-- Created : 2011-11-07
-- Last update: 2017-04-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wrapper for wrc_syscon_wb. Uses types instead of std_logic signals and
-- can use pipelined or classic wishbone.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2012 Elproma Elektronika
-- Copyright (c) 2012-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
entity xwr_syscon_wb is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end xwr_syscon_wb;
architecture syn of xwr_syscon_wb is
component wrc_syscon_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end component;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => slave_i.adr,
sl_dat_i => slave_i.dat,
sl_sel_i => slave_i.sel,
sl_cyc_i => slave_i.cyc,
sl_stb_i => slave_i.stb,
sl_we_i => slave_i.we,
sl_dat_o => slave_o.dat,
sl_ack_o => slave_o.ack,
sl_stall_o => slave_o.stall);
WRAPPED_SYSCON: wrc_syscon_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(4 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
regs_i => regs_i,
regs_o => regs_o);
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end syn;
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