Commit 0f1615da authored by Committed by Grzegorz Daniluk
wr_softpll_ng: 'reversed' mode for DDMTDs that does not require DDMTD counters in clk_in domain.
This may fix the WRs locking offsets issue & save a lot of FPGA resources. Signed-off-by: Grzegorz Daniluk <email@example.com>
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