Commit 0f1615da authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk

wr_softpll_ng: 'reversed' mode for DDMTDs that does not require DDMTD counters in clk_in domain.

This may fix the WRs locking offsets issue & save a lot of FPGA resources.
Signed-off-by: Grzegorz Daniluk's avatarGrzegorz Daniluk <grzegorz.daniluk@cern.ch>
parent 35b77aba
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT -- Company : CERN BE-Co-HT
-- Created : 2010-02-25 -- Created : 2010-02-25
-- Last update: 2012-07-24 -- Last update: 2013-04-24
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL '93 -- Standard : VHDL '93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -61,7 +61,10 @@ entity dmtd_with_deglitcher is ...@@ -61,7 +61,10 @@ entity dmtd_with_deglitcher is
-- Divides the inputs by 2 (effectively passing the clock through a flip flop) -- Divides the inputs by 2 (effectively passing the clock through a flip flop)
-- before it gets to the DMTD, effectively removing Place&Route warnings -- before it gets to the DMTD, effectively removing Place&Route warnings
-- (at the cost of detector bandwidth) -- (at the cost of detector bandwidth)
g_divide_input_by_2 : boolean := false g_divide_input_by_2 : boolean := false;
-- reversed mode: samples clk_dmtd with clk_in.
g_reverse : boolean := false
); );
port ( port (
-- resets for different clock domains -- resets for different clock domains
...@@ -132,8 +135,8 @@ architecture rtl of dmtd_with_deglitcher is ...@@ -132,8 +135,8 @@ architecture rtl of dmtd_with_deglitcher is
signal in_d0, in_d1 : std_logic; signal in_d0, in_d1 : std_logic;
signal s_one : std_logic; signal s_one : std_logic;
signal clk_in : std_logic; signal clk_in : std_logic;
signal clk_i_d0, clk_i_d1, clk_i_d2, clk_i_d3 : std_logic; signal clk_i_d0, clk_i_d1, clk_i_d2, clk_i_d3, clk_i_dx : std_logic;
attribute keep : string; attribute keep : string;
attribute keep of clk_in : signal is "true"; attribute keep of clk_in : signal is "true";
...@@ -179,32 +182,58 @@ begin -- rtl ...@@ -179,32 +182,58 @@ begin -- rtl
data_i => resync_done_dmtd, data_i => resync_done_dmtd,
synced_o => resync_done_o); synced_o => resync_done_o);
gen_straight : if(g_reverse = false) generate
gen_input_div2 : if(g_divide_input_by_2 = true) generate
p_divide_input_clock : process(clk_in_i, rst_n_sysclk_i) gen_input_div2 : if(g_divide_input_by_2 = true) generate
p_divide_input_clock : process(clk_in_i, rst_n_sysclk_i)
begin
if rst_n_sysclk_i = '0' then
clk_in <= '0';
elsif rising_edge(clk_in_i) then
clk_in <= not clk_in;
end if;
end process;
end generate gen_input_div2;
gen_input_straight : if(g_divide_input_by_2 = false) generate
clk_in <= clk_in_i;
end generate gen_input_straight;
p_the_dmtd_itself : process(clk_dmtd_i)
begin begin
if rst_n_sysclk_i = '0' then if rising_edge(clk_dmtd_i) then
clk_in <= '0'; clk_i_d0 <= clk_in;
elsif rising_edge(clk_in_i) then clk_i_d1 <= clk_i_d0;
clk_in <= not clk_in; clk_i_d2 <= clk_i_d1;
clk_i_d3 <= clk_i_d2;
end if; end if;
end process; end process;
end generate gen_input_div2;
gen_input_straight : if(g_divide_input_by_2 = false) generate end generate gen_straight;
clk_in <= clk_in_i;
end generate gen_input_straight;
p_the_dmtd_itself : process(clk_dmtd_i) gen_reverse : if(g_reverse = true) generate
begin
if rising_edge(clk_dmtd_i) then assert (not g_divide_input_by_2) report "dmtd_with_deglitcher: g_reverse implies g_divide_input_by_2 == false" severity failure;
clk_i_d0 <= clk_in;
clk_i_d1 <= clk_i_d0; p_the_dmtd_itself : process(clk_in_i)
clk_i_d2 <= clk_i_d1; begin
clk_i_d3 <= clk_i_d2; if rising_edge(clk_in_i) then
end if; clk_i_d0 <= clk_dmtd_i;
end process; clk_i_d1 <= clk_i_d0;
end if;
end process;
p_sync : process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
clk_i_dx <= clk_i_d1;
clk_i_d2 <= not clk_i_dx;
clk_i_d3 <= clk_i_d2;
end if;
end process;
end generate gen_reverse;
-- glitchproof DMTD output edge detection -- glitchproof DMTD output edge detection
p_deglitch : process (clk_dmtd_i) p_deglitch : process (clk_dmtd_i)
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2011-01-29 -- Created : 2011-01-29
-- Last update: 2012-07-23 -- Last update: 2013-03-20
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -199,7 +199,8 @@ architecture rtl of wr_softpll_ng is ...@@ -199,7 +199,8 @@ architecture rtl of wr_softpll_ng is
component dmtd_with_deglitcher component dmtd_with_deglitcher
generic ( generic (
g_counter_bits : natural; g_counter_bits : natural;
g_divide_input_by_2 : boolean); g_divide_input_by_2 : boolean;
g_reverse : boolean);
port ( port (
rst_n_dmtdclk_i : in std_logic; rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic; rst_n_sysclk_i : in std_logic;
...@@ -376,11 +377,6 @@ architecture rtl of wr_softpll_ng is ...@@ -376,11 +377,6 @@ architecture rtl of wr_softpll_ng is
signal dbg_seq_id : unsigned(15 downto 0); signal dbg_seq_id : unsigned(15 downto 0);
signal dbg_fifo_permit_write : std_logic; signal dbg_fifo_permit_write : std_logic;
-- Temporary vectors for DDMTD clock selection (straight/reversed)
signal dmtd_ref_clk_in, dmtd_ref_clk_dmtd : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal dmtd_fb_clk_in, dmtd_fb_clk_dmtd : std_logic_vector(g_num_outputs-1 downto 0);
signal bb_sync_en, bb_sync_done : std_logic; signal bb_sync_en, bb_sync_done : std_logic;
signal ext_ref_present : std_logic; signal ext_ref_present : std_logic;
signal fb_resync_out : std_logic_vector(g_num_outputs-1 downto 0); signal fb_resync_out : std_logic_vector(g_num_outputs-1 downto 0);
...@@ -484,22 +480,20 @@ begin -- rtl ...@@ -484,22 +480,20 @@ begin -- rtl
gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
dmtd_ref_clk_in(i) <= f_pick(g_reverse_dmtds, clk_dmtd_i, clk_ref_i(i));
dmtd_ref_clk_dmtd(i) <= f_pick(g_reverse_dmtds, clk_ref_i(i), clk_dmtd_i);
DMTD_REF : dmtd_with_deglitcher DMTD_REF : dmtd_with_deglitcher
generic map ( generic map (
g_counter_bits => g_tag_bits, g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2) g_divide_input_by_2 => g_divide_input_by_2,
g_reverse => g_reverse_dmtds)
port map ( port map (
rst_n_dmtdclk_i => rst_n_dmtdclk, rst_n_dmtdclk_i => rst_n_dmtdclk,
rst_n_sysclk_i => rst_n_i, rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => dmtd_ref_clk_dmtd(i), clk_dmtd_i => clk_dmtd_i,
clk_dmtd_en_i => '1', --clk_dmtd_en_ref(i), clk_dmtd_en_i => '1', --clk_dmtd_en_ref(i),
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
clk_in_i => dmtd_ref_clk_in(i), clk_in_i => clk_ref_i(i),
resync_done_o => regs_out.crr_in_i(i), resync_done_o => regs_out.crr_in_i(i),
resync_start_p_i => ref_resync_start_p(i), resync_start_p_i => ref_resync_start_p(i),
...@@ -518,21 +512,20 @@ begin -- rtl ...@@ -518,21 +512,20 @@ begin -- rtl
gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
dmtd_fb_clk_in(i) <= f_pick(g_reverse_dmtds, clk_dmtd_i, clk_fb_i(i));
dmtd_fb_clk_dmtd(i) <= f_pick(g_reverse_dmtds, clk_fb_i(i), clk_dmtd_i);
DMTD_FB : dmtd_with_deglitcher DMTD_FB : dmtd_with_deglitcher
generic map ( generic map (
g_counter_bits => g_tag_bits, g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2) g_divide_input_by_2 => g_divide_input_by_2,
g_reverse => g_reverse_dmtds)
port map ( port map (
rst_n_dmtdclk_i => rst_n_dmtdclk, rst_n_dmtdclk_i => rst_n_dmtdclk,
rst_n_sysclk_i => rst_n_i, rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => dmtd_fb_clk_dmtd(i),
clk_dmtd_i => clk_dmtd_i,
clk_dmtd_en_i => '1', clk_dmtd_en_i => '1',
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
clk_in_i => dmtd_fb_clk_in(i), clk_in_i => clk_fb_i(i),
resync_done_o => regs_out.crr_out_i(i), resync_done_o => regs_out.crr_out_i(i),
resync_start_p_i => fb_resync_start_p(i), resync_start_p_i => fb_resync_start_p(i),
......
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