Commit 115886be authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'greg-peter-clb' into proposed_master

parents cc28eacd a6256755
files = [
"wr_clbv2_pkg.vhd",
"xwrc_board_clbv2.vhd",
"wrc_board_clbv2.vhd",
]
modules = {
"local" : [
"../common",
]
}
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files = [
"wr_clbv3_pkg.vhd",
"xwrc_board_clbv3.vhd",
"wrc_board_clbv3.vhd",
]
modules = {
"local" : [
"../common",
]
}
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files = ["gtp_bitslide.vhd",
"gtp_phase_align.vhd",
"gtp_phase_align_virtex6.vhd",
"gtx_reset.vhd",
"whiterabbitgtx_wrapper_gtx.vhd",
# "whiterabbitgtp_wrapper.vhd",
"whiterabbitgtp_wrapper_tile.vhd",
"whiterabbit_gtxe2_channel_wrapper_gt.vhd",
"wr_gtp_phy_spartan6.vhd",
"wr_gtx_phy_virtex6.vhd",
"wr_gtx_phy_kintex7.vhd"];
files = [
"gtp_bitslide.vhd",
];
if (syn_device[0:4].upper()=="XC6S"): # Spartan6
files.extend(["spartan6/wr_gtp_phy_spartan6.vhd",
"spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd",
"spartan6/gtp_phase_align.vhd"])
elif (syn_device[0:4].upper()=="XC6V"): # Virtex6
files.extend(["virtex6/wr_gtx_phy_virtex6.vhd",
"virtex6/whiterabbitgtx_wrapper_gtx.vhd",
"virtex6/gtp_phase_align_virtex6.vhd",
"virtex6/gtx_reset.vhd"])
elif (syn_device[0:4].upper()=="XC7A"): # Family 7 GTP (Artix7)
files.extend(["family7-gtp/wr_gtp_phy_family7.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd" ]);
elif (syn_device[0:4].upper()=="XC7K" or # Family 7 GTX (Kintex7 and Virtex7 585, 2000, X485)
syn_device[0:7].upper()=="XC7V585" or
syn_device[0:8].upper()=="XC7V2000" or
syn_device[0:8].upper()=="XC7VX485"):
files.extend(["family7-gtx/wr_gtx_phy_family7.vhd",
"family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"]);
elif (syn_device[0:4].upper()=="XC7V"): # Family 7 GTH (other Virtex7 devices)
files.extend(["family7-gth/wr_gth_phy_family7.vhd",
"whiterabbit_gthe2_channel_wrapper_gt.vhd",
"whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd",
"whiterabbit_gthe2_channel_wrapper_sync_block.vhd" ]);
\ No newline at end of file
--////////////////////////////////////////////////////////////////////////////////
--// ____ ____
--// / /\/ /
--// /___/ \ / Vendor: Xilinx
--// \ \ \/ Version : 3.6
--// \ \ Application : 7 Series FPGAs Transceivers Wizard
--// / / Filename : whiterabbit_gthe2_channel_wrapper_sync_block.vhd
--// /___/ /\
--// \ \ / \
--// \___\/\___\
--//
--//
--
-- Description: Used on signals crossing from one clock domain to
-- another, this is a flip-flop pair, with both flops
-- placed together with RLOCs into the same slice. Thus
-- the routing delay between the two is minimum to safe-
-- guard against metastability issues.
--
--
-- Module whiterabbit_gthe2_channel_wrapper_sync_block
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity whiterabbit_gthe2_channel_wrapper_sync_block is
generic (
INITIALISE : bit_vector(5 downto 0) := "000000"
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
-- attribute dont_touch : string;
-- attribute dont_touch of whiterabbit_gthe2_channel_wrapper_sync_block : entity is "yes";
end whiterabbit_gthe2_channel_wrapper_sync_block;
architecture structural of whiterabbit_gthe2_channel_wrapper_sync_block is
-- Internal Signals
signal data_sync1 : std_logic;
signal data_sync2 : std_logic;
signal data_sync3 : std_logic;
signal data_sync4 : std_logic;
signal data_sync5 : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of data_sync_reg1 : label is "true";
attribute ASYNC_REG of data_sync_reg2 : label is "true";
attribute ASYNC_REG of data_sync_reg3 : label is "true";
attribute ASYNC_REG of data_sync_reg4 : label is "true";
attribute ASYNC_REG of data_sync_reg5 : label is "true";
attribute ASYNC_REG of data_sync_reg6 : label is "true";
-- These attributes will stop XST translating the desired flip-flops into an
-- SRL based shift register.
attribute shreg_extract : string;
attribute shreg_extract of data_sync_reg1 : label is "no";
attribute shreg_extract of data_sync_reg2 : label is "no";
attribute shreg_extract of data_sync_reg3 : label is "no";
attribute shreg_extract of data_sync_reg4 : label is "no";
attribute shreg_extract of data_sync_reg5 : label is "no";
attribute shreg_extract of data_sync_reg6 : label is "no";
begin
data_sync_reg1 : FD
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
D => data_in,
Q => data_sync1
);
data_sync_reg2 : FD
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
D => data_sync1,
Q => data_sync2
);
data_sync_reg3 : FD
generic map (
INIT => INITIALISE(2)
)
port map (
C => clk,
D => data_sync2,
Q => data_sync3
);
data_sync_reg4 : FD
generic map (
INIT => INITIALISE(3)
)
port map (
C => clk,
D => data_sync3,
Q => data_sync4
);
data_sync_reg5 : FD
generic map (
INIT => INITIALISE(4)
)
port map (
C => clk,
D => data_sync4,
Q => data_sync5
);
data_sync_reg6 : FD
generic map (
INIT => INITIALISE(5)
)
port map (
C => clk,
D => data_sync5,
Q => data_out
);
end structural;
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......@@ -2,7 +2,7 @@
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtx_phy_kintex7.vhd
-- File : wr_gtx_phy_family7.vhd
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
......@@ -54,7 +54,7 @@ library work;
--use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtx_phy_kintex7 is
entity wr_gtx_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
......@@ -114,9 +114,9 @@ entity wr_gtx_phy_kintex7 is
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end wr_gtx_phy_kintex7;
end wr_gtx_phy_family7;
architecture rtl of wr_gtx_phy_kintex7 is
architecture rtl of wr_gtx_phy_family7 is
component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT is
generic
......
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target = "xilinx"
action = "synthesis"
syn_device = "xc7k160t"
syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv2_wr_ref_top"
syn_project = "clbv2_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/clbv2_ref_design/"}
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target = "xilinx"
action = "synthesis"
syn_device = "xc7a200t"
syn_grade = "-2"
syn_package = "fbg484"
syn_top = "clbv3_wr_ref_top"
syn_project = "clbv3_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/clbv3_ref_design/"}
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