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White Rabbit core collection
Commit 1304e31d authored by Maciej Lipinski's avatar Maciej Lipinski
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[streamers] update simulations so they work with updated streamers and LM32 binaries

parent f267c217
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Showing with 17 additions and 1015 deletions
testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
View file @ 1304e31d
......@@ -95,8 +95,11 @@ module main;
initial begin
// wait until both SPECs see the Ethernet link. Otherwise the packet we're going
// to send might end up in void...
$display("Start very looooong wait until link is OK (over 600us)");
#520us
wait(link_up_a == 1'b1 && link_up_b == 1'b1);
#10us
$display("Stop very looooong wait until link is OK");
forever begin // send a pulse every 30 us;
pulse_in = 1;
#1us;
......
testbench/wr_streamers/streamers-on-spec_trigger-distribution/run.do
View file @ 1304e31d
......@@ -4,6 +4,6 @@ set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 400us
run 40000us
wave zoomfull
radix -hex
testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave.do
View file @ 1304e31d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/link_up_a
add wave -noupdate /main/link_up_b
add wave -noupdate -divider {SPEC A-common}
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/clk_ref_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/clk_sys_i
......@@ -55,7 +57,7 @@ add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/trig_valid_
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/trig_ready_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/pulse_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {98492029160 fs} 0}
WaveRestoreCursors {{Cursor 1} {593239379560 fs} 1} {{Cursor 2} {538394383110 fs} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 152
configure wave -justifyvalue left
......@@ -70,4 +72,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {210 us}
WaveRestoreZoom {0 fs} {839137496540 fs}
testbench/wr_streamers/streamers-only_basic-transfer/wave.do
View file @ 1304e31d
......@@ -3,12 +3,12 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate /main/U_TX_Streamer/clk_sys_i
add wave -noupdate /main/U_TX_Streamer/rst_n_i
add wave -noupdate -divider {TX streamer - User side}
add wave -noupdate /main/U_TX_Streamer/tx_flush_i
add wave -noupdate /main/U_TX_Streamer/tx_last_i
add wave -noupdate /main/U_TX_Streamer/tx_data_i
add wave -noupdate /main/U_TX_Streamer/tx_reset_seq_i
add wave -noupdate /main/U_TX_Streamer/tx_valid_i
add wave -noupdate /main/U_TX_Streamer/tx_dreq_o
add wave -noupdate /main/U_TX_Streamer/tx_last_p1_i
add wave -noupdate /main/U_TX_Streamer/tx_flush_p1_i
add wave -noupdate -divider Wishbone
add wave -noupdate /main/mac/g_data_width
add wave -noupdate /main/mac/g_addr_width
......@@ -24,14 +24,14 @@ add wave -noupdate /main/mac/cyc
add wave -noupdate /main/mac/stb
add wave -noupdate /main/mac/we
add wave -noupdate -divider {RX streamer - user side}
add wave -noupdate /main/U_RX_Streamer/rx_first_o
add wave -noupdate /main/U_RX_Streamer/rx_last_o
add wave -noupdate /main/U_RX_Streamer/rx_data_o
add wave -noupdate /main/U_RX_Streamer/rx_valid_o
add wave -noupdate /main/U_RX_Streamer/rx_dreq_i
add wave -noupdate /main/U_RX_Streamer/rx_lost_o
add wave -noupdate /main/U_RX_Streamer/rx_latency_o
add wave -noupdate /main/U_RX_Streamer/rx_latency_valid_o
add wave -noupdate /main/U_RX_Streamer/rx_first_p1_o
add wave -noupdate /main/U_RX_Streamer/rx_last_p1_o
add wave -noupdate /main/U_RX_Streamer/rx_lost_p1_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1370 ns} 0}
configure wave -namecolwidth 150
......
top/spec_1_1/wr_streamers_demo/spec_top.vhd
View file @ 1304e31d
......@@ -505,7 +505,7 @@ begin
U_The_WR_Core : xwr_core
generic map (
g_simulation => 0,
g_simulation => g_simulation,
g_with_external_clock_input => true,
--
g_phys_uart => true,
......@@ -514,7 +514,7 @@ begin
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => true,
g_pcs_16bit => false,
g_dpram_initf => "wrc-simulation.ram",
g_dpram_initf => "../../../bin/wrpc/wrc_phy8_sim.bram",
-- g_aux_sdb => c_etherbone_sdb, --ML
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
......@@ -762,10 +762,7 @@ begin
generic map (
-- data width must be identical as in the TX streamer - otherwise, we'll be receiving
-- rubbish
g_data_width => 80,
-- we don't care where our triggers come from. Just blindly accept them all
-- without checking source addresses.
g_filter_remote_mac => false)
g_data_width => 80)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n,
......
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