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White Rabbit core collection
Commit 13169b65 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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cute_wr: reorganize board wrapper to match other board wrappers

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board/cute/cute_reset_gen.vhd deleted 100644 → 0
View file @ 7be63043
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cute_reset_gen is
port (
clk_sys_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end cute_reset_gen;
architecture behavioral of cute_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal powerup_n : std_logic := '0';
signal button_synced_n : std_logic;
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component;
begin -- behavioral
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n;
end behavioral;
board/cute/wr_cute_pkg.vhd
View file @ 13169b65
......@@ -46,7 +46,7 @@ use work.streamers_pkg.all;
package wr_cute_pkg is
component xwrc_board_cute is
generic (
generic(
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 0;
......@@ -60,89 +60,106 @@ package wr_cute_pkg is
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
-- cute special
g_sfp0_enable : boolean:= true;
g_sfp1_enable : boolean:= false;
g_multiboot_enable : boolean:= false);
-- CUTE special
g_cute_version : string := "2.2";
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false);
port (
rst_n_i : in std_logic;
clk_20m_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
clk_sfp0_i : in std_logic :='0';
clk_sfp1_i : in std_logic :='0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic;
sfp0_rxn_i : in std_logic;
sfp0_det_i : in std_logic;
sfp0_scl_i : in std_logic;
sfp0_scl_o : out std_logic;
sfp0_sda_i : in std_logic;
sfp0_sda_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic;
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic;
sfp0_refclk_sel_i : in std_logic_vector(2 downto 0):="110";
sfp0_rx_rbclk_o : out std_logic;
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic;
sfp1_rxn_i : in std_logic;
sfp1_det_i : in std_logic;
sfp1_scl_i : in std_logic;
sfp1_scl_o : out std_logic;
sfp1_sda_i : in std_logic;
sfp1_sda_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic;
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic;
sfp1_refclk_sel_i : in std_logic_vector(2 downto 0):="110";
sfp1_rx_rbclk_o : out std_logic;
eeprom_sda_i : in std_logic := '1';
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic := '1';
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp0_p_i : in std_logic :='0';
clk_125m_gtp0_n_i : in std_logic :='0';
clk_125m_gtp1_p_i : in std_logic :='0';
clk_125m_gtp1_n_i : in std_logic :='0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
plldac_clr_n_o : out std_logic;
plldac_load_n_o : out std_logic;
plldac_sync_n_o : out std_logic;
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic := '0';
sfp0_rxn_i : in std_logic := '0';
sfp0_det_i : in std_logic := '0';
sfp0_sda_i : in std_logic := '1';
sfp0_sda_o : out std_logic;
sfp0_scl_i : in std_logic := '1';
sfp0_scl_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic := '0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic := '0';
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic := '0';
sfp1_rxn_i : in std_logic := '0';
sfp1_det_i : in std_logic := '0';
sfp1_sda_i : in std_logic := '1';
sfp1_sda_o : out std_logic;
sfp1_scl_i : in std_logic := '1';
sfp1_scl_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
......@@ -150,8 +167,8 @@ package wr_cute_pkg is
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_valid_o : out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
......@@ -159,19 +176,20 @@ package wr_cute_pkg is
link_ok_o : out std_logic);
end component xwrc_board_cute;
constant c_xwb_tcpip_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000001103", -- thu
device_id => x"c0413599",
version => x"00000001",
date => x"20160424",
name => "wr-tcp-ip-stack ")));
constant c_xwb_tcpip_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000001103", -- thu
device_id => x"c0413599",
version => x"00000001",
date => x"20160424",
name => "wr-tcp-ip-stack ")));
end wr_cute_pkg;
board/cute/xwrc_board_cute.vhd
View file @ 13169b65
......@@ -4,10 +4,8 @@
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_cute.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Company : Tsinghua Univ. (DEP)
-- Created : 2018-07-14
-- Last update: 2018-07-14
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>, Greg Daniluk <grzegorz.daniluk@cern.ch>
-- Company : Tsinghua Univ. (DEP), CERN
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -77,77 +75,85 @@ entity xwrc_board_cute is
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
---------------------------------------------------------------------------
-- cute special
g_sfp0_enable : boolean:= true;
g_sfp1_enable : boolean:= false;
g_multiboot_enable : boolean:= false
---------------------------------------------------------------------------
g_cute_version : string := "2.2";
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
rst_n_i : in std_logic;
-- Clock input, used to derive the DDMTD clock
clk_20m_i : in std_logic;
-- 62.5m dmtd clock, from pll drived by clk_20m_vcxo
clk_dmtd_i : in std_logic;
-- 62.5m system clock, from pll drived by clk_125m_pllref
clk_sys_i : in std_logic;
-- 125m reference clock, from pll drived by clk_125m_pllref
clk_ref_i : in std_logic;
-- Dedicated clock for the Xilinx GTP transceiver.
clk_sfp0_i : in std_logic :='0';
clk_sfp1_i : in std_logic :='0';
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp0_p_i : in std_logic :='0';
clk_125m_gtp0_n_i : in std_logic :='0';
clk_125m_gtp1_p_i : in std_logic :='0';
clk_125m_gtp1_n_i : in std_logic :='0';
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
-- SPI interface to DACs
---------------------------------------------------------------------------
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
plldac_clr_n_o : out std_logic;
plldac_load_n_o : out std_logic;
plldac_sync_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic;
sfp0_rxn_i : in std_logic;
sfp0_rxp_i : in std_logic := '0';
sfp0_rxn_i : in std_logic := '0';
sfp0_det_i : in std_logic := '1';
sfp0_sda_i : in std_logic;
sfp0_sda_i : in std_logic := '1';
sfp0_sda_o : out std_logic;
sfp0_scl_i : in std_logic;
sfp0_scl_i : in std_logic := '1';
sfp0_scl_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic := '0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic := '0';
sfp0_refclk_sel_i : in std_logic_vector(2 downto 0);
sfp0_rx_rbclk_o : out std_logic;
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic;
sfp1_rxn_i : in std_logic;
sfp1_rxp_i : in std_logic := '0';
sfp1_rxn_i : in std_logic := '0';
sfp1_det_i : in std_logic := '1';
sfp1_sda_i : in std_logic;
sfp1_sda_i : in std_logic := '1';
sfp1_sda_o : out std_logic;
sfp1_scl_i : in std_logic;
sfp1_scl_i : in std_logic := '1';
sfp1_scl_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic := '0';
sfp1_refclk_sel_i : in std_logic_vector(2 downto 0);
sfp1_rx_rbclk_o : out std_logic;
---------------------------------------------------------------------------
-- I2C EEPROM
......@@ -194,6 +200,21 @@ entity xwrc_board_cute is
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
......@@ -259,12 +280,64 @@ entity xwrc_board_cute is
end entity xwrc_board_cute;
architecture struct of xwrc_board_cute is
------------------------------------------------------------------------------
-- components declaration
------------------------------------------------------------------------------
component cute_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_ldac_n_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_sync_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component cute_serial_dac_arb;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- IBUFDS
signal clk_125m_pllref_buf : std_logic;
-- PLLs, clocks
signal clk_125m_gtp_p : std_logic;
signal clk_125m_gtp_n : std_logic;
signal clk_pll_62m5 : std_logic;
signal clk_pll_125m : std_logic;
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DAC ARB
signal dac_hpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_load_p1 : std_logic;
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal dac_val1_data : std_logic_vector(15 downto 0);
signal dac_val2_data : std_logic_vector(15 downto 0);
signal dac_val1_load : std_logic;
signal dac_val2_load : std_logic;
-- OneWire
signal onewire_in : std_logic_vector(1 downto 0);
signal onewire_en : std_logic_vector(1 downto 0);
......@@ -279,11 +352,19 @@ architecture struct of xwrc_board_cute is
signal ext_ref_mul_stopped : std_logic;
signal ext_ref_rst : std_logic;
signal sfp_det_i : std_logic;
signal sfp_scl_i : std_logic;
signal sfp_scl_o : std_logic;
signal sfp_sda_i : std_logic;
signal sfp_sda_o : std_logic;
-- CUTE-WR specific stuff
signal sfp_txp_out : std_logic;
signal sfp_txn_out : std_logic;
signal sfp_rxp_in : std_logic;
signal sfp_rxn_in : std_logic;
signal sfp_det_in : std_logic;
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
signal sfp_tx_fault_in : std_logic;
signal sfp_tx_disable_out : std_logic;
signal sfp_los_in : std_logic;
signal tm_time_valid : std_logic;
......@@ -297,6 +378,176 @@ architecture struct of xwrc_board_cute is
begin -- architecture struct
-----------------------------------------------------------------------------
-- Platform-dependent part (PHY, PLLs, buffers, etc)
-----------------------------------------------------------------------------
cmp_ibufgds_pllref : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref_buf,
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_gtp_enable_ch0 => 0,
g_gtp_enable_ch1 => 1,
g_phy_refclk_sel => g_phy_refclk_sel,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_i => clk_125m_pllref_buf,
clk_125m_gtp_p_i => clk_125m_gtp_p,
clk_125m_gtp_n_i => clk_125m_gtp_n,
sfp_txn_o => sfp_txn_out,
sfp_txp_o => sfp_txp_out,
sfp_rxn_i => sfp_rxn_in,
sfp_rxp_i => sfp_rxp_in,
sfp_tx_fault_i => sfp_tx_fault_in,
sfp_los_i => sfp_los_in,
sfp_tx_disable_o => sfp_tx_disable_out,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_62m5_dmtd_o => clk_pll_dmtd,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
phy8_o => phy8_to_wrc,
phy8_i => phy8_from_wrc,
ext_ref_mul_o => ext_ref_mul,
ext_ref_mul_locked_o => ext_ref_mul_locked,
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_125m_o <= clk_pll_125m;
-----------------------------------------------------------------------------
-- SFP0/1 selection
-----------------------------------------------------------------------------
GEN_GTP0: if g_sfp0_enable = 1 generate
clk_125m_gtp_p <= clk_125m_gtp0_p_i;
clk_125m_gtp_n <= clk_125m_gtp0_n_i;
sfp0_txp_o <= sfp_txp_out;
sfp0_txn_o <= sfp_txn_out;
sfp0_sda_o <= sfp_sda_out;
sfp0_scl_o <= sfp_scl_out;
sfp0_tx_disable_o <= sfp_tx_disable_out;
sfp_rxp_in <= sfp0_rxp_i;
sfp_rxn_in <= sfp0_rxn_i;
sfp_det_in <= sfp0_det_i;
sfp_sda_in <= sfp0_sda_i;
sfp_scl_in <= sfp0_scl_i;
sfp_tx_fault_in <= sfp0_tx_fault_i;
sfp_los_in <= sfp0_los_i;
end generate;
GEN_GTP1: if g_sfp1_enable = 1 generate
clk_125m_gtp_p <= clk_125m_gtp1_p_i;
clk_125m_gtp_n <= clk_125m_gtp1_n_i;
sfp1_txp_o <= sfp_txp_out;
sfp1_txn_o <= sfp_txn_out;
sfp1_sda_o <= sfp_sda_out;
sfp1_scl_o <= sfp_scl_out;
sfp1_tx_disable_o <= sfp_tx_disable_out;
sfp_rxp_in <= sfp1_rxp_i;
sfp_rxn_in <= sfp1_rxn_i;
sfp_det_in <= sfp1_det_i;
sfp_sda_in <= sfp1_sda_i;
sfp_scl_in <= sfp1_scl_i;
sfp_tx_fault_in <= sfp1_tx_fault_i;
sfp_los_in <= sfp1_los_i;
end generate;
sfp0_rate_select_o <= '1';
sfp1_rate_select_o <= '1';
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
cmp_rstlogic_reset : gc_reset
generic map (
g_clocks => 2, -- 62.5MHz, 125MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map (
free_clk_i => clk_125m_pllref_buf,
locked_i => rstlogic_arst_n,
clks_i => rstlogic_clk_in,
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_125m_n_o <= rstlogic_rst_out(1);
-----------------------------------------------------------------------------
-- Double-channel SPI DAC
-----------------------------------------------------------------------------
GEN_DAC_DEFAULT: if g_cute_version /= "2.1" generate
dac_val1_data <= dac_dpll_data;
dac_val1_load <= dac_dpll_load_p1;
dac_val2_data <= dac_hpll_data;
dac_val2_load <= dac_hpll_load_p1;
end generate;
GEN_DAC_CUTE_2_1: if g_cute_version = "2.1" generate
-- Cute 2.1 had hpll and dpll DACs swapped
dac_val1_data <= dac_hpll_data;
dac_val1_load <= dac_hpll_load_p1;
dac_val2_data <= dac_dpll_data;
dac_val2_load <= dac_dpll_load_p1;
end generate;
cmp_dac_arb: cute_serial_dac_arb
generic map (
g_invert_sclk => FALSE,
g_num_extra_bits => 8)
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
val1_i => dac_val1_data,
load1_i => dac_val1_load,
val2_i => dac_val2_data,
load2_i => dac_val2_load,
dac_sync_n_o => plldac_sync_n_o,
dac_ldac_n_o => plldac_load_n_o,
dac_clr_n_o => plldac_clr_n_o,
dac_sclk_o => plldac_sclk_o,
dac_din_o => plldac_din_o);
-----------------------------------------------------------------------------
-- The WR PTP core with optional fabric interface attached
-----------------------------------------------------------------------------
......@@ -331,32 +582,32 @@ begin -- architecture struct
g_fabric_iface => g_fabric_iface
)
port map (
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
clk_ref_i => clk_ref_i,
clk_sys_i => clk_pll_62m5,
clk_dmtd_i => clk_pll_dmtd,
clk_ref_i => clk_pll_125m,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => ext_ref_mul_stopped,
clk_ext_rst_o => ext_ref_rst,
pps_ext_i => pps_ext_i,
rst_n_i => rst_n_i,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o,
dac_dpll_load_p1_o => dac_dpll_load_p1_o,
dac_dpll_data_o => dac_dpll_data_o,
rst_n_i => rst_62m5_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy8_o => phy8_from_wrc,
phy8_i => phy8_to_wrc,
scl_o => eeprom_scl_o,
scl_i => eeprom_scl_i,
sda_o => eeprom_sda_o,
sda_i => eeprom_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_det_in,
spi_sclk_o => flash_sclk_o,
spi_ncs_o => flash_ncs_o,
spi_mosi_o => flash_mosi_o,
......@@ -374,6 +625,18 @@ begin -- architecture struct
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
wb_eth_master_o => wb_eth_master_o,
wb_eth_master_i => wb_eth_master_i,
aux_diag_i => aux_diag_i,
......@@ -405,150 +668,10 @@ begin -- architecture struct
tm_time_valid_o <= tm_time_valid;
pps_valid_o <= tm_time_valid;
sfp0_rate_select_o <= '1';
sfp1_rate_select_o <= '1';
onewire_oen_o <= onewire_en(0);
onewire_in(0) <= onewire_i;
onewire_in(1) <= '1';
U_WRPC_SFP0: if (g_sfp0_enable = true) generate
phy8_to_wrc.ref_clk <= clk_ref_i;
phy8_to_wrc.sfp_tx_fault <= sfp0_tx_fault_i;
phy8_to_wrc.sfp_los <= sfp0_los_i;
sfp0_tx_disable_o <= phy8_from_wrc.sfp_tx_disable;
sfp_det_i <= sfp0_det_i;
sfp_scl_i <= sfp0_scl_i;
sfp0_scl_o <= sfp_scl_o;
sfp_sda_i <= sfp0_sda_i;
sfp0_sda_o <= sfp_sda_o;
sfp0_rx_rbclk_o <= phy8_to_wrc.rx_clk;
u_gtp0 : wr_gtp_phy_spartan6
generic map (
g_enable_ch0 => 0,
g_enable_ch1 => 1,
g_simulation => g_simulation)
port map (
gtp1_clk_i => clk_sfp0_i,
ch1_ref_clk_i => clk_ref_i,
ch1_tx_data_i => phy8_from_wrc.tx_data,
ch1_tx_k_i => phy8_from_wrc.tx_k(0),
ch1_tx_disparity_o => phy8_to_wrc.tx_disparity,
ch1_tx_enc_err_o => phy8_to_wrc.tx_enc_err,
ch1_rx_rbclk_o => phy8_to_wrc.rx_clk,
ch1_rx_data_o => phy8_to_wrc.rx_data,
ch1_rx_k_o => phy8_to_wrc.rx_k(0),
ch1_rx_enc_err_o => phy8_to_wrc.rx_enc_err,
ch1_rx_bitslide_o => phy8_to_wrc.rx_bitslide,
ch1_rst_i => phy8_from_wrc.rst,
ch1_loopen_i => phy8_from_wrc.loopen,
ch1_loopen_vec_i => phy8_from_wrc.loopen_vec,
ch1_tx_prbs_sel_i => phy8_from_wrc.tx_prbs_sel,
ch1_rdy_o => phy8_to_wrc.rdy,
pad_txn1_o => sfp0_txn_o,
pad_txp1_o => sfp0_txp_o,
pad_rxn1_i => sfp0_rxn_i,
pad_rxp1_i => sfp0_rxp_i,
gtp0_clk_i => '0',
ch0_ref_clk_i => clk_ref_i,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_data_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch0_loopen_vec_i => (others=>'0'),
ch0_tx_prbs_sel_i => (others=>'0'),
ch0_rdy_o => open,
ch0_ref_sel_pll => "100",
ch1_ref_sel_pll => sfp0_refclk_sel_i,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0'
);
end generate;
U_WRPC_SFP1: if (g_sfp1_enable = true) generate
phy8_to_wrc.ref_clk <= clk_ref_i;
phy8_to_wrc.sfp_tx_fault <= sfp1_tx_fault_i;
phy8_to_wrc.sfp_los <= sfp1_los_i;
sfp0_tx_disable_o <= phy8_from_wrc.sfp_tx_disable;
sfp_det_i <= sfp1_det_i;
sfp_scl_i <= sfp1_scl_i;
sfp1_scl_o <= sfp_scl_o;
sfp_sda_i <= sfp1_sda_i;
sfp1_sda_o <= sfp_sda_o;
sfp1_rx_rbclk_o <= phy8_to_wrc.rx_clk;
u_gtp1 : wr_gtp_phy_spartan6
generic map (
g_enable_ch0 => 0,
g_enable_ch1 => 1,
g_simulation => g_simulation)
port map (
gtp1_clk_i => clk_sfp1_i,
ch1_ref_clk_i => clk_ref_i,
ch1_tx_data_i => phy8_from_wrc.tx_data,
ch1_tx_k_i => phy8_from_wrc.tx_k(0),
ch1_tx_disparity_o => phy8_to_wrc.tx_disparity,
ch1_tx_enc_err_o => phy8_to_wrc.tx_enc_err,
ch1_rx_rbclk_o => phy8_to_wrc.rx_clk,
ch1_rx_data_o => phy8_to_wrc.rx_data,
ch1_rx_k_o => phy8_to_wrc.rx_k(0),
ch1_rx_enc_err_o => phy8_to_wrc.rx_enc_err,
ch1_rx_bitslide_o => phy8_to_wrc.rx_bitslide,
ch1_rst_i => phy8_from_wrc.rst,
ch1_loopen_i => phy8_from_wrc.loopen,
ch1_loopen_vec_i => phy8_from_wrc.loopen_vec,
ch1_tx_prbs_sel_i => phy8_from_wrc.tx_prbs_sel,
ch1_rdy_o => phy8_to_wrc.rdy,
pad_txn1_o => sfp1_txn_o,
pad_txp1_o => sfp1_txp_o,
pad_rxn1_i => sfp1_rxn_i,
pad_rxp1_i => sfp1_rxp_i,
gtp0_clk_i => '0',
ch0_ref_clk_i => clk_ref_i,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_data_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch0_loopen_vec_i => (others=>'0'),
ch0_tx_prbs_sel_i => (others=>'0'),
ch0_rdy_o => open,
ch0_ref_sel_pll => "100",
ch1_ref_sel_pll => sfp1_refclk_sel_i,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0'
);
end generate;
U_WRPC_MULTIBOOT: if (g_multiboot_enable = true) generate
multiboot_slave_in <= aux_master_out;
......@@ -557,19 +680,19 @@ U_WRPC_MULTIBOOT: if (g_multiboot_enable = true) generate
cmp_clock_crossing: xwb_clock_crossing
port map (
slave_clk_i => clk_sys_i,
slave_rst_n_i => rst_n_i,
slave_clk_i => clk_pll_62m5,
slave_rst_n_i => rst_62m5_n,
slave_i => multiboot_slave_in,
slave_o => multiboot_slave_out,
master_clk_i => clk_20m_i,
master_rst_n_i => rst_n_i,
master_clk_i => clk_20m_vcxo_i,
master_rst_n_i => rst_62m5_n,
master_i => multiboot_wb_in,
master_o => multiboot_wb_out);
u_multiboot: xwb_xil_multiboot
port map (
clk_i => clk_20m_i,
rst_n_i => rst_n_i,
clk_i => clk_20m_vcxo_i,
rst_n_i => rst_62m5_n,
wbs_i => multiboot_wb_out,
wbs_o => multiboot_wb_in,
spi_cs_n_o => open,
......
syn/cute_ref_design/Makefile
View file @ 13169b65
......@@ -59,13 +59,14 @@ endif
CWD := $(shell pwd)
FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
FILES := ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
../../top/cute_ref_design/cute_wr_ref_top.ucf \
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd \
../../modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
......@@ -97,7 +98,7 @@ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../board/cute/wr_cute_pkg.vhd \
../../modules/wr_softpll_ng/spll_aligner.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
......@@ -117,9 +118,9 @@ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../modules/wr_eca/eca_channel.vhd \
../../modules/wr_eca/wr_eca.vhd \
run.tcl \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../modules/wr_eca/eca_offset.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../modules/wr_endpoint/ep_crc32_pkg.vhd \
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
......@@ -130,9 +131,9 @@ run.tcl \
../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd \
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../modules/wr_dacs/cute_serial_dac_arb.vhd \
../../modules/wr_dacs/spec_serial_dac_arb.vhd \
../../modules/wr_streamers/xrx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
../../modules/wr_eca/eca_auto.vhd \
......@@ -141,12 +142,13 @@ run.tcl \
../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../modules/wr_tlu/tlu_pkg.vhd \
../../board/cute/wr_cute_pkg.vhd \
../../modules/wr_dacs/cute_serial_dac.vhd \
../../modules/wr_eca/eca_ac_wbm_auto.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../board/cute/cute_reset_gen.vhd \
../../board/cute/xwrc_board_cute.vhd \
../../modules/wr_eca/eca_tlu.vhd \
cute_wr_ref.xise \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
../../modules/wr_mini_nic/minic_wb_slave.vhd \
......@@ -168,9 +170,11 @@ run.tcl \
../../modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
run.tcl \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../modules/wr_eca/eca_scubus_channel.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
../../board/cute/xwrc_board_cute.vhd \
../../modules/timing/pulse_stamper.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../modules/wr_streamers/streamers_pkg.vhd \
......@@ -188,7 +192,6 @@ run.tcl \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../modules/wr_si57x_interface/si570_if_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
../../modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd \
../../modules/wrc_core/wrcore_pkg.vhd \
......@@ -201,13 +204,14 @@ run.tcl \
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
../../modules/wr_tlu/tlu.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../top/cute_ref_design/cute_wr_ref_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../modules/wr_eca/eca_piso_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
../../modules/wrc_core/wrc_syscon_wb.vhd \
../../modules/wrc_core/xwr_core.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../top/cute_ref_design/cute_wr_ref_top.ucf \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../modules/wr_eca/eca_rmw.vhd \
../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
......@@ -223,12 +227,12 @@ run.tcl \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../modules/wr_dacs/cute_serial_dac.vhd \
../../modules/wr_dacs/spec_serial_dac.vhd \
../../modules/wrc_core/wrc_diags_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../modules/wr_pps_gen/xwr_pps_gen.vhd \
../../board/common/xwrc_board_common.vhd \
../../ip_cores/gn4124-core/hdl/cute/ip_cores/l2p_fifo.ngc \
../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
......@@ -288,11 +292,9 @@ run.tcl \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../modules/wr_si57x_interface/wr_si57x_interface.vhd \
../../modules/wr_softpll_ng/spll_aligner.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd \
cute_wr_ref.xise \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../modules/wr_endpoint/wr_endpoint.vhd \
../../modules/wr_streamers/escape_detector.vhd \
......@@ -322,12 +324,14 @@ cute_wr_ref.xise \
../../modules/wr_eca/eca_internals_pkg.vhd \
../../modules/wr_streamers/xtx_streamer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../modules/wr_dacs/cute_serial_dac_arb.vhd \
../../ip_cores/general-cores/modules/common/gc_comparator.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
......@@ -342,16 +346,18 @@ cute_wr_ref.xise \
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../modules/timing/pulse_gen.vhd \
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../board/cute/cute_reset_gen.vhd \
../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../board/cute/wrc_board_cute.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../modules/wr_streamers/wr_streamers_wb.vhd \
../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_line.vhd \
......@@ -363,7 +369,6 @@ cute_wr_ref.xise \
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../modules/wr_eca/eca_search.vhd \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
......@@ -373,8 +378,6 @@ cute_wr_ref.xise \
../../modules/wr_eca/eca_queue_auto.vhd \
../../modules/wr_streamers/tx_streamer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../top/cute_ref_design/cute_core_ref_top.vhd \
../../top/cute_ref_design/cute_wr_ref_top.vhd \
../../modules/wr_eca/eca_wr_time.vhd \
../../modules/wr_streamers/xrx_streamer.vhd \
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
......
syn/cute_ref_design/cute_wr_ref.xise
View file @ 13169b65
......@@ -19,9 +19,6 @@
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
......@@ -35,8 +32,8 @@
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -81,7 +78,6 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -94,7 +90,6 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -116,7 +111,7 @@
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -134,8 +129,7 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|cute_wr_ref_top|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/cute_ref_design/cute_wr_ref_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|cute_wr_ref_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cute_wr_ref_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -148,7 +142,7 @@
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft" xil_pn:valueState="non-default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
......@@ -158,7 +152,7 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
......@@ -201,7 +195,7 @@
<property xil_pn:name="Output File Name" xil_pn:value="cute_wr_ref_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Outputs Only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -221,7 +215,6 @@
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -335,8 +328,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-02-20T14:40:16" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6841520F5DB4380D7FA352D3187A85B6" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-24T11:39:40" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="574109865E841D46499DFB09720CA881" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......@@ -344,1000 +337,1013 @@
<libraries/>
<files>
<file xil_pn:name="../../top/cute_ref_design/cute_wr_ref_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../top/cute_ref_design/cute_wr_ref_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
<file xil_pn:name="../../modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_free.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../board/cute/wr_cute_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_msi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_loopback/lbk_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../modules/wr_dacs/cute_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
<file xil_pn:name="../../modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_auto.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../board/cute/wr_cute_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../modules/wr_dacs/cute_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_ac_wbm_auto.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../board/cute/xwrc_board_cute.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_tlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_scan.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/dropping_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_reg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_scubus_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../board/cute/xwrc_board_cute.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/streamers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/rx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
<file xil_pn:name="../../platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_diags_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../modules/wr_tlu/tlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../top/cute_ref_design/cute_wr_ref_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_piso_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_rmw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../modules/wr_dacs/cute_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
<file xil_pn:name="../../modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../modules/wrc_core/wrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../board/common/xwrc_board_common.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_tlu_auto.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_tlu_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/streamers_priv_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file>
<file xil_pn:name="../../board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="../../modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/escape_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_ac_wbm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_data.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="248"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_queue.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="249"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="250"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="251"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="252"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="253"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="254"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
<association xil_pn:name="Implementation" xil_pn:seqID="255"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="256"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="257"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="258"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="259"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="260"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="261"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="262"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="263"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="264"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="265"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../modules/wr_dacs/cute_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="266"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_comparator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="267"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="268"/>
</file>
<file xil_pn:name="../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="269"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
<association xil_pn:name="Implementation" xil_pn:seqID="270"/>
</file>
<file xil_pn:name="../../modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
<file xil_pn:name="../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="271"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="272"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="273"/>
</file>
<file xil_pn:name="../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="274"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="275"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="276"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="277"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="278"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
<association xil_pn:name="Implementation" xil_pn:seqID="279"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="280"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="281"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="282"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="283"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="284"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="285"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="286"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="287"/>
</file>
<file xil_pn:name="../../modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="288"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="289"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="290"/>
</file>
<file xil_pn:name="../../board/cute/cute_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="291"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="292"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
<association xil_pn:name="Implementation" xil_pn:seqID="293"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="294"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="295"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="296"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="297"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/wr_streamers_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
<association xil_pn:name="Implementation" xil_pn:seqID="298"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="299"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_line.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="300"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="301"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="302"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_tag_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="303"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="304"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="305"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="306"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="307"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="308"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="309"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_queue_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="310"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="311"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="312"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="313"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="314"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_queue_auto.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="315"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/tx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="316"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/cute_ref_design/cute_wr_ref_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
<association xil_pn:name="Implementation" xil_pn:seqID="317"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="318"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="319"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="320"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="321"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
<association xil_pn:name="Implementation" xil_pn:seqID="322"/>
</file>
<file xil_pn:name="../../modules/wr_streamers/escape_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
<association xil_pn:name="Implementation" xil_pn:seqID="323"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="324"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="325"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
<association xil_pn:name="Implementation" xil_pn:seqID="326"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="327"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="328"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="329"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="330"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="331"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="332"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="333"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="334"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="335"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../board/cute/cute_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="332"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../top/cute_ref_design/cute_core_ref_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="336"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
<association xil_pn:name="Implementation" xil_pn:seqID="336"/>
</file>
</files>
......
top/cute_ref_design/Manifest.py
View file @ 13169b65
fetchto = "../../ip_cores"
files = [
"cute_core_ref_top.vhd",
"cute_wr_ref_top.vhd",
"cute_wr_ref_top.ucf",
]
......
top/cute_ref_design/cute_core_ref_top.vhd
View file @ 13169b65
......@@ -97,7 +97,6 @@ entity cute_core_ref_top is
sfp0_tx_fault_i : in std_logic:='0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic:='0';
sfp0_refclk_sel_i : in std_logic_vector(2 downto 0);
sfp0_rx_rbclk_o : out std_logic;
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
......@@ -112,7 +111,6 @@ entity cute_core_ref_top is
sfp1_tx_fault_i : in std_logic:='0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic:='0';
sfp1_refclk_sel_i : in std_logic_vector(2 downto 0);
sfp1_rx_rbclk_o : out std_logic;
---------------------------------------------------------------------------
......@@ -202,7 +200,6 @@ begin
sfp0_tx_fault_i => sfp0_tx_fault_i,
sfp0_tx_disable_o => sfp0_tx_disable_o,
sfp0_los_i => sfp0_los_i,
sfp0_refclk_sel_i => sfp0_refclk_sel_i,
sfp0_rx_rbclk_o => sfp0_rx_rbclk_o,
sfp1_txp_o => sfp1_txp_o,
sfp1_txn_o => sfp1_txn_o,
......@@ -217,7 +214,6 @@ begin
sfp1_tx_fault_i => sfp1_tx_fault_i,
sfp1_tx_disable_o => sfp1_tx_disable_o,
sfp1_los_i => sfp1_los_i,
sfp1_refclk_sel_i => sfp1_refclk_sel_i,
sfp1_rx_rbclk_o => sfp1_rx_rbclk_o,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
......
top/cute_ref_design/cute_wr_ref_top.ucf
View file @ 13169b65
......@@ -15,9 +15,10 @@ config vccaux = 3.3;
#net "la29_n" loc = a16;net "la29_n" iostandard = lvds_33;
#net "la24_p" loc = e14;net "la24_p" iostandard = lvds_33;
#net "la24_n" loc = d15;net "la24_n" iostandard = lvds_33;
net "fpga_clk_p" loc = f12;net "fpga_clk_p" iostandard = lvds_33;
net "fpga_clk_n" loc = e12;net "fpga_clk_n" iostandard = lvds_33;
net "clk_125m_pllref_p_i" loc = f12;
net "clk_125m_pllref_p_i" iostandard = lvds_33;
net "clk_125m_pllref_n_i" loc = e12;
net "clk_125m_pllref_n_i" iostandard = lvds_33;
# bank 1
net "pps_out" loc = c18;net "pps_out" iostandard = lvcmos33;
......@@ -30,7 +31,6 @@ net "usr_led2" loc = d17;net "usr_led2" iostandard = lvcmos33;
#net "sfp1_scl" loc = g18;net "sfp1_scl" iostandard = lvcmos33;
#net "sfp1_sda" loc = h17;net "sfp1_sda" iostandard = lvcmos33;
#net "sfp1_tx_disable" loc = h18;net "sfp1_tx_disable" iostandard = lvcmos33;
net "eeprom_sda" loc = j18;net "eeprom_sda" iostandard = lvcmos33;
net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
......@@ -40,7 +40,6 @@ net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
#net "la33_n" loc = t18;net "la33_n" iostandard = lvds_33;
#net "la31_p" loc = u17;net "la31_p" iostandard = lvds_33;
#net "la31_n" loc = u18;net "la31_n" iostandard = lvds_33;
# bank 2
net "flash_sclk_o" loc = r15;net "flash_sclk_o" iostandard = lvcmos33;
net "flash_ncs_o" loc = v3;net "flash_ncs_o" iostandard = lvcmos33;
......@@ -99,9 +98,8 @@ net "flash_miso_i" loc = r13;net "flash_miso_i" iostandard = lvcmos33;
#net "la06_n" loc = v4;net "la06_n" iostandard = lvds_33;
#net "la05_p" loc = n5;net "la05_p" iostandard = lvds_33;
#net "la05_n" loc = p6;net "la05_n" iostandard = lvds_33;
# bank 3
net "clk20" loc = h1;net "clk20" iostandard = lvcmos33;
net "clk20m_vcxo_i" loc = h1;net "clk20m_vcxo_i" iostandard = lvcmos33;
net "usr_button" loc = h3;net "usr_button" iostandard = lvcmos33;
net "one_wire" loc = h2;net "one_wire" iostandard = lvcmos33;
net "uart_rx" loc = j1;net "uart_rx" iostandard = lvcmos33;
......@@ -131,35 +129,28 @@ net "sfp0_rx_p" loc = d7;
net "sfp0_tx_n" loc = a6;
net "sfp0_tx_p" loc = b6;
net "sfp1_ref_clk_n" loc = e10;net "sfp1_ref_clk_n" iostandard = lvcmos33;
net "sfp1_ref_clk_p" loc = f10;net "sfp1_ref_clk_p" iostandard = lvcmos33;
#net "sfp1_ref_clk_n" loc = e10;net "sfp1_ref_clk_n" iostandard = lvcmos33;
#net "sfp1_ref_clk_p" loc = f10;net "sfp1_ref_clk_p" iostandard = lvcmos33;
#net "sfp1_rx_n" loc = c13;
#net "sfp1_rx_p" loc = d13;
#net "sfp1_tx_n" loc = a14;
#net "sfp1_tx_p" loc = b14;
#net "mgtrx0_n" loc = c5;
#net "mgtrx0_p" loc = d5;
#net "mgttx0_n" loc = a4;
#net "mgttx0_p" loc = b4;
#---------------------------------------------------------------------------------------------
# clock period information
#---------------------------------------------------------------------------------------------
net "clk20" tnm_net = "clk20";
timespec ts_clk20 = period "clk20" 50 ns high 50 %;
net "fpga_clk_i" tnm_net = "fpga_clk_i";
timespec ts_fpga_clk_i = period "fpga_clk_i" 8 ns high 50 %;
net "clk_sfp*_i" tnm_net = "clk_sfp_i";
timespec ts_clk_sfp_i = period "clk_sfp_i" 8 ns high 50 %;
net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_rx_rbclk_o" tnm_net = "phy_rx_clk";
timespec ts_phy_rx_clk = period "phy_rx_clk" 8 ns high 50 %;
net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_rx_divclk" tnm_net = "ch_rx_divclk";
timespec ts_ch_rx_divclk = period "ch_rx_divclk" 8 ns high 50 %;
net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_gtp_clkout_int[1]" tnm_net = "ch_gtp_clkout_int";
timespec ts_ch_gtp_clkout_int = period "ch_gtp_clkout_int" 8 ns high 50 %;
\ No newline at end of file
NET "clk20m_vcxo_i" TNM_NET = clk20m_vcxo_i;
TIMESPEC TS_clk20m_vcxo_i = PERIOD "clk20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "sfp0_ref_clk_n" TNM_NET = sfp0_ref_clk_n;
TIMESPEC TS_sfp0_ref_clk_n = PERIOD "sfp0_ref_clk_n" 8 ns HIGH 50%;
NET "sfp0_ref_clk_p" TNM_NET = sfp0_ref_clk_p;
TIMESPEC TS_sfp0_ref_clk_p = PERIOD "sfp0_ref_clk_p" 8 ns HIGH 50%;
NET "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" TNM_NET = u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>;
TIMESPEC TS_u_wr_core_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch_gtp_clkout_int_1_ = PERIOD "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" 8 ns HIGH 50%;
top/cute_ref_design/cute_wr_ref_top.vhd
View file @ 13169b65
-------------------------------------------------------------------------------
-- Title : WRPC reference design for CUTE
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : cute_wr_ref_top.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : Tsinghua Univ. (DEP), CERN
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CUTE.
--
-- This is a reference top HDL that instanciates the WR PTP Core together with
-- its peripherals to be run on a CUTE board.
--
-- There are two main usecases for this HDL file:
-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
-- reference hardware
-- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects.
--
-- CUTE: https://www.ohwr.org/projects/cute-wr-dp
--
-------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -7,238 +54,126 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_cute_pkg.all;
use work.wrcore_pkg.all;
use work.wr_xilinx_pkg.all;
use work.endpoint_pkg.all;
use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity cute_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_sfp0_enable : boolean:= true;
g_sfp1_enable : boolean:= false;
g_aux_sdb : t_sdb_device := c_xwb_xil_multiboot_sdb;
g_multiboot_enable : boolean:= true
);
port
(
-- clock
clk20 : in std_logic; -- 20mhz vcxo clock
fpga_clk_p : in std_logic; -- 125 mhz pll reference
fpga_clk_n : in std_logic;
sfp0_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp0_ref_clk_n : in std_logic;
sfp1_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp1_ref_clk_n : in std_logic;
-- pll
plldac_sclk : out std_logic;
plldac_din : out std_logic;
plldac_clr_n : out std_logic;
plldac_load_n : out std_logic;
plldac_sync_n : out std_logic;
-- eeprom
eeprom_scl : inout std_logic;
eeprom_sda : inout std_logic;
-- 1-wire
one_wire : inout std_logic; -- 1-wire interface to ds18b20
-- flash
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
-- sfp0 pins
sfp0_tx_p : out std_logic;
sfp0_tx_n : out std_logic;
sfp0_rx_p : in std_logic;
sfp0_rx_n : in std_logic;
sfp0_det : in std_logic; -- sfp detect
sfp0_scl : inout std_logic; -- scl
sfp0_sda : inout std_logic; -- sda
sfp0_tx_fault : in std_logic;
sfp0_tx_disable : out std_logic;
sfp0_los : in std_logic;
--sfp1_tx_p : out std_logic;
--sfp1_tx_n : out std_logic;
--sfp1_rx_p : in std_logic;
--sfp1_rx_n : in std_logic;
--sfp1_det : in std_logic; -- sfp detect
--sfp1_scl : inout std_logic; -- scl
--sfp1_sda : inout std_logic; -- sda
--sfp1_tx_fault : in std_logic;
--sfp1_tx_disable : out std_logic;
--sfp1_tx_los : in std_logic;
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_sfp0_enable : integer:= 1;
g_sfp1_enable : integer:= 0;
g_aux_sdb : t_sdb_device := c_xwb_xil_multiboot_sdb;
g_multiboot_enable : boolean:= false
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
--uart
uart_rx : in std_logic;
uart_tx : out std_logic;
-- user interface
sfp0_led : out std_logic;
sfp1_led : out std_logic;
--ext_clk : out std_logic;
usr_button : in std_logic;
usr_led1 : out std_logic;
usr_led2 : out std_logic;
pps_out : out std_logic
);
end cute_wr_ref_top;
-- Local oscillators
clk20m_vcxo_i : in std_logic; -- 20mhz vcxo clock
architecture rtl of cute_wr_ref_top is
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
------------------------------------------------------------------------------
-- components declaration
------------------------------------------------------------------------------
component cute_reset_gen is
port (
clk_sys_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end component;
sfp0_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp0_ref_clk_n : in std_logic;
sfp1_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp1_ref_clk_n : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
component cute_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
plldac_sclk : out std_logic;
plldac_din : out std_logic;
plldac_clr_n : out std_logic;
plldac_load_n : out std_logic;
plldac_sync_n : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp0_tx_p : out std_logic;
sfp0_tx_n : out std_logic;
sfp0_rx_p : in std_logic;
sfp0_rx_n : in std_logic;
sfp0_det : in std_logic; -- sfp detect
sfp0_scl : inout std_logic; -- scl
sfp0_sda : inout std_logic; -- sda
sfp0_tx_fault : in std_logic;
sfp0_tx_disable : out std_logic;
sfp0_los : in std_logic;
--sfp1_tx_p : out std_logic;
--sfp1_tx_n : out std_logic;
--sfp1_rx_p : in std_logic;
--sfp1_rx_n : in std_logic;
--sfp1_det : in std_logic; -- sfp detect
--sfp1_scl : inout std_logic; -- scl
--sfp1_sda : inout std_logic; -- sda
--sfp1_tx_fault : in std_logic;
--sfp1_tx_disable : out std_logic;
--sfp1_tx_los : in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
one_wire : inout std_logic; -- 1-wire interface to ds18b20
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rx : in std_logic;
uart_tx : out std_logic;
dac_ldac_n_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_sync_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
---------------------------------------------------------------------------
-- I2C configuration EEPROM interface
---------------------------------------------------------------------------
eeprom_scl : inout std_logic;
eeprom_sda : inout std_logic;
end component;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
component cute_core_ref_top is
generic
(
g_simulation : integer := 0;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_sfp0_enable : boolean:= true;
g_sfp1_enable : boolean:= false;
g_aux_sdb : t_sdb_device := c_xwb_xil_multiboot_sdb;
g_multiboot_enable : boolean:= false);
port
(
rst_n_i : in std_logic;
clk_20m_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
clk_sfp0_i : in std_logic :='0';
clk_sfp1_i : in std_logic :='0';
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic:='0';
uart_txd_o : out std_logic;
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic:='0';
sfp0_rxn_i : in std_logic:='0';
sfp0_det_i : in std_logic:='0'; -- sfp detect
sfp0_scl_i : in std_logic:='0'; -- scl
sfp0_scl_o : out std_logic; -- scl
sfp0_sda_i : in std_logic:='0'; -- sda
sfp0_sda_o : out std_logic; -- sda
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic:='0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic:='0';
sfp0_refclk_sel_i : in std_logic_vector(2 downto 0):="000";
sfp0_rx_rbclk_o : out std_logic;
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic:='0';
sfp1_rxn_i : in std_logic:='0';
sfp1_det_i : in std_logic:='0';
sfp1_scl_i : in std_logic:='0';
sfp1_scl_o : out std_logic:='0';
sfp1_sda_i : in std_logic:='0';
sfp1_sda_o : out std_logic:='0';
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic:='0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic:='0';
sfp1_refclk_sel_i : in std_logic_vector(2 downto 0):="000";
sfp1_rx_rbclk_o : out std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
link_ok_o : out std_logic
);
end component;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
---------------------------------------------------------------------------
-- Miscellanous I/O pins
---------------------------------------------------------------------------
-- user interface
sfp0_led : out std_logic;
sfp1_led : out std_logic;
--ext_clk : out std_logic;
usr_button : in std_logic;
usr_led1 : out std_logic;
usr_led2 : out std_logic;
pps_out : out std_logic
);
end cute_wr_ref_top;
architecture rtl of cute_wr_ref_top is
------------------------------------------------------------------------------
-- signals declaration
------------------------------------------------------------------------------
-- reset
signal local_reset_n : std_logic;
-- clock
signal fpga_clk_i : std_logic;
signal clk_ref_i : std_logic;
signal clk_sys_i : std_logic;
signal clk_dmtd_i : std_logic;
signal clk_sfp0_i : std_logic;
signal clk_sfp1_i : std_logic;
signal clk_20m_buf : std_logic;
signal pllout_clk_62_5 : std_logic;
signal pllout_clk_125 : std_logic;
signal pllout_clk_fb_ref : std_logic;
signal pllout_clk_fb_dmtd: std_logic;
signal pllout_clk_dmtd : std_logic;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- I2C EEPROM
signal eeprom_scl_o : std_logic;
signal eeprom_scl_i : std_logic;
signal eeprom_sda_o : std_logic;
signal eeprom_sda_i : std_logic;
-- OneWire
signal onewire_i : std_logic;
signal onewire_oen_o : std_logic;
-- SFP
signal sfp0_scl_i : std_logic;
signal sfp0_scl_o : std_logic;
signal sfp0_sda_i : std_logic;
......@@ -247,10 +182,6 @@ end component;
signal sfp1_scl_o : std_logic;
signal sfp1_sda_i : std_logic;
signal sfp1_sda_o : std_logic;
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal pps_p1 : std_logic;
......@@ -263,229 +194,113 @@ end component;
signal cnx_slave_out : t_wishbone_slave_out_array(0 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(0 downto 0);
begin
u_reset_gen : cute_reset_gen
port map (
clk_sys_i => clk_sys_i,
rst_button_n_a_i => usr_button,
rst_n_o => local_reset_n);
cmp_refclk_buf : ibufgds
generic map (
diff_term => true, -- differential termination
ibuf_low_pwr => true, -- low power (true) vs. performance (false) setting for referenced i/o standards
iostandard => "default")
port map (
o => fpga_clk_i, -- buffer output
i => fpga_clk_p, -- diff_p buffer input (connect directly to top-level port)
ib => fpga_clk_n); -- diff_n buffer input (connect directly to top-level port)
cmp_clk_vcxo_buf : bufg
port map (
o => clk_20m_buf,
i => clk20);
cmp_sfp0_dedicated_clk_buf : ibufds
generic map(
diff_term => true,
ibuf_low_pwr => true,
iostandard => "default")
port map (
o => clk_sfp0_i,
i => sfp0_ref_clk_p,
ib => sfp0_ref_clk_n);
cmp_sfp1_dedicated_clk_buf : ibufds
generic map(
diff_term => true,
ibuf_low_pwr => true,
iostandard => "default")
port map (
o => clk_sfp1_i,
i => sfp1_ref_clk_p,
ib => sfp1_ref_clk_n);
cmp_sys_clk_pll : pll_base
generic map (
bandwidth => "optimized",
clk_feedback => "clkfbout",
compensation => "internal",
divclk_divide => 1,
clkfbout_mult => 8,
clkfbout_phase => 0.000,
clkout0_divide => 16, -- 62.5 mhz
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkout1_divide => 8, -- 125 mhz
clkout1_phase => 0.000,
clkout1_duty_cycle => 0.500,
clkout2_divide => 4, -- 250 mhz
clkout2_phase => 0.000,
clkout2_duty_cycle => 0.500,
clkin_period => 8.0,
ref_jitter => 0.016)
port map (
clkfbout => pllout_clk_fb_ref,
clkout0 => pllout_clk_62_5,
clkout1 => pllout_clk_125,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => open,
rst => '0',
clkfbin => pllout_clk_fb_ref,
clkin => fpga_clk_i);
cmp_dmtd_clk_pll : pll_base
generic map (
bandwidth => "optimized",
clk_feedback => "clkfbout",
compensation => "internal",
divclk_divide => 1,
clkfbout_mult => 50,
clkfbout_phase => 0.000,
clkout0_divide => 16, -- 62.5 mhz
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkout1_divide => 16, -- 62.5 mhz
clkout1_phase => 0.000,
clkout1_duty_cycle => 0.500,
clkout2_divide => 16, -- 62.5 mhz
clkout2_phase => 0.000,
clkout2_duty_cycle => 0.500,
clkin_period => 50.0,
ref_jitter => 0.016)
port map (
clkfbout => pllout_clk_fb_dmtd,
clkout0 => pllout_clk_dmtd,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => open,
rst => '0',
clkfbin => pllout_clk_fb_dmtd,
clkin => clk_20m_buf);
-- Not needed now, but useful if application cores are added
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
cmp_clk_sys_buf : bufg
port map (
o => clk_sys_i,
i => pllout_clk_62_5);
begin
cmd_clk_ref_buf: bufg
port map(
o => clk_ref_i,
i => pllout_clk_125);
u_wr_core : xwrc_board_cute
generic map(
g_dpram_initf => g_dpram_initf,
g_sfp0_enable => g_sfp0_enable,
g_sfp1_enable => g_sfp1_enable,
g_aux_sdb => g_aux_sdb,
g_cute_version => "2.1",
g_multiboot_enable => g_multiboot_enable)
port map (
areset_n_i => usr_button,
clk_20m_vcxo_i => clk20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp0_p_i => sfp0_ref_clk_p,
clk_125m_gtp0_n_i => sfp0_ref_clk_n,
clk_125m_gtp1_p_i => sfp1_ref_clk_p,
clk_125m_gtp1_n_i => sfp1_ref_clk_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
plldac_sclk_o => plldac_sclk,
plldac_din_o => plldac_din,
plldac_clr_n_o => plldac_clr_n,
plldac_load_n_o => plldac_load_n,
plldac_sync_n_o => plldac_sync_n,
sfp0_txp_o => sfp0_tx_p,
sfp0_txn_o => sfp0_tx_n,
sfp0_rxp_i => sfp0_rx_p,
sfp0_rxn_i => sfp0_rx_n,
sfp0_det_i => sfp0_det,
sfp0_scl_i => sfp0_scl_i,
sfp0_scl_o => sfp0_scl_o,
sfp0_sda_i => sfp0_sda_i,
sfp0_sda_o => sfp0_sda_o,
sfp0_rate_select_o => open,
sfp0_tx_fault_i => sfp0_tx_fault,
sfp0_tx_disable_o => sfp0_tx_disable,
sfp0_los_i => sfp0_los,
--sfp1_txp_o => sfp1_tx_p,
--sfp1_txn_o => sfp1_tx_n,
--sfp1_rxp_i => sfp1_rx_p,
--sfp1_rxn_i => sfp1_rx_n,
--sfp1_det_i => sfp1_det,
--sfp1_scl_i => sfp1_scl_i,
--sfp1_scl_o => sfp1_scl_o,
--sfp1_sda_i => sfp1_sda_i,
--sfp1_sda_o => sfp1_sda_o,
--sfp1_rate_select_o => open,
--sfp1_tx_fault_i => sfp1_tx_fault,
--sfp1_tx_disable_o => sfp1_tx_disable,
--sfp1_los_i => sfp1_tx_los,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
eeprom_sda_i => eeprom_sda_i,
eeprom_sda_o => eeprom_sda_o,
onewire_i => onewire_i,
onewire_oen_o => onewire_oen_o,
uart_rxd_i => uart_rx,
uart_txd_o => uart_tx,
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
cmp_clk_dmtd_buf : bufg
port map (
o => clk_dmtd_i,
i => pllout_clk_dmtd);
wb_slave_o => cnx_slave_out(0),
wb_slave_i => cnx_slave_in(0),
u_wr_core : cute_core_ref_top
generic map(
g_dpram_initf => g_dpram_initf,
g_sfp0_enable => g_sfp0_enable,
g_sfp1_enable => g_sfp1_enable,
g_aux_sdb => g_aux_sdb,
g_multiboot_enable => g_multiboot_enable)
port map (
rst_n_i => local_reset_n,
clk_20m_i => clk_20m_buf,
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
clk_ref_i => clk_ref_i,
clk_sfp0_i => clk_sfp0_i,
clk_sfp1_i => clk_sfp1_i,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
eeprom_sda_i => eeprom_sda_i,
eeprom_sda_o => eeprom_sda_o,
onewire_i => onewire_i,
onewire_oen_o => onewire_oen_o,
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
uart_rxd_i => uart_rx,
uart_txd_o => uart_tx,
sfp0_txp_o => sfp0_tx_p,
sfp0_txn_o => sfp0_tx_n,
sfp0_rxp_i => sfp0_rx_p,
sfp0_rxn_i => sfp0_rx_n,
sfp0_det_i => sfp0_det,
sfp0_scl_i => sfp0_scl_i,
sfp0_scl_o => sfp0_scl_o,
sfp0_sda_i => sfp0_sda_i,
sfp0_sda_o => sfp0_sda_o,
sfp0_rate_select_o => open,
sfp0_tx_fault_i => sfp0_tx_fault,
sfp0_tx_disable_o => sfp0_tx_disable,
sfp0_los_i => sfp0_los,
sfp0_refclk_sel_i => "100",
sfp0_rx_rbclk_o => open,
--sfp1_txp_o => sfp1_tx_p,
--sfp1_txn_o => sfp1_tx_n,
--sfp1_rxp_i => sfp1_rx_p,
--sfp1_rxn_i => sfp1_rx_n,
--sfp1_det_i => sfp1_det,
--sfp1_scl_i => sfp1_scl_i,
--sfp1_scl_o => sfp1_scl_o,
--sfp1_sda_i => sfp1_sda_i,
--sfp1_sda_o => sfp1_sda_o,
--sfp1_rate_select_o => open,
--sfp1_tx_fault_i => sfp1_tx_fault,
--sfp1_tx_disable_o => sfp1_tx_disable,
--sfp1_los_i => sfp1_tx_los,
--sfp1_refclk_sel_i => "100",
--sfp1_rx_rbclk_o => open,
wb_slave_o => cnx_slave_out(0),
wb_slave_i => cnx_slave_in(0),
wb_eth_master_o => cnx_master_out(0),
wb_eth_master_i => cnx_master_in(0),
tm_link_up_o => open,
tm_time_valid_o => tm_tai_valid,
tm_tai_o => tm_tai,
tm_cycles_o => open,
led_act_o => sfp0_led,
led_link_o => sfp1_led,
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_csync_o => pps_p1,
link_ok_o => usr_led2);
wb_eth_master_o => cnx_master_out(0),
wb_eth_master_i => cnx_master_in(0),
tm_link_up_o => open,
tm_time_valid_o => tm_tai_valid,
tm_tai_o => tm_tai,
tm_cycles_o => open,
led_act_o => sfp0_led,
led_link_o => sfp1_led,
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_csync_o => pps_p1,
link_ok_o => usr_led2);
cnx_slave_in <= cnx_master_out;
cnx_master_in <= cnx_slave_out;
u_dac_arb: cute_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys_i,
rst_n_i => local_reset_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_sync_n_o => plldac_sync_n,
dac_ldac_n_o => plldac_load_n,
dac_clr_n_o => plldac_clr_n,
dac_sclk_o => plldac_sclk,
dac_din_o => plldac_din);
-- Tristates for configuration EEPROM
eeprom_scl <= '0' when eeprom_scl_o = '0' else 'Z';
eeprom_sda <= '0' when eeprom_sda_o = '0' else 'Z';
eeprom_scl_i <= eeprom_scl;
eeprom_sda_i <= eeprom_sda;
-- Tristates for SFP EEPROM
sfp0_scl <= '0' when sfp0_scl_o = '0' else 'Z';
sfp0_sda <= '0' when sfp0_sda_o = '0' else 'Z';
sfp0_scl_i <= sfp0_scl;
......@@ -495,6 +310,7 @@ u_wr_core : cute_core_ref_top
--sfp1_scl_i <= sfp1_scl;
--sfp1_sda_i <= sfp1_sda;
-- Tristates for Onewire
one_wire <= '0' when onewire_oen_o = '1' else 'Z';
onewire_i <= one_wire;
......
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