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White Rabbit core collection
Commit 13169b65 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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cute_wr: reorganize board wrapper to match other board wrappers

parent 7be63043
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board/cute/cute_reset_gen.vhd deleted 100644 → 0
View file @ 7be63043
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cute_reset_gen is
port (
clk_sys_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end cute_reset_gen;
architecture behavioral of cute_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal powerup_n : std_logic := '0';
signal button_synced_n : std_logic;
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component;
begin -- behavioral
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n;
end behavioral;
board/cute/wr_cute_pkg.vhd
View file @ 13169b65
......@@ -46,7 +46,7 @@ use work.streamers_pkg.all;
package wr_cute_pkg is
component xwrc_board_cute is
generic (
generic(
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 0;
......@@ -60,58 +60,63 @@ package wr_cute_pkg is
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
-- cute special
g_sfp0_enable : boolean:= true;
g_sfp1_enable : boolean:= false;
g_multiboot_enable : boolean:= false);
-- CUTE special
g_cute_version : string := "2.2";
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false);
port (
rst_n_i : in std_logic;
clk_20m_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
clk_sfp0_i : in std_logic :='0';
clk_sfp1_i : in std_logic :='0';
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp0_p_i : in std_logic :='0';
clk_125m_gtp0_n_i : in std_logic :='0';
clk_125m_gtp1_p_i : in std_logic :='0';
clk_125m_gtp1_n_i : in std_logic :='0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
plldac_clr_n_o : out std_logic;
plldac_load_n_o : out std_logic;
plldac_sync_n_o : out std_logic;
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic;
sfp0_rxn_i : in std_logic;
sfp0_det_i : in std_logic;
sfp0_scl_i : in std_logic;
sfp0_scl_o : out std_logic;
sfp0_sda_i : in std_logic;
sfp0_rxp_i : in std_logic := '0';
sfp0_rxn_i : in std_logic := '0';
sfp0_det_i : in std_logic := '0';
sfp0_sda_i : in std_logic := '1';
sfp0_sda_o : out std_logic;
sfp0_scl_i : in std_logic := '1';
sfp0_scl_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic;
sfp0_tx_fault_i : in std_logic := '0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic;
sfp0_refclk_sel_i : in std_logic_vector(2 downto 0):="110";
sfp0_rx_rbclk_o : out std_logic;
sfp0_los_i : in std_logic := '0';
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic;
sfp1_rxn_i : in std_logic;
sfp1_det_i : in std_logic;
sfp1_scl_i : in std_logic;
sfp1_scl_o : out std_logic;
sfp1_sda_i : in std_logic;
sfp1_rxp_i : in std_logic := '0';
sfp1_rxn_i : in std_logic := '0';
sfp1_det_i : in std_logic := '0';
sfp1_sda_i : in std_logic := '1';
sfp1_sda_o : out std_logic;
sfp1_scl_i : in std_logic := '1';
sfp1_scl_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic;
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic;
sfp1_refclk_sel_i : in std_logic_vector(2 downto 0):="110";
sfp1_rx_rbclk_o : out std_logic;
eeprom_sda_i : in std_logic := '1';
sfp1_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic := '1';
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
......@@ -120,7 +125,7 @@ package wr_cute_pkg is
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
flash_miso_i : in std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
......@@ -129,6 +134,18 @@ package wr_cute_pkg is
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
......@@ -159,7 +176,7 @@ package wr_cute_pkg is
link_ok_o : out std_logic);
end component xwrc_board_cute;
constant c_xwb_tcpip_sdb : t_sdb_device := (
constant c_xwb_tcpip_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -174,4 +191,5 @@ constant c_xwb_tcpip_sdb : t_sdb_device := (
version => x"00000001",
date => x"20160424",
name => "wr-tcp-ip-stack ")));
end wr_cute_pkg;
board/cute/xwrc_board_cute.vhd
View file @ 13169b65
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syn/cute_ref_design/Makefile
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syn/cute_ref_design/cute_wr_ref.xise
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top/cute_ref_design/Manifest.py
View file @ 13169b65
fetchto = "../../ip_cores"
files = [
"cute_core_ref_top.vhd",
"cute_wr_ref_top.vhd",
"cute_wr_ref_top.ucf",
]
......
top/cute_ref_design/cute_core_ref_top.vhd
View file @ 13169b65
......@@ -97,7 +97,6 @@ entity cute_core_ref_top is
sfp0_tx_fault_i : in std_logic:='0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic:='0';
sfp0_refclk_sel_i : in std_logic_vector(2 downto 0);
sfp0_rx_rbclk_o : out std_logic;
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
......@@ -112,7 +111,6 @@ entity cute_core_ref_top is
sfp1_tx_fault_i : in std_logic:='0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic:='0';
sfp1_refclk_sel_i : in std_logic_vector(2 downto 0);
sfp1_rx_rbclk_o : out std_logic;
---------------------------------------------------------------------------
......@@ -202,7 +200,6 @@ begin
sfp0_tx_fault_i => sfp0_tx_fault_i,
sfp0_tx_disable_o => sfp0_tx_disable_o,
sfp0_los_i => sfp0_los_i,
sfp0_refclk_sel_i => sfp0_refclk_sel_i,
sfp0_rx_rbclk_o => sfp0_rx_rbclk_o,
sfp1_txp_o => sfp1_txp_o,
sfp1_txn_o => sfp1_txn_o,
......@@ -217,7 +214,6 @@ begin
sfp1_tx_fault_i => sfp1_tx_fault_i,
sfp1_tx_disable_o => sfp1_tx_disable_o,
sfp1_los_i => sfp1_los_i,
sfp1_refclk_sel_i => sfp1_refclk_sel_i,
sfp1_rx_rbclk_o => sfp1_rx_rbclk_o,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
......
top/cute_ref_design/cute_wr_ref_top.ucf
View file @ 13169b65
......@@ -15,9 +15,10 @@ config vccaux = 3.3;
#net "la29_n" loc = a16;net "la29_n" iostandard = lvds_33;
#net "la24_p" loc = e14;net "la24_p" iostandard = lvds_33;
#net "la24_n" loc = d15;net "la24_n" iostandard = lvds_33;
net "fpga_clk_p" loc = f12;net "fpga_clk_p" iostandard = lvds_33;
net "fpga_clk_n" loc = e12;net "fpga_clk_n" iostandard = lvds_33;
net "clk_125m_pllref_p_i" loc = f12;
net "clk_125m_pllref_p_i" iostandard = lvds_33;
net "clk_125m_pllref_n_i" loc = e12;
net "clk_125m_pllref_n_i" iostandard = lvds_33;
# bank 1
net "pps_out" loc = c18;net "pps_out" iostandard = lvcmos33;
......@@ -30,7 +31,6 @@ net "usr_led2" loc = d17;net "usr_led2" iostandard = lvcmos33;
#net "sfp1_scl" loc = g18;net "sfp1_scl" iostandard = lvcmos33;
#net "sfp1_sda" loc = h17;net "sfp1_sda" iostandard = lvcmos33;
#net "sfp1_tx_disable" loc = h18;net "sfp1_tx_disable" iostandard = lvcmos33;
net "eeprom_sda" loc = j18;net "eeprom_sda" iostandard = lvcmos33;
net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
......@@ -40,7 +40,6 @@ net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
#net "la33_n" loc = t18;net "la33_n" iostandard = lvds_33;
#net "la31_p" loc = u17;net "la31_p" iostandard = lvds_33;
#net "la31_n" loc = u18;net "la31_n" iostandard = lvds_33;
# bank 2
net "flash_sclk_o" loc = r15;net "flash_sclk_o" iostandard = lvcmos33;
net "flash_ncs_o" loc = v3;net "flash_ncs_o" iostandard = lvcmos33;
......@@ -99,9 +98,8 @@ net "flash_miso_i" loc = r13;net "flash_miso_i" iostandard = lvcmos33;
#net "la06_n" loc = v4;net "la06_n" iostandard = lvds_33;
#net "la05_p" loc = n5;net "la05_p" iostandard = lvds_33;
#net "la05_n" loc = p6;net "la05_n" iostandard = lvds_33;
# bank 3
net "clk20" loc = h1;net "clk20" iostandard = lvcmos33;
net "clk20m_vcxo_i" loc = h1;net "clk20m_vcxo_i" iostandard = lvcmos33;
net "usr_button" loc = h3;net "usr_button" iostandard = lvcmos33;
net "one_wire" loc = h2;net "one_wire" iostandard = lvcmos33;
net "uart_rx" loc = j1;net "uart_rx" iostandard = lvcmos33;
......@@ -131,35 +129,28 @@ net "sfp0_rx_p" loc = d7;
net "sfp0_tx_n" loc = a6;
net "sfp0_tx_p" loc = b6;
net "sfp1_ref_clk_n" loc = e10;net "sfp1_ref_clk_n" iostandard = lvcmos33;
net "sfp1_ref_clk_p" loc = f10;net "sfp1_ref_clk_p" iostandard = lvcmos33;
#net "sfp1_ref_clk_n" loc = e10;net "sfp1_ref_clk_n" iostandard = lvcmos33;
#net "sfp1_ref_clk_p" loc = f10;net "sfp1_ref_clk_p" iostandard = lvcmos33;
#net "sfp1_rx_n" loc = c13;
#net "sfp1_rx_p" loc = d13;
#net "sfp1_tx_n" loc = a14;
#net "sfp1_tx_p" loc = b14;
#net "mgtrx0_n" loc = c5;
#net "mgtrx0_p" loc = d5;
#net "mgttx0_n" loc = a4;
#net "mgttx0_p" loc = b4;
#---------------------------------------------------------------------------------------------
# clock period information
#---------------------------------------------------------------------------------------------
net "clk20" tnm_net = "clk20";
timespec ts_clk20 = period "clk20" 50 ns high 50 %;
net "fpga_clk_i" tnm_net = "fpga_clk_i";
timespec ts_fpga_clk_i = period "fpga_clk_i" 8 ns high 50 %;
net "clk_sfp*_i" tnm_net = "clk_sfp_i";
timespec ts_clk_sfp_i = period "clk_sfp_i" 8 ns high 50 %;
net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_rx_rbclk_o" tnm_net = "phy_rx_clk";
timespec ts_phy_rx_clk = period "phy_rx_clk" 8 ns high 50 %;
net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_rx_divclk" tnm_net = "ch_rx_divclk";
timespec ts_ch_rx_divclk = period "ch_rx_divclk" 8 ns high 50 %;
net "u_wr_core/cmp_xwrc_board_cute/*u_gtp*/ch*_gtp_clkout_int[1]" tnm_net = "ch_gtp_clkout_int";
timespec ts_ch_gtp_clkout_int = period "ch_gtp_clkout_int" 8 ns high 50 %;
\ No newline at end of file
NET "clk20m_vcxo_i" TNM_NET = clk20m_vcxo_i;
TIMESPEC TS_clk20m_vcxo_i = PERIOD "clk20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "sfp0_ref_clk_n" TNM_NET = sfp0_ref_clk_n;
TIMESPEC TS_sfp0_ref_clk_n = PERIOD "sfp0_ref_clk_n" 8 ns HIGH 50%;
NET "sfp0_ref_clk_p" TNM_NET = sfp0_ref_clk_p;
TIMESPEC TS_sfp0_ref_clk_p = PERIOD "sfp0_ref_clk_p" 8 ns HIGH 50%;
NET "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" TNM_NET = u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>;
TIMESPEC TS_u_wr_core_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch_gtp_clkout_int_1_ = PERIOD "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" 8 ns HIGH 50%;
top/cute_ref_design/cute_wr_ref_top.vhd
View file @ 13169b65
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