txtsu: move simulation model from wr-switch-hdl repo

13e46349 · Grzegorz Daniluk · 85c1f20e · 13e46349 · 13e46349
Commit 13e46349 authored Mar 11, 2019 by Grzegorz Daniluk
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simdrv_txtsu.svh sim/simdrv_txtsu.svh +58 -0

txtsu_regs.vh sim/txtsu_regs.vh +32 -0

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--- a/sim/simdrv_txtsu.svh
+++ b/sim/simdrv_txtsu.svh
+`ifndef __SIMDRV_WR_TXTSU_SVH
+`define __SIMDRV_WR_TXTSU_SVH 1
+
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "regs/txtsu_regs.vh"
+
+class CSimDrv_TXTSU;
+
+   CBusAccessor acc_regs;
+   
+   uint64_t base_addr;
+   
+   function new(CBusAccessor regs_, uint64_t base_addr_);
+      base_addr      = base_addr_;
+      acc_regs       = regs_;
+  endfunction // new
+
+   task init();
+      writel(`ADDR_TXTSU_EIC_IER, 1);
+   endtask // init
+   
+   
+   task writel(uint32_t addr, uint32_t val);
+      acc_regs.write(base_addr + addr, val, 4);
+   endtask // writel
+
+   task readl(uint32_t addr, output uint32_t val);
+      uint64_t tmp;
+      acc_regs.read(base_addr + addr, tmp, 4);
+      val  = tmp;
+   endtask // readl
+
+   task update(bit txts_irq);
+      uint32_t csr, r0, r1, r2;
+      
+      if(!txts_irq)
+        return;
+
+      while(1) begin
+         readl(`ADDR_TXTSU_TSF_CSR, csr);
+
+         if(csr & `TXTSU_TSF_CSR_EMPTY)
+           break;
+
+         
+         readl(`ADDR_TXTSU_TSF_R0, r0);
+         readl(`ADDR_TXTSU_TSF_R1, r1);
+         readl(`ADDR_TXTSU_TSF_R2, r2);
+         $display("txtsu: val %x pid %d fid %d incorrect %1b", r0, r1 & 'h1f, r1 >> 16, r2 & 1);
+      end // while (1)
+   endtask // update
+
+endclass
+
+`endif //  `ifndef __SIMDRV_WR_TXTSU_SVH
+
--- a/sim/txtsu_regs.vh
+++ b/sim/txtsu_regs.vh
+`define ADDR_TXTSU_EIC_IDR             5'h0
+`define TXTSU_EIC_IDR_NEMPTY_OFFSET 0
+`define TXTSU_EIC_IDR_NEMPTY 32'h00000001
+`define ADDR_TXTSU_EIC_IER             5'h4
+`define TXTSU_EIC_IER_NEMPTY_OFFSET 0
+`define TXTSU_EIC_IER_NEMPTY 32'h00000001
+`define ADDR_TXTSU_EIC_IMR             5'h8
+`define TXTSU_EIC_IMR_NEMPTY_OFFSET 0
+`define TXTSU_EIC_IMR_NEMPTY 32'h00000001
+`define ADDR_TXTSU_EIC_ISR             5'hc
+`define TXTSU_EIC_ISR_NEMPTY_OFFSET 0
+`define TXTSU_EIC_ISR_NEMPTY 32'h00000001
+`define ADDR_TXTSU_TSF_R0              5'h10
+`define TXTSU_TSF_R0_VAL_R_OFFSET 0
+`define TXTSU_TSF_R0_VAL_R 32'h0fffffff
+`define TXTSU_TSF_R0_VAL_F_OFFSET 28
+`define TXTSU_TSF_R0_VAL_F 32'hf0000000
+`define ADDR_TXTSU_TSF_R1              5'h14
+`define TXTSU_TSF_R1_PID_OFFSET 0
+`define TXTSU_TSF_R1_PID 32'h0000001f
+`define TXTSU_TSF_R1_FID_OFFSET 16
+`define TXTSU_TSF_R1_FID 32'hffff0000
+`define ADDR_TXTSU_TSF_R2              5'h18
+`define TXTSU_TSF_R2_INCORRECT_OFFSET 0
+`define TXTSU_TSF_R2_INCORRECT 32'h00000001
+`define ADDR_TXTSU_TSF_CSR             5'h1c
+`define TXTSU_TSF_CSR_FULL_OFFSET 16
+`define TXTSU_TSF_CSR_FULL 32'h00010000
+`define TXTSU_TSF_CSR_EMPTY_OFFSET 17
+`define TXTSU_TSF_CSR_EMPTY 32'h00020000
+`define TXTSU_TSF_CSR_USEDW_OFFSET 0
+`define TXTSU_TSF_CSR_USEDW 32'h000000ff