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White Rabbit core collection
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White Rabbit core collection
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19764b0d
Commit
19764b0d
authored
Feb 24, 2012
by
Tomasz Wlostowski
Committed by
Grzegorz Daniluk
Mar 11, 2019
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modules/wrsw_txtsu: updated
parent
13e46349
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2 changed files
with
4 additions
and
7 deletions
+4
-7
wrsw_txtsu_wb.vhd
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
+1
-1
xwrsw_txtsu.vhd
modules/wrsw_txtsu/xwrsw_txtsu.vhd
+3
-6
No files found.
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
View file @
19764b0d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrsw_txtsu_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_txtsu.wb
-- Created :
Wed Mar 16 15:27:30 2011
-- Created :
Tue Jan 24 21:27:39 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_txtsu.wb
...
...
modules/wrsw_txtsu/xwrsw_txtsu.vhd
View file @
19764b0d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-01-
18
-- Last update: 2012-01-
20
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -118,9 +118,6 @@ architecture syn of xwrsw_tx_tsu is
signal
state
:
t_txtsu_state
;
signal
ep_valid
:
std_logic_vector
(
g_num_ports
-1
downto
0
);
signal
ep_ack
:
std_logic_vector
(
g_num_ports
-1
downto
0
);
signal
cur_ep
:
integer
;
signal
wb_out
:
t_wishbone_slave_out
;
...
...
@@ -162,8 +159,8 @@ begin -- syn
case
state
is
when
TSU_SCAN
=>
if
(
ep_valid
(
cur_ep
)
=
'1'
)
then
ep_ack
(
cur_ep
)
<=
'1'
;
if
(
timestamps_i
(
cur_ep
)
.
valid
=
'1'
)
then
timestamps_ack_o
(
cur_ep
)
<=
'1'
;
state
<=
TSU_ACK
;
if
(
txtsu_tsf_wr_full
=
'0'
)
then
...
...
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