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Commit 19bab703 authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
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upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file;… 

upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd
parent b3178fb4
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Showing with 772 additions and 1088 deletions
board/Manifest.py
View file @ 19bab703
try:
if board in ["spec", "svec", "vfchd", "clbv2", "common"]:
if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "common"]:
modules = {"local" : [ board ] }
except NameError:
pass
board/clbv3/wr_clbv3_pkg.vhd
View file @ 19bab703
......@@ -287,6 +287,8 @@ package wr_clbv3_pkg is
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
......
syn/clbv3_ref_design/Manifest.py
View file @ 19bab703
board = "clbv3"
target = "xilinx"
action = "synthesis"
......@@ -6,8 +7,8 @@ syn_grade = "-2"
syn_package = "fbg484"
syn_top = "clbv3_wr_ref_top"
syn_project = "clbv3_wr_ref.xise"
syn_project = "clbv3_wr_ref.xpr"
syn_tool = "ise"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv3_ref_design/"}
syn/clbv3_ref_design/clbv3_wr_ref.xise.xise deleted 100644 → 0
View file @ b3178fb4
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
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<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clbv3_wr_ref_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="clbv3_wr_ref.xise" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-30T10:38:33" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8A25E8A3E6524895B535944C55324846" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/clbv3_ref_design/Manifest.py
View file @ 19bab703
......@@ -2,14 +2,13 @@ fetchto = "../../ip_cores"
files = [
"clbv3_wr_ref_top.vhd",
"clbv3_wr_ref_top.ucf",
"clbv3_wr_ref_top.xdc",
"clbv3_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv3",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
......
top/clbv3_ref_design/clbv3_wr_ref_top.bmm
View file @ 19bab703
......@@ -29,39 +29,39 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
BUS_BLOCK
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
top/clbv3_ref_design/clbv3_wr_ref_top.vhd
View file @ 19bab703
......@@ -8,7 +8,7 @@
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Last update: 2019-06-28
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the clbv3.
......@@ -54,14 +54,16 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv3_pkg.all;
--use work.gn4124_core_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv3_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy16.bram";
g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16_direct_dmtd.bram";
-- In Vivado Project-Mode, during a Synthesis run or an Implementation run, the Vivado working
-- directory temporarily changes to the "project_name/project_name.runs/run_name" directory.
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
......@@ -134,7 +136,15 @@ entity clbv3_wr_ref_top is
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
-- Reset control
reset_i : in std_logic;
suicide : out std_logic;
-- test_lemo outputs PPS
test_lemo : out std_logic;
-- Monitoring signals output on External Debug Connector J35
pps_mon : out std_logic;
ref_clk_mon : out std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
......@@ -197,35 +207,6 @@ end entity clbv3_wr_ref_top;
architecture top of clbv3_wr_ref_top is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 2;
-- Number of slaves on the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_PCIE : integer := 0;
constant c_WB_MASTER_ETHBONE : integer := 1;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00040000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"));
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
......@@ -277,12 +258,13 @@ architecture top of clbv3_wr_ref_top is
begin -- architecture top
suicide<= '1';
reset_n <= not reset_i; -- Reset = high active on CLB
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
reset_n <= not reset_i; -- Reset = high active on CLB
cmp_xwrc_board_clbv3 : xwrc_board_clbv3
generic map (
g_simulation => g_simulation,
......@@ -371,13 +353,13 @@ begin -- architecture top
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
-- Configure Digital I/Os 0 to 3 as outputs
-- Configure Digital I/Os 0 to 2 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- All DIO connectors are not terminated
dio_term_en_o <= (others => '0');
-- Configure Digital I/Os 3 to 4 inputs to be terminated.
dio_term_en_o <= "11000";
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
......@@ -406,6 +388,10 @@ begin -- architecture top
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
test_lemo <= wrc_pps_out;
pps_mon <= wrc_pps_out;
ref_clk_mon <= clk_ref_62m5;
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
......
top/clbv3_ref_design/clbv3_wr_ref_top.ucf → top/clbv3_ref_design/clbv3_wr_ref_top.xdc
View file @ 19bab703
......@@ -3,54 +3,100 @@
# ---------------------------------------------------------------------------
# -- Local oscillators
NET "clk_125m_dmtd_p_i" LOC = J19 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V -- CVPD-922-124.992 MHz PLL reference
NET "clk_125m_dmtd_n_i" LOC = H19 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V
#NET "clk_125m_dmtd_p_i" LOC = K18 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V -- FRETHE025 5x25 MHz PLL reference
#NET "clk_125m_dmtd_n_i" LOC = K19 | IOSTANDARD = "LVDS_25"; #Bank 15 VCCO - 2.5 V
NET "clk_125m_dmtd_p_i" TNM_NET = clk_125m_dmtd_p_i;
TIMESPEC TS_dmtd_clk_p_i = PERIOD "clk_125m_dmtd_p_i" 8 ns HIGH 50%;
NET "clk_125m_dmtd_n_i" TNM_NET = clk_125m_dmtd_n_i;
TIMESPEC TS_dmtd_clk_n_i = PERIOD "clk_125m_dmtd_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" LOC = F6 | IOSTANDARD = "LVDS_25"; #Bank 216 -- 125.000 MHz GTP reference
NET "clk_125m_gtp_n_i" LOC = E6 | IOSTANDARD = "LVDS_25"; #Bank 216
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
#Bank 15 VCCO - 2.5 V -- CVPD-922-124.992 MHz PLL reference
set_property PACKAGE_PIN J19 [get_ports clk_125m_dmtd_p_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_p_i]
set_property PACKAGE_PIN H19 [get_ports clk_125m_dmtd_n_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
#Bank 15 VCCO - 2.5 V -- FRETHE025 5x25 MHz PLL reference
#set_property PACKAGE_PIN K18 [get_ports clk_125m_dmtd_p_i]
#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_p_i]
#set_property PACKAGE_PIN K19 [get_ports clk_125m_dmtd_n_i]
#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_dmtd_p_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
#create_clock -period 8.000 -name clk_125m_dmtd_n_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_n_i] # AR57109: "Only P side needs constraint"
create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv3/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q]
#Bank 216 -- 125.000 MHz GTP reference
set_property PACKAGE_PIN F6 [get_ports clk_125m_gtp_p_i]
set_property PACKAGE_PIN E6 [get_ports clk_125m_gtp_n_i]
create_clock -period 8.000 -name clk_125m_gtp_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtp_p_i]
#create_clock -period 8.000 -name clk_125m_gtp_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtp_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv3/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/GT_INST/gtpe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv3/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/GT_INST/gtpe2_i/TXOUTCLK]
create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
set_clock_groups -asynchronous \
-group {clk_sys } \
-group {clk_dmtd } \
-group {clk_125m_dmtd_p_i } \
-group {clk_125m_gtp_p_i } \
-group {RXOUTCLK} \
-group {TXOUTCLK} \
-group {clk_ext_mul } \
-group {dio_clk_p_i}
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
# ---------------------------------------------------------------------------
NET "dac_dmtd_din_o" LOC = G21 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_dmtd_sclk_o" LOC = G22 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_dmtd_cs_n_o" LOC = D22 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_din_o" LOC = E21 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_sclk_o" LOC = D21 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
NET "dac_refclk_cs_n_o" LOC = B22 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN G21 [get_ports dac_dmtd_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_din_o]
set_property PACKAGE_PIN G22 [get_ports dac_dmtd_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_sclk_o]
set_property PACKAGE_PIN D22 [get_ports dac_dmtd_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_cs_n_o]
set_property PACKAGE_PIN E21 [get_ports dac_refclk_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_din_o]
set_property PACKAGE_PIN D21 [get_ports dac_refclk_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_sclk_o]
set_property PACKAGE_PIN B22 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_cs_n_o]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
NET "sfp_txp_o" LOC = B4; #Bank 216
NET "sfp_txn_o" LOC = A4; #Bank 216
NET "sfp_rxp_i" LOC = B8; #Bank 216
NET "sfp_rxn_i" LOC = A8; #Bank 216
NET "sfp_mod_def0_i" LOC = W17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sfp detect
NET "sfp_mod_def1_b" LOC = AA18 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- scl
NET "sfp_mod_def2_b" LOC = AB18 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V -- sda
NET "sfp_rate_select_o" LOC = AB20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_fault_i" LOC = R19 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_tx_disable_o" LOC = P19 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "sfp_los_i" LOC = V17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#Bank 216
set_property PACKAGE_PIN B4 [get_ports sfp_txp_o]
set_property PACKAGE_PIN A4 [get_ports sfp_txn_o]
set_property PACKAGE_PIN B8 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN A8 [get_ports sfp_rxn_i]
#Bank 14 VCCO - 3.3 V -- sfp detect
set_property PACKAGE_PIN W17 [get_ports sfp_mod_def0_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def0_i]
#Bank 14 VCCO - 3.3 V -- scl
set_property PACKAGE_PIN AA18 [get_ports sfp_mod_def1_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def1_b]
#Bank 14 VCCO - 3.3 V -- sda
set_property PACKAGE_PIN AB18 [get_ports sfp_mod_def2_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def2_b]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN AB20 [get_ports sfp_rate_select_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_rate_select_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN R19 [get_ports sfp_tx_fault_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_fault_i]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN P19 [get_ports sfp_tx_disable_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN V17 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- Onewire interface
# ---------------------------------------------------------------------------
NET "onewire_b" LOC = P16 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN P16 [get_ports onewire_b]
set_property IOSTANDARD LVCMOS33 [get_ports onewire_b]
# ---------------------------------------------------------------------------
# -- UART
......@@ -60,15 +106,32 @@ NET "onewire_b" LOC = P16 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
# Signal USB_TX is an output in the design and must be connected to pin 20/12 (RXD_I) of U26 (CP2105GM)
# Signal USB_RX is an input in the design and must be connected to pin 21/13 (TXD_O) of U26 (CP2105GM)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
NET "uart_rxd_i" LOC = W6 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 34 VCCO - 1.8 V
NET "uart_txd_o" LOC = W5 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 1.8 V
#NET "USB_RX2" LOC = U6 | IOSTANDARD = LVCMOS25 | PULLDOWN; #Bank 34 VCCO - 1.8 V
#NET "USB_TX2" LOC = V5 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 1.8 V
#Bank 34 VCCO - 1.8 V
set_property PACKAGE_PIN W6 [get_ports uart_rxd_i]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rxd_i]
set_property PULLDOWN true [get_ports uart_rxd_i]
set_property PACKAGE_PIN W5 [get_ports uart_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports uart_txd_o]
#Bank 34 VCCO - 1.8 V
#set_property PACKAGE_PIN U6 [get_ports USB_RX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX2]
#set_property PULLDOWN true [get_ports USB_RX2]
#set_property PACKAGE_PIN V5 [get_ports USB_TX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX2]
#USB Connection on Test&Debug Connector (J20)
#NET "USBEXT_RX1" LOC = D19 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX1" LOC = E19 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_RX2" LOC = F19 | IOSTANDARD = LVCMOS33 | PULLDOWN; #Bank 16 VCCO - 3.3 V
#NET "USBEXT_TX2" LOC = F20 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#Bank 16 VCCO - 3.3 V
#set_property PACKAGE_PIN D19 [get_ports USBEXT_RX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX1]
#set_property PULLDOWN true [get_ports USBEXT_RX1]
#set_property PACKAGE_PIN E19 [get_ports USBEXT_TX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX1]
#set_property PACKAGE_PIN F19 [get_ports USBEXT_RX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX2]
#set_property PULLDOWN true [get_ports USBEXT_RX2]
#set_property PACKAGE_PIN F20 [get_ports USBEXT_TX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX2]
# ---------------------------------------------------------------------------
# -- Flash memory SPI interface
......@@ -83,17 +146,41 @@ NET "uart_txd_o" LOC = W5 | IOSTANDARD = LVCMOS25;
# -- Miscellanous CLBv3 pins
# ---------------------------------------------------------------------------
#NET "GPIO_LED[0]" LOC = T20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "led_act_o" LOC = T20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[1]" LOC = W21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[2]" LOC = W22 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[3]" LOC = Y21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[4]" LOC = AA21 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "GPIO_LED[5]" LOC = AA20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "led_link_o" LOC = AA20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "reset_i" LOC = C18 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
#Bank 14 VCCO - 3.3 V
#set_property PACKAGE_PIN T20 [get_ports {GPIO_LED[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[0]}]
set_property PACKAGE_PIN T20 [get_ports led_act_o]
set_property IOSTANDARD LVCMOS33 [get_ports led_act_o]
#set_property PACKAGE_PIN W21 [get_ports {GPIO_LED[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[1]}]
#set_property PACKAGE_PIN W22 [get_ports {GPIO_LED[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[2]}]
#set_property PACKAGE_PIN Y21 [get_ports {GPIO_LED[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[3]}]
#set_property PACKAGE_PIN AA21 [get_ports {GPIO_LED[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[4]}]
#set_property PACKAGE_PIN AA20 [get_ports {GPIO_LED[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_LED[5]}]
set_property PACKAGE_PIN AA20 [get_ports led_link_o]
set_property IOSTANDARD LVCMOS33 [get_ports led_link_o]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN C18 [get_ports reset_i]
set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN AB21 [get_ports suicide]
set_property IOSTANDARD LVCMOS33 [get_ports suicide]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN B20 [get_ports test_lemo]
set_property IOSTANDARD LVCMOS33 [get_ports test_lemo]
#Bank 16 VCCO - 3.3 V Monitoring signals output on External Debug Connector J35
set_property PACKAGE_PIN F18 [get_ports pps_mon]
set_property IOSTANDARD LVCMOS33 [get_ports pps_mon]
set_property PACKAGE_PIN E18 [get_ports ref_clk_mon]
set_property IOSTANDARD LVCMOS33 [get_ports ref_clk_mon]
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
......@@ -103,179 +190,444 @@ NET "reset_i" LOC = C18 | IOSTANDARD = LVCMOS33; #Bank 16 VCCO - 3.3 V
# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
# -- external reference input.
NET "dio_clk_p_i" LOC = R4 | IOSTANDARD=LVDS_25; #CLK1_M2C_P
NET "dio_clk_n_i" LOC = T4 | IOSTANDARD=LVDS_25; #CLK1_M2C_N
#CLK1_M2C_P
set_property PACKAGE_PIN R4 [get_ports dio_clk_p_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_p_i]
#CLK1_M2C_N
set_property PACKAGE_PIN T4 [get_ports dio_clk_n_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_n_i]
# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
# -- the mezzanine front panel.
NET "dio_p_i[4]" LOC = J22 | IOSTANDARD=LVDS_25; #LA00_P
NET "dio_n_i[4]" LOC = H22 | IOSTANDARD=LVDS_25; #LA00_N
NET "dio_p_i[3]" LOC = M13 | IOSTANDARD=LVDS_25; #LA03_P
NET "dio_n_i[3]" LOC = L13 | IOSTANDARD=LVDS_25; #LA03_N
NET "dio_p_i[2]" LOC = T16 | IOSTANDARD=LVDS_25; #LA16_P
NET "dio_n_i[2]" LOC = U16 | IOSTANDARD=LVDS_25; #LA16_N
NET "dio_p_i[1]" LOC = AA10 | IOSTANDARD=LVDS_25; #LA20_P
NET "dio_n_i[1]" LOC = AA11 | IOSTANDARD=LVDS_25; #LA20_N
NET "dio_p_i[0]" LOC = R6 | IOSTANDARD=LVDS_25; #LA33_P
NET "dio_n_i[0]" LOC = T6 | IOSTANDARD=LVDS_25; #LA33_N
#LA00_P
set_property PACKAGE_PIN J22 [get_ports {dio_p_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[4]}]
#LA00_N
set_property PACKAGE_PIN H22 [get_ports {dio_n_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[4]}]
#LA03_P
set_property PACKAGE_PIN M13 [get_ports {dio_p_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[3]}]
#LA03_N
set_property PACKAGE_PIN L13 [get_ports {dio_n_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[3]}]
#LA16_P
set_property PACKAGE_PIN T16 [get_ports {dio_p_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[2]}]
#LA16_N
set_property PACKAGE_PIN U16 [get_ports {dio_n_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[2]}]
#LA20_P
set_property PACKAGE_PIN AA10 [get_ports {dio_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[1]}]
#LA20_N
set_property PACKAGE_PIN AA11 [get_ports {dio_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[1]}]
#LA33_P
set_property PACKAGE_PIN R6 [get_ports {dio_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
#LA33_N
set_property PACKAGE_PIN T6 [get_ports {dio_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
NET "dio_p_o[4]" LOC = M18 | IOSTANDARD=LVDS_25; #LA04_P
NET "dio_n_o[4]" LOC = L18 | IOSTANDARD=LVDS_25; #LA04_N
NET "dio_p_o[3]" LOC = N20 | IOSTANDARD=LVDS_25; #LA07_P
NET "dio_n_o[3]" LOC = M20 | IOSTANDARD=LVDS_25; #LA07_N
NET "dio_p_o[2]" LOC = N22 | IOSTANDARD=LVDS_25; #LA08_P
NET "dio_n_o[2]" LOC = M22 | IOSTANDARD=LVDS_25; #LA08_N
NET "dio_p_o[1]" LOC = AA9 | IOSTANDARD=LVDS_25; #LA28_P
NET "dio_n_o[1]" LOC = AB10 | IOSTANDARD=LVDS_25; #LA28_N
NET "dio_p_o[0]" LOC = W11 | IOSTANDARD=LVDS_25; #LA29_P
NET "dio_n_o[0]" LOC = W12 | IOSTANDARD=LVDS_25; #LA29_N
#LA04_P
set_property PACKAGE_PIN M18 [get_ports {dio_p_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
#LA04_N
set_property PACKAGE_PIN L18 [get_ports {dio_n_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[4]}]
#LA07_P
set_property PACKAGE_PIN N20 [get_ports {dio_p_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[3]}]
#LA07_N
set_property PACKAGE_PIN M20 [get_ports {dio_n_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[3]}]
#LA08_P
set_property PACKAGE_PIN N22 [get_ports {dio_p_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[2]}]
#LA08_N
set_property PACKAGE_PIN M22 [get_ports {dio_n_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[2]}]
#LA28_P
set_property PACKAGE_PIN AA9 [get_ports {dio_p_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[1]}]
#LA28_N
set_property PACKAGE_PIN AB10 [get_ports {dio_n_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[1]}]
#LA29_P
set_property PACKAGE_PIN W11 [get_ports {dio_p_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[0]}]
#LA29_N
set_property PACKAGE_PIN W12 [get_ports {dio_n_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[0]}]
# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
# -- panel is configured as an output.
NET "dio_oe_n_o[4]" LOC = V10 | IOSTANDARD=LVCMOS25; #LA05_P
NET "dio_oe_n_o[3]" LOC = M15 | IOSTANDARD=LVCMOS25; #LA11_P
NET "dio_oe_n_o[2]" LOC = W16 | IOSTANDARD=LVCMOS25; #LA15_N
NET "dio_oe_n_o[1]" LOC = AB13 | IOSTANDARD=LVCMOS25; #LA24_N
NET "dio_oe_n_o[0]" LOC = G17 | IOSTANDARD=LVCMOS25; #LA30_P
#LA05_P
set_property PACKAGE_PIN V10 [get_ports {dio_oe_n_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[4]}]
#LA11_P
set_property PACKAGE_PIN M15 [get_ports {dio_oe_n_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[3]}]
#LA15_N
set_property PACKAGE_PIN W16 [get_ports {dio_oe_n_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[2]}]
#LA24_N
set_property PACKAGE_PIN AB13 [get_ports {dio_oe_n_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[1]}]
#LA30_P
set_property PACKAGE_PIN G17 [get_ports {dio_oe_n_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[0]}]
# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
# -- panel is 50-ohm terminated
NET "dio_term_en_o[4]" LOC = V14 | IOSTANDARD=LVCMOS25; #LA09_N
NET "dio_term_en_o[3]" LOC = V13 | IOSTANDARD=LVCMOS25; #LA09_P
NET "dio_term_en_o[2]" LOC = W10 | IOSTANDARD=LVCMOS25; #LA05_N
NET "dio_term_en_o[1]" LOC = Y12 | IOSTANDARD=LVCMOS25; #LA06_N
NET "dio_term_en_o[0]" LOC = G18 | IOSTANDARD=LVCMOS25; #LA30_N
#LA09_N
set_property PACKAGE_PIN V14 [get_ports {dio_term_en_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[4]}]
#LA09_P
set_property PACKAGE_PIN V13 [get_ports {dio_term_en_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[3]}]
#LA05_N
set_property PACKAGE_PIN W10 [get_ports {dio_term_en_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[2]}]
#LA06_N
set_property PACKAGE_PIN Y12 [get_ports {dio_term_en_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[1]}]
#LA30_N
set_property PACKAGE_PIN G18 [get_ports {dio_term_en_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[0]}]
# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
# -- blink 1-PPS.
NET "dio_led_top_o" LOC = AB11 | IOSTANDARD=LVCMOS25; #LA01_P
NET "dio_led_bot_o" LOC = AB12 | IOSTANDARD=LVCMOS25; #LA01_N
#LA01_P
set_property PACKAGE_PIN AB11 [get_ports dio_led_top_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
#LA01_N
set_property PACKAGE_PIN AB12 [get_ports dio_led_bot_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
NET "dio_scl_b" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
NET "dio_sda_b" LOC = N17 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN P17 [get_ports dio_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_scl_b]
set_property PACKAGE_PIN N17 [get_ports dio_sda_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_sda_b]
# ---------------------------------------------------------------------------
# -- Bulls-eye connector outputs
# ---------------------------------------------------------------------------
NET "txts_p_o" LOC = H13 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 1
NET "txts_n_o" LOC = G13 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 2
NET "rxts_p_o" LOC = G15 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 3
NET "rxts_n_o" LOC = G16 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 4
NET "pps_p_o" LOC = J15 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 5
NET "pps_n_o" LOC = H15 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 6
NET "clk_ref_62m5_p_o" LOC = H17 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 7
NET "clk_ref_62m5_n_o" LOC = H18 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 8
NET "clk_dmtd_62m5_p_o" LOC = K21 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 12
NET "clk_dmtd_62m5_n_o" LOC = K22 | IOSTANDARD=LVDS_25; #Bank 15 VCCO - 2.5 V -- BullsEye 13
#Bank 15 VCCO - 2.5 V -- BullsEye 1
set_property PACKAGE_PIN H13 [get_ports txts_p_o]
set_property IOSTANDARD LVDS_25 [get_ports txts_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 2
set_property PACKAGE_PIN G13 [get_ports txts_n_o]
set_property IOSTANDARD LVDS_25 [get_ports txts_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 3
set_property PACKAGE_PIN G15 [get_ports rxts_p_o]
set_property IOSTANDARD LVDS_25 [get_ports rxts_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 4
set_property PACKAGE_PIN G16 [get_ports rxts_n_o]
set_property IOSTANDARD LVDS_25 [get_ports rxts_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 5
set_property PACKAGE_PIN J15 [get_ports pps_p_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 6
set_property PACKAGE_PIN H15 [get_ports pps_n_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 7
set_property PACKAGE_PIN H17 [get_ports clk_ref_62m5_p_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 8
set_property PACKAGE_PIN H18 [get_ports clk_ref_62m5_n_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 12
set_property PACKAGE_PIN K21 [get_ports clk_dmtd_62m5_p_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_dmtd_62m5_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 13
set_property PACKAGE_PIN K22 [get_ports clk_dmtd_62m5_n_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_dmtd_62m5_n_o]
# ---------------------------------------------------------------------------
# -- GPIO connector
# ---------------------------------------------------------------------------
#NET "GPIO[1]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[2]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[3]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[4]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[5]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[6]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[7]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[8]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[9]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[10]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[11]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[12]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[13]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[14]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[15]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#NET "GPIO[16]" LOC = | IOSTANDARD = LVCMOS??; #Bank ?? VCCO - ?.? V
#Bank ?? VCCO - ?.? V
#set_property PACKAGE_PIN ?? [get_ports {GPIO[1]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[1]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[2]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[2]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[3]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[3]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[4]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[4]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[5]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[5]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[6]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[6]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[7]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[7]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[8]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[8]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[9]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[9]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[10]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[10]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[11]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[11]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[12]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[12]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[13]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[13]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[14]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[14]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[15]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[15]}]
#set_property PACKAGE_PIN ?? [get_ports {GPIO[16]}]
#set_property IOSTANDARD LVCMOS?? [get_ports {GPIO[16]}]
#FMC SIGNALS CLK LPC
#NET "FMC_CLK0_M2C_P" LOC = T5 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK0_M2C_N" LOC = U5 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_P" LOC = R4 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_CLK1_M2C_N" LOC = T4 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA00_CC_P" LOC = J22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 1
#NET "FMC_LA00_CC_N" LOC = H22 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 3
#NET "FMC_LA01_CC_P" LOC = AB11 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 5
#NET "FMC_LA01_CC_N" LOC = AB12 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 7
#NET "FMC_LA17_CC_P" LOC = J20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 30
#NET "FMC_LA17_CC_N" LOC = J21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 32 *
#NET "FMC_LA18_CC_P" LOC = L19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 34 *
#NET "FMC_LA18_CC_N" LOC = L20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE"; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 36 *
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK0_M2C_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_P]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_P]
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK0_M2C_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK0_M2C_N]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK0_M2C_N]
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK1_M2C_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_P]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_P]
#set_property PACKAGE_PIN T5 [get_ports FMC_CLK1_M2C_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_CLK1_M2C_N]
#set_property DIFF_TERM TRUE [get_ports FMC_CLK1_M2C_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 1
#set_property PACKAGE_PIN J22 [get_ports FMC_LA00_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 3
#set_property PACKAGE_PIN H22 [get_ports FMC_LA00_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA00_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA00_CC_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 5
#set_property PACKAGE_PIN AB11 [get_ports FMC_LA01_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 7
#set_property PACKAGE_PIN AB12 [get_ports FMC_LA01_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA01_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA01_CC_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 30
#set_property PACKAGE_PIN J20 [get_ports FMC_LA17_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 32 *
#set_property PACKAGE_PIN J21 [get_ports FMC_LA17_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA17_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA17_CC_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 34 *
#set_property PACKAGE_PIN L19 [get_ports FMC_LA18_CC_P]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_P]
#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 36 *
#set_property PACKAGE_PIN L20 [get_ports FMC_LA18_CC_N]
#set_property IOSTANDARD LVDS_25 [get_ports FMC_LA18_CC_N]
#set_property DIFF_TERM TRUE [get_ports FMC_LA18_CC_N]
########################################################
#FMC SIGNALS LPC
#NET "FMC_PRSNT_B" LOC = W20 | IOSTANDARD = LVCMOS33; #Bank 14 VCCO - 3.3 V
#NET "FMC_LA02_P" LOC = K17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 9 *
#NET "FMC_LA02_N" LOC = J17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 11 *
#NET "FMC_LA03_P" LOC = M13 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 13
#NET "FMC_LA03_N" LOC = L13 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 15
#NET "FMC_LA04_P" LOC = M18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 17
#NET "FMC_LA04_N" LOC = L18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 19
#NET "FMC_LA05_P" LOC = V10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 21
#NET "FMC_LA05_N" LOC = W10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 23
#NET "FMC_LA06_P" LOC = Y11 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 25 *
#NET "FMC_LA06_N" LOC = Y12 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 27
#NET "FMC_LA07_P" LOC = N20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 29
#NET "FMC_LA07_N" LOC = M20 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 31
#NET "FMC_LA08_P" LOC = N22 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 33
#NET "FMC_LA08_N" LOC = M22 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 35
#NET "FMC_LA09_P" LOC = V13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#NET "FMC_LA09_N" LOC = V14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#NET "FMC_LA10_P" LOC = W14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 2 *
#NET "FMC_LA10_N" LOC = Y14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 4 *
#NET "FMC_LA11_P" LOC = M15 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 6
#NET "FMC_LA11_N" LOC = M16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 8 *
#NET "FMC_LA12_P" LOC = N18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 10 *
#NET "FMC_LA12_N" LOC = N19 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 12 *
#NET "FMC_LA13_P" LOC = U15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 14 *
#NET "FMC_LA13_N" LOC = V15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 16 *
#NET "FMC_LA14_P" LOC = T14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 18 *
#NET "FMC_LA14_N" LOC = T15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 20 *
#NET "FMC_LA15_P" LOC = W15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 22 *
#NET "FMC_LA15_N" LOC = W16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 24
#NET "FMC_LA16_P" LOC = T16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 26
#NET "FMC_LA16_N" LOC = U16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 28
#NET "FMC_LA19_P" LOC = Y16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 38 *
#NET "FMC_LA19_N" LOC = AA16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 40 *
#NET "FMC_LA20_P" LOC = AA10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA20_N" LOC = AA11 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_P" LOC = Y13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA21_N" LOC = AA14 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_P" LOC = AB16 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA22_N" LOC = AB17 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA23_P" LOC = K13 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA23_N" LOC = K14 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA24_P" LOC = AA13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA24_N" LOC = AB13 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_P" LOC = AA15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA25_N" LOC = AB15 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA26_P" LOC = L14 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA26_N" LOC = L15 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA27_P" LOC = L16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA27_N" LOC = K16 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA28_P" LOC = AA9 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA28_N" LOC = AB10 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_P" LOC = W11 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA29_N" LOC = W12 | IOSTANDARD = LVCMOS25; #Bank 13 VCCO - 2.5 V
#NET "FMC_LA30_P" LOC = G17 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA30_N" LOC = G18 | IOSTANDARD = LVCMOS25; #Bank 15 VCCO - 2.5 V
#NET "FMC_LA31_P" LOC = R3 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA31_N" LOC = R2 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA32_P" LOC = W2 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA32_N" LOC = Y2 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA33_P" LOC = R6 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#NET "FMC_LA33_N" LOC = T6 | IOSTANDARD = LVCMOS25; #Bank 34 VCCO - 2.5 V
#Bank 14 VCCO - 3.3 V
#set_property PACKAGE_PIN W20 [get_ports FMC_PRSNT_B]
#set_property IOSTANDARD LVCMOS33 [get_ports FMC_PRSNT_B]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 9 *
#set_property PACKAGE_PIN K17 [get_ports FMC_LA02_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 11 *
#set_property PACKAGE_PIN J17 [get_ports FMC_LA02_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA02_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 13
#set_property PACKAGE_PIN M13 [get_ports FMC_LA03_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 15
#set_property PACKAGE_PIN L13 [get_ports FMC_LA03_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA03_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 17
#set_property PACKAGE_PIN M18 [get_ports FMC_LA04_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 19
#set_property PACKAGE_PIN L18 [get_ports FMC_LA04_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA04_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 21
#set_property PACKAGE_PIN V10 [get_ports FMC_LA05_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 23
#set_property PACKAGE_PIN W10 [get_ports FMC_LA05_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA05_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 25 *
#set_property PACKAGE_PIN Y11 [get_ports FMC_LA06_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 27
#set_property PACKAGE_PIN Y12 [get_ports FMC_LA06_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA06_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 29
#set_property PACKAGE_PIN N20 [get_ports FMC_LA07_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 31
#set_property PACKAGE_PIN M20 [get_ports FMC_LA07_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA07_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 33
#set_property PACKAGE_PIN N22 [get_ports FMC_LA08_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 35
#set_property PACKAGE_PIN M22 [get_ports FMC_LA08_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA08_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
#set_property PACKAGE_PIN V13 [get_ports FMC_LA09_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
#set_property PACKAGE_PIN V14 [get_ports FMC_LA09_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA09_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 2 *
#set_property PACKAGE_PIN W14 [get_ports FMC_LA10_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 4 *
#set_property PACKAGE_PIN Y14 [get_ports FMC_LA10_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA10_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 6
#set_property PACKAGE_PIN M15 [get_ports FMC_LA11_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 8 *
#set_property PACKAGE_PIN M16 [get_ports FMC_LA11_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA11_N]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 10 *
#set_property PACKAGE_PIN N18 [get_ports FMC_LA12_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_P]
#Bank 15 VCCO - 2.5 V FMC_XM105 J1 pin 12 *
#set_property PACKAGE_PIN N19 [get_ports FMC_LA12_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA12_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 14 *
#set_property PACKAGE_PIN U15 [get_ports FMC_LA13_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 16 *
#set_property PACKAGE_PIN V15 [get_ports FMC_LA13_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA13_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 18 *
#set_property PACKAGE_PIN T14 [get_ports FMC_LA14_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 20 *
#set_property PACKAGE_PIN T15 [get_ports FMC_LA14_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA14_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 22 *
#set_property PACKAGE_PIN W15 [get_ports FMC_LA15_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 24
#set_property PACKAGE_PIN W16 [get_ports FMC_LA15_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA15_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 26
#set_property PACKAGE_PIN T16 [get_ports FMC_LA16_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 28
#set_property PACKAGE_PIN U16 [get_ports FMC_LA16_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA16_N]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 38 *
#set_property PACKAGE_PIN Y16 [get_ports FMC_LA19_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_P]
#Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 40 *
#set_property PACKAGE_PIN AA16 [get_ports FMC_LA19_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA19_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA10 [get_ports FMC_LA20_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA11 [get_ports FMC_LA20_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA20_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN Y13 [get_ports FMC_LA21_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA14 [get_ports FMC_LA21_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA21_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB16 [get_ports FMC_LA22_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB17 [get_ports FMC_LA22_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA22_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN K13 [get_ports FMC_LA23_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN K14 [get_ports FMC_LA23_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA23_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA13 [get_ports FMC_LA24_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB13 [get_ports FMC_LA24_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA24_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA15 [get_ports FMC_LA25_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB15 [get_ports FMC_LA25_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA25_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L14 [get_ports FMC_LA26_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L15 [get_ports FMC_LA26_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA26_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN L16 [get_ports FMC_LA27_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN K16 [get_ports FMC_LA27_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA27_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AA9 [get_ports FMC_LA28_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN AB10 [get_ports FMC_LA28_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA28_N]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN W11 [get_ports FMC_LA29_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_P]
#Bank 13 VCCO - 2.5 V
#set_property PACKAGE_PIN W12 [get_ports FMC_LA29_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA29_N]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN G17 [get_ports FMC_LA30_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_P]
#Bank 15 VCCO - 2.5 V
#set_property PACKAGE_PIN G18 [get_ports FMC_LA30_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA30_N]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN R3 [get_ports FMC_LA31_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_P]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN R2 [get_ports FMC_LA31_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA31_N]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN W2 [get_ports FMC_LA32_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_P]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN Y2 [get_ports FMC_LA32_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA32_N]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN R6 [get_ports FMC_LA33_P]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_P]
#Bank 34 VCCO - 2.5 V
#set_property PACKAGE_PIN T6 [get_ports FMC_LA33_N]
#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LA33_N]
#OCTOPUS SMALL
#NET "IIC1_SDA" LOC = | IOSTANDARD = LVCMOS33; #Bank ?? VCCO - ?.? V
......
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