wrcore_v2: spec_top with minibone and dpram for testing minibone

1b04440c · Grzegorz Daniluk · d472a87f · 1b04440c · 1b04440c · 1b04440c
Commit 1b04440c authored Jan 24, 2012 by Grzegorz Daniluk
5 changed files
--- a/Manifest.py
+++ b/Manifest.py
@@ -8,6 +8,7 @@ modules =  {"local" :
 												"modules/wr_softpll",
 												"modules/wr_endpoint",
 												"modules/wr_pps_gen",
+                        "modules/mini_bone",
 												"modules/wrc_core" ],
 						"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master"
 						}

--- a/modules/mini_bone/Manifest.py
+++ b/modules/mini_bone/Manifest.py
+files = ["mini_bone.vhd", "xmini_bone.vhd"];
--- a/modules/mini_bone/mini_bone.vhd
+++ b/modules/mini_bone/mini_bone.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.Wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity mini_bone is
+  generic(
+    g_class_mask    : std_logic_vector(7 downto 0) := x"ff";
+    g_our_ethertype : std_logic_vector(15 downto 0) := x"a0a0");
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    snk_cyc_i   : in  std_logic;
+    snk_stb_i   : in  std_logic;
+    snk_sel_i   : in  std_logic_vector(1 downto 0);
+    snk_adr_i   : in  std_logic_vector(1 downto 0);
+    snk_dat_i   : in  std_logic_vector(15 downto 0);
+    snk_we_i    : in  std_logic;
+    snk_stall_o : out std_logic;
+    snk_ack_o   : out std_logic;
+    snk_err_o   : out std_logic;
+
+    src_cyc_o   : out std_logic;
+    src_stb_o   : out std_logic;
+    src_dat_o   : out std_logic_vector(15 downto 0);
+    src_adr_o   : out std_logic_vector(1 downto 0);
+    src_we_o    : out std_logic;
+    src_ack_i   : in  std_logic;
+    src_err_i   : in  std_logic;
+    src_sel_o   : out std_logic_vector(1 downto 0);
+    src_stall_i : in  std_logic;
+
+    master_cyc_o : out std_logic;
+    master_we_o  : out std_logic;
+    master_stb_o : out std_logic;
+    master_sel_o : out std_logic_vector(3 downto 0);
+    master_adr_o : out std_logic_vector(31 downto 0);
+    master_dat_o : out std_logic_vector(31 downto 0);
+    master_dat_i : in  std_logic_vector(31 downto 0);
+    master_ack_i : in  std_logic
+    );
+
+end mini_bone;
+
+
+architecture wrapper of mini_bone is
+
+  component xmini_bone
+    generic (
+      g_class_mask    : std_logic_vector(7 downto 0);
+      g_our_ethertype : std_logic_vector(15 downto 0));
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      src_o     : out t_wrf_source_out;
+      src_i     : in  t_wrf_source_in;
+      snk_o     : out t_wrf_sink_out;
+      snk_i     : in  t_wrf_sink_in;
+      master_o  : out t_wishbone_master_out;
+      master_i  : in  t_wishbone_master_in);
+  end component;
+
+
+  signal src_out    : t_wrf_source_out;
+  signal src_in     : t_wrf_source_in;
+  signal snk_out    : t_wrf_sink_out;
+  signal snk_in     : t_wrf_sink_in;
+  signal master_out : t_wishbone_master_out;
+  signal master_in  : t_wishbone_master_in;
+
+begin  -- wrapper
+
+  U_Wrapped_MB : xmini_bone
+    generic map (
+      g_class_mask    => g_class_mask,
+      g_our_ethertype => g_our_ethertype)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      src_o     => src_out,
+      src_i     => src_in,
+      snk_o     => snk_out,
+      snk_i     => snk_in,
+      master_o  => master_out,
+      master_i  => master_in);
+
+  src_cyc_o <= src_out.cyc;
+  src_stb_o <= src_out.stb;
+  src_we_o  <= src_out.we;
+  src_adr_o <= src_out.adr;
+  src_dat_o <= src_out.dat;
+  src_sel_o <= src_out.sel;
+
+  src_in.ack   <= src_ack_i;
+  src_in.stall <= src_stall_i;
+
+
+  snk_in.cyc <= snk_cyc_i;
+  snk_in.stb <= snk_stb_i;
+  snk_in.we  <= snk_we_i;
+  snk_in.sel <= snk_sel_i;
+  snk_in.adr <= snk_adr_i;
+  snk_in.dat <= snk_dat_i;
+
+  snk_ack_o   <= snk_out.ack;
+  snk_stall_o <= snk_out.stall;
+
+  master_cyc_o <= master_out.cyc;
+  master_stb_o <= master_out.stb;
+  master_we_o  <= master_out.we;
+  master_sel_o <= master_out.sel;
+  master_adr_o <= master_out.adr;
+  master_dat_o <= master_out.dat;
+
+  master_in.dat <= master_dat_i;
+  master_in.ack <= master_ack_i;
+  
+end wrapper;
--- a/modules/mini_bone/xmini_bone.vhd
+++ b/modules/mini_bone/xmini_bone.vhd
--- a/top/spec_1_1/wr_core_demo/spec_top.vhd
+++ b/top/spec_1_1/wr_core_demo/spec_top.vhd
@@ -7,7 +7,6 @@ use work.gn4124_core_pkg.all;
 use work.gencores_pkg.all;
 use work.wrcore_pkg.all;
 use work.wr_fabric_pkg.all;
--use work.wbconmax_pkg.all;

 library UNISIM;
 use UNISIM.vcomponents.all;
@@ -475,6 +474,31 @@ architecture rtl of spec_top is
  signal wrc_slave_o : t_wishbone_slave_out;

  signal wb_adr : std_logic_vector(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
+
+  component xmini_bone
+    generic (
+      g_class_mask    : std_logic_vector(7 downto 0);
+      g_our_ethertype : std_logic_vector(15 downto 0));
+    port (
+      clk_sys_i : in  std_logic;
+      rst_n_i   : in  std_logic;
+      src_o     : out t_wrf_source_out;
+      src_i     : in  t_wrf_source_in;
+      snk_o     : out t_wrf_sink_out;
+      snk_i     : in  t_wrf_sink_in;
+      master_o  : out t_wishbone_master_out;
+      master_i  : in  t_wishbone_master_in);
+  end component;
+
+  signal mbone_rst_n     : std_logic;
+  signal mbone_src_out   : t_wrf_source_out;
+  signal mbone_src_in    : t_wrf_source_in;
+  signal mbone_snk_out   : t_wrf_sink_out;
+  signal mbone_snk_in    : t_wrf_sink_in;
+  signal mbone_wb_out    : t_wishbone_master_out;
+  signal mbone_wb_in     : t_wishbone_master_in;
+  signal dpram_slave2_in : t_wishbone_master_out;
+
 begin

  cmp_sys_clk_pll : PLL_BASE
@@ -771,6 +795,11 @@ begin
      slave_i => wrc_slave_i,
      slave_o => wrc_slave_o,

+      wrf_src_o => mbone_snk_in,
+      wrf_src_i => mbone_snk_out,
+      wrf_snk_o => mbone_src_in,
+      wrf_snk_i => mbone_src_out,
+
      tm_dac_value_o       => open,
      tm_dac_wr_o          => open,
      tm_clk_aux_lock_en_i => '0',
@@ -781,10 +810,48 @@ begin
      pps_p_o              => pps,

      dio_o       => dio_out(4 downto 1),
-      rst_aux_n_o => open
+      rst_aux_n_o => mbone_rst_n
    );


+  -- Mini-BONE
+  U_MiniBone : xmini_bone
+    generic map (
+      g_class_mask    => x"f0",
+      g_our_ethertype => x"a0a0")
+    port map (
+      clk_sys_i => clk_sys,
+      rst_n_i   => mbone_rst_n,
+      src_o     => mbone_src_out,
+      src_i     => mbone_src_in,
+      snk_o     => mbone_snk_out,
+      snk_i     => mbone_snk_in,
+      master_o  => mbone_wb_out,
+      master_i  => mbone_wb_in);
+
+  U_DPRAM : xwb_dpram
+    generic map (
+      g_size                  => 2048,
+      g_init_file             => "",
+      g_must_have_init_file   => false,
+      g_slave1_interface_mode => CLASSIC,
+      g_slave2_interface_mode => CLASSIC,
+      g_slave1_granularity    => WORD,
+      g_slave2_granularity    => WORD)
+    port map (
+      clk_sys_i => clk_sys,
+      rst_n_i   => mbone_rst_n,
+      slave1_i  => mbone_wb_out,
+      slave1_o  => mbone_wb_in,
+      slave2_i  => dpram_slave2_in,
+      slave2_o  => open);
+
+  dpram_slave2_in.cyc <= '0';
+  dpram_slave2_in.stb <= '0';
+
+  ---------------------
+  ---------------------
+
  U_GTP : wr_gtp_phy_spartan6
    generic map (
      g_simulation => 0)