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White Rabbit core collection
Commit 1b373238 authored by Stefan Rauch's avatar Stefan Rauch Committed by Wesley W. Terpstra
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Massive reorginizaion of GSI project files. 

  * Added the new SCU2 target (different pinouts and components)
  * Moved common components (uart) to modules
  * Moved the common spec and SCU DAC files into modules
  * Added the DDR3 controller for Altera
  * Removed a few superfluous files from version control
parent 0d0ee9b1
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Manifest.py
View file @ 1b373238
......@@ -9,6 +9,7 @@ modules = {"local" :
"modules/wr_softpll_ng",
"modules/wr_endpoint",
"modules/wr_pps_gen",
"modules/wr_dacs",
"modules/wrc_core" ],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"
}
modules/lpc_uart/Manifest.py 0 → 100644
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files = [
"lpc_peripheral.vhd",
"lpc_uart.vhd",
"postcode.vhd",
"serirq_defines.v",
"serirq_slave.v"
]
modules/uart/Manifest.py 0 → 100644
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files = [
"slib_clock_div.vhd",
"slib_counter.vhd",
"slib_edge_detect.vhd",
"slib_fifo_cyclone2.vhd",
"slib_fifo.vhd",
"slib_input_filter.vhd",
"slib_input_sync.vhd",
"slib_mv_filter.vhd",
"uart_16750.vhd",
"uart_baudgen.vhd",
"uart_interrupt.vhd",
"uart_receiver.vhd",
"uart_transmitter.vhd"
]
modules/wr_dacs/Manifest.py 0 → 100644
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files = [
"spec_serial_dac_arb.vhd",
"spec_serial_dac.vhd"
]
platform/altera/ddr3/Micron MT41J64M16LA-15E.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<preset name="Micron MT41J64M16LA-15E">
<parameter name="mem_if_memtype" value="DDR3 SDRAM" />
<parameter name="vendor" value="Micron" />
<parameter name="chip_or_dimm" value="Discrete Device" />
<parameter name="mem_fmax" value="666.666" />
<parameter name="mem_if_coladdr_width" value="10" />
<parameter name="mem_if_rowaddr_width" value="13" />
<parameter name="mem_if_bankaddr_width" value="3" />
<parameter name="mem_if_clk_pair_count" value="1" />
<parameter name="mem_if_cs_per_dimm" value="1" />
<parameter name="mem_if_cs_per_rank" value="1" />
<parameter name="mem_if_cs_width" value="1" />
<parameter name="mirror_addressing" value="0" />
<parameter name="register_control_word_size" value="4" />
<parameter name="register_control_word_0" value="0000" />
<parameter name="register_control_word_1" value="0000" />
<parameter name="register_control_word_2" value="0000" />
<parameter name="register_control_word_3" value="0000" />
<parameter name="register_control_word_4" value="0000" />
<parameter name="register_control_word_5" value="0000" />
<parameter name="register_control_word_6" value="0000" />
<parameter name="register_control_word_7" value="0000" />
<parameter name="register_control_word_8" value="0000" />
<parameter name="register_control_word_9" value="0000" />
<parameter name="register_control_word_10" value="0000" />
<parameter name="register_control_word_11" value="0000" />
<parameter name="register_control_word_12" value="0000" />
<parameter name="register_control_word_13" value="0000" />
<parameter name="register_control_word_14" value="0000" />
<parameter name="register_control_word_15" value="0000" />
<parameter name="mem_if_dq_per_dqs" value="8" />
<parameter name="mem_if_dwidth" value="8" />
<parameter name="mem_if_dm_pins_en" value="Yes" />
<parameter name="mem_if_tinit_us" value="500.0" />
<parameter name="dss_tinit_rst_us" value="200.0" />
<parameter name="mem_if_tmrd_ns" value="6.0" />
<parameter name="mem_if_tras_ns" value="36.0" />
<parameter name="mem_if_trcd_ns" value="13.5" />
<parameter name="mem_if_trp_ns" value="13.5" />
<parameter name="mem_if_trefi_us" value="7.8" />
<parameter name="mem_if_trfc_ns" value="110.0" />
<parameter name="mem_if_twr_ns" value="15.0" />
<parameter name="mem_if_twtr_ck" value="4" />
<parameter name="mem_tdqsck_ps" value="255" />
<parameter name="mem_tdqsq_ps" value="125" />
<parameter name="mem_tdqss_ck" value="0.25" />
<parameter name="mem_tdha_ps" value="165" />
<parameter name="mem_tdsa_ps" value="180" />
<parameter name="mem_tdsh_ck" value="0.2" />
<parameter name="mem_tdss_ck" value="0.2" />
<parameter name="mem_tiha_ps" value="240" />
<parameter name="mem_tisa_ps" value="340" />
<parameter name="mem_tqh_ck" value="0.38" />
<parameter name="mem_tfaw_ns" value="30.0" />
<parameter name="mem_trrd_ns" value="6.0" />
<parameter name="mem_trtp_ns" value="7.5" />
<parameter name="mem_bl" value="On the fly" />
<parameter name="mem_btype" value="Sequential" />
<parameter name="mem_dll_pch" value="Fast exit" />
<parameter name="mem_dll_en" value="Yes" />
<parameter name="mem_rtt_nom" value="ODT Disabled" />
<parameter name="mem_rtt_wr" value="Dynamic ODT off" />
<parameter name="mem_drv_impedance" value="RZQ/7" />
<parameter name="mem_tcl" value="9.0" />
<parameter name="mem_atcl" value="Disabled" />
<parameter name="mem_wtcl" value="7.0" />
<parameter name="mem_pasr" value="Full Array" />
<parameter name="mem_asrm" value="Manual SR Reference (SRT)" />
<parameter name="mem_srtr" value="Normal" />
<parameter name="mem_tcl_50_fmax" value="333.333" />
<parameter name="mem_tcl_60_fmax" value="400.0" />
<parameter name="mem_tcl_70_fmax" value="533.333" />
<parameter name="mem_tcl_80_fmax" value="533.333" />
<parameter name="mem_tcl_90_fmax" value="666.666" />
<parameter name="mem_tcl_100_fmax" value="666.666" />
</preset>
platform/altera/ddr3/alt_mem_ddrx_addr_cmd.v 0 → 100644
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platform/altera/ddr3/alt_mem_ddrx_buffer.v 0 → 100644
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module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
platform/altera/ddr3/alt_mem_ddrx_buffer_manager.v 0 → 100644
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module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
platform/altera/ddr3/alt_mem_ddrx_burst_gen.v 0 → 100644
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platform/altera/ddr3/alt_mem_ddrx_burst_tracking.v 0 → 100644
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//altera message_off 10230
module alt_mem_ddrx_burst_tracking
# (
// module parameter port list
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
// port list
ctl_clk,
ctl_reset_n,
// data burst interface
burst_ready,
burst_valid,
// burstcount counter sent to data_id_manager
burst_pending_burstcount,
burst_next_pending_burstcount,
// burstcount consumed by data_id_manager
burst_consumed_valid,
burst_counsumed_burstcount
);
// -----------------------------
// local parameter declarations
// -----------------------------
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// data burst interface
input burst_ready;
input burst_valid;
// burstcount counter sent to data_id_manager
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
// burstcount consumed by data_id_manager
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// data burst interface
wire burst_ready;
wire burst_valid;
// burstcount counter sent to data_id_manager
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
//wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_count_accepted;
// burstcount consumed by data_id_manager
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// signal declaration
// -----------------------------
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
// -----------------------------
// module definition
// -----------------------------
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule
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//--------------------------------------------------------------------------------------------------------
//
// [START] MMR - Memory Mapped Register Definition
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Generic Signals
//----------------------------------------------------------------------------------------------------
// cfg_type
`define MMR_TYPE_DDR1 3'b000
`define MMR_TYPE_DDR2 3'b001
`define MMR_TYPE_DDR3 3'b010
`define MMR_TYPE_LPDDR1 3'b011
`define MMR_TYPE_LPDDR2 3'b100
//----------------------------------------------------------------------------------------------------
// Address Mapping Signals
//----------------------------------------------------------------------------------------------------
// cfg_addr_order
`define MMR_ADDR_ORDER_CS_ROW_BA_COL 2'b00
`define MMR_ADDR_ORDER_CS_BA_ROW_COL 2'b01
`define MMR_ADDR_ORDER_ROW_CS_BA_COL 2'b10
//--------------------------------------------------------------------------------------------------------
//
// [END] MMR - Memory Mapped Register Definition
//
//--------------------------------------------------------------------------------------------------------
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set_false_path -from * -to [get_ports "pnf"]
set_false_path -from * -to [get_ports "test_complete"]
set_false_path -from * -to [get_ports "pnf_per_byte\[*\]"]
set_false_path -from * -to [get_ports "mem_reset_n"]
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