Commit 1b809998 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski

wr_streamers: added timeout feature to fixed_latency_ts_match

parent 39aedf14
......@@ -19,6 +19,7 @@ entity fixed_latency_ts_match is
ts_tai_i : in std_logic_vector(39 downto 0);
ts_cycles_i : in std_logic_vector(27 downto 0);
ts_latency_i : in std_logic_vector(27 downto 0);
ts_timeout_i : in std_logic_vector(27 downto 0);
-- Time valid flag
tm_time_valid_i : in std_logic := '0';
......@@ -29,9 +30,9 @@ entity fixed_latency_ts_match is
-- Fractional part of the second (in clk_ref_i cycles)
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
match_o : out std_logic;
late_o : out std_logic
late_o : out std_logic;
timeout_o : out std_logic
);
......@@ -58,27 +59,36 @@ architecture rtl of fixed_latency_ts_match is
signal ts_adjusted_cycles : unsigned(28 downto 0);
signal ts_adjusted_tai : unsigned(39 downto 0);
signal ts_timeout_cycles : unsigned(28 downto 0);
signal ts_timeout_tai : unsigned(39 downto 0);
signal tm_cycles_scaled : unsigned(28 downto 0);
signal ts_latency_scaled : unsigned(28 downto 0);
signal ts_timeout_scaled : unsigned(28 downto 0);
signal tm_cycles_scaled_d : unsigned(28 downto 0);
signal ts_latency_scaled_d : unsigned(28 downto 0);
signal ts_adjusted_d : unsigned(28 downto 0);
signal tm_cycles_scaled_d : unsigned(28 downto 0);
signal tm_tai_d : unsigned(39 downto 0);
signal match, late : std_logic;
signal match, late, timeout : std_logic;
signal state : t_state;
signal trig : std_logic;
signal ts_adj_next_cycle, roll_lo, roll_hi : std_logic;
signal wait_cnt : unsigned(23 downto 0);
attribute mark_debug : string;
attribute mark_debug of ts_adjusted_d : signal is "TRUE";
attribute mark_debug of tm_cycles_scaled_d : signal is "TRUE";
attribute mark_debug of ts_latency_scaled_d : signal is "TRUE";
attribute mark_debug of state : signal is "TRUE";
attribute mark_debug of match : signal is "TRUE";
attribute mark_debug of late : signal is "TRUE";
attribute mark_debug of ts_adjusted_cycles : signal is "TRUE";
attribute mark_debug of ts_adjusted_tai : signal is "TRUE";
attribute mark_debug of ts_timeout_cycles : signal is "TRUE";
attribute mark_debug of ts_timeout_tai : signal is "TRUE";
attribute mark_debug of tm_cycles_scaled_d : signal is "TRUE";
attribute mark_debug of tm_tai_d : signal is "TRUE";
attribute mark_debug of state : signal is "TRUE";
attribute mark_debug of match : signal is "TRUE";
attribute mark_debug of late : signal is "TRUE";
attribute mark_debug of timeout : signal is "TRUE";
attribute mark_debug of trig : signal is "TRUE";
begin
......@@ -86,14 +96,13 @@ begin
process(clk_i)
begin
if rising_edge(clk_i) then
ts_adjusted_d <= ts_adjusted_cycles;
tm_cycles_scaled_d <= tm_cycles_scaled;
ts_latency_scaled_d <= ts_latency_scaled;
tm_cycles_scaled_d <= tm_cycles_scaled;
tm_tai_d <= unsigned(tm_tai_i);
end if;
end process;
process(tm_cycles_i, ts_latency_i)
process(tm_cycles_i, ts_latency_i, ts_timeout_i)
begin
if g_clk_ref_rate = 62500000 then
tm_cycles_scaled <= unsigned(tm_cycles_i & '0');
......@@ -107,6 +116,32 @@ begin
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wait_cnt <= (others => '0');
trig <= '0';
else
case State is
when IDLE =>
wait_cnt <= (others => '0');
trig <= '0';
when others =>
wait_cnt <= wait_cnt + 1;
if wait_cnt = 3000 then
trig <= '1';
end if;
end case;
end if;
end if;
end process;
process(clk_i)
begin
......@@ -122,11 +157,16 @@ begin
when IDLE =>
match <= '0';
late <= '0';
timeout <= '0';
if arm_i = '1' then
ts_adjusted_cycles <= resize(unsigned(ts_cycles_i) + unsigned(ts_latency_i), 29);
ts_adjusted_cycles <= resize(unsigned(ts_cycles_i) + unsigned(ts_latency_scaled), 29);
ts_adjusted_tai <= resize(unsigned(ts_tai_i), 40);
State <= WRAP_ADJ_TS;
ts_timeout_cycles <= resize(unsigned(ts_cycles_i) + unsigned(ts_timeout_scaled), 29);
ts_timeout_tai <= resize(unsigned(ts_tai_i), 40);
State <= WRAP_ADJ_TS;
end if;
when WRAP_ADJ_TS =>
......@@ -137,6 +177,11 @@ begin
ts_adjusted_tai <= ts_adjusted_tai + 1;
end if;
if ts_timeout_cycles >= f_cycles_counter_range then
ts_timeout_cycles <= ts_timeout_cycles - f_cycles_counter_range;
ts_timeout_tai <= ts_timeout_tai + 1;
end if;
State <= CHECK_LATE;
when CHECK_LATE =>
......@@ -147,10 +192,10 @@ begin
end if;
if ts_adjusted_tai < unsigned(tm_tai_i) then
if ts_adjusted_tai < tm_tai_d then
late <= '1';
State <= IDLE;
elsif ts_adjusted_tai = unsigned(tm_tai_i) and ts_adjusted_cycles <= tm_cycles_scaled then
elsif ts_adjusted_tai = tm_tai_d and ts_adjusted_cycles <= tm_cycles_scaled_d then
late <= '1';
State <= IDLE;
else
......@@ -158,7 +203,15 @@ begin
end if;
when WAIT_TRIG =>
if ts_adjusted_cycles = tm_cycles_scaled and ts_adjusted_tai = unsigned(tm_tai_i) then
if tm_tai_d > ts_timeout_tai or
(ts_timeout_tai = tm_tai_d and tm_cycles_scaled_d > ts_timeout_cycles) then
timeout <= '1';
State <= IDLE;
end if;
if ts_adjusted_cycles = tm_cycles_scaled_d and ts_adjusted_tai = tm_tai_d then
match <= '1';
State <= IDLE;
end if;
......@@ -170,5 +223,6 @@ begin
match_o <= match;
late_o <= late;
timeout_o <= timeout;
end rtl;
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