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W
White Rabbit core collection
Commit 2291d6ee authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wishbonized: little cleanup

parent 3151840a
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Showing with 28 additions and 25 deletions
Manifest.py
View file @ 2291d6ee
...@@ -12,6 +12,3 @@ modules = {"local" : ...@@ -12,6 +12,3 @@ modules = {"local" :
"modules/wrc_core" ], "modules/wrc_core" ],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::wishbone_with_adapter" "git" : "git://ohwr.org/hdl-core-lib/general-cores.git::wishbone_with_adapter"
} }
\ No newline at end of file
modules/wrc_core/wr_core.vhd
View file @ 2291d6ee
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk -- Author : Grzegorz Daniluk
-- Company : Elproma -- Company : Elproma
-- Created : 2011-02-02 -- Created : 2011-02-02
-- Last update: 2011-11-09 -- Last update: 2011-12-09
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 2291d6ee
...@@ -309,7 +309,11 @@ architecture rtl of spec_top is ...@@ -309,7 +309,11 @@ architecture rtl of spec_top is
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
rst_aux_n_o : out std_logic; rst_aux_n_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0)); dio_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic
);
end component; end component;
component wr_gtp_phy_spartan6 component wr_gtp_phy_spartan6
...@@ -824,10 +828,12 @@ begin ...@@ -824,10 +828,12 @@ begin
ext_src_we_o => mbone_snk_in.we, ext_src_we_o => mbone_snk_in.we,
ext_src_ack_i => mbone_snk_out.ack, ext_src_ack_i => mbone_snk_out.ack,
ext_src_err_i => mbone_snk_out.err, ext_src_err_i => mbone_snk_out.err,
ext_src_stall_i => mbone_snk_out.stall ext_src_stall_i => mbone_snk_out.stall,
owr_i => '0'
); );
U_MiniBone: xmini_bone U_MiniBone : xmini_bone
generic map ( generic map (
g_class_mask => x"f0", g_class_mask => x"f0",
g_our_ethertype => x"a0a0") g_our_ethertype => x"a0a0")
...@@ -844,7 +850,7 @@ begin ...@@ -844,7 +850,7 @@ begin
U_DPRAM: xwb_dpram U_DPRAM : xwb_dpram
generic map ( generic map (
g_size => 2048, g_size => 2048,
g_init_file => "", g_init_file => "",
......
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