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White Rabbit core collection
Commit 230ab94b authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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ext pll: for spartan use clk_in stopped indicator and reset signal

parent 68838142
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Showing with 94 additions and 25 deletions
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ 230ab94b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Aug 6 16:05:11 2015
-- Created : Thu Dec 3 18:39:19 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -43,6 +43,7 @@ end spll_wb_slave;
architecture syn of spll_wb_slave is
signal spll_eccr_ext_en_int : std_logic ;
signal spll_eccr_ext_ref_pllrst_int : std_logic ;
signal spll_occr_out_lock_int : std_logic_vector(7 downto 0);
signal spll_deglitch_thr_int : std_logic_vector(15 downto 0);
signal spll_dfr_host_rst_n : std_logic ;
......@@ -97,6 +98,7 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
spll_eccr_ext_en_int <= '0';
spll_eccr_ext_ref_pllrst_int <= '0';
regs_o.al_cr_valid_load_o <= '0';
regs_o.f_dmtd_valid_load_o <= '0';
regs_o.f_ref_valid_load_o <= '0';
......@@ -180,11 +182,13 @@ begin
when "000001" =>
if (wb_we_i = '1') then
spll_eccr_ext_en_int <= wrdata_reg(0);
spll_eccr_ext_ref_pllrst_int <= wrdata_reg(31);
end if;
rddata_reg(0) <= spll_eccr_ext_en_int;
rddata_reg(1) <= regs_i.eccr_ext_supported_i;
rddata_reg(2) <= regs_i.eccr_ext_ref_present_i;
rddata_reg(3) <= 'X';
rddata_reg(2) <= regs_i.eccr_ext_ref_locked_i;
rddata_reg(3) <= regs_i.eccr_ext_ref_stopped_i;
rddata_reg(31) <= spll_eccr_ext_ref_pllrst_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -212,7 +216,6 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
......@@ -760,6 +763,9 @@ begin
regs_o.eccr_ext_en_o <= spll_eccr_ext_en_int;
-- External Clock Input Available
-- External Clock Reference Present
-- EXT_REF_STOPPED
-- EXT_PLL_RST
regs_o.eccr_ext_ref_pllrst_o <= spll_eccr_ext_ref_pllrst_int;
-- Aligner sample valid/select on channel
regs_o.al_cr_valid_o <= wrdata_reg(8 downto 0);
-- Aligner required on channel
......
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ 230ab94b
......@@ -77,11 +77,29 @@ peripheral {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
prefix = "EXT_REF_LOCKED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "EXT_REF_STOPPED";
description = "1: Reference 10MHz clock unplugged";
prefix = "EXT_REF_STOPPED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "EXT_PLL_RST";
prefix = "EXT_REF_PLLRST";
align = 31;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ 230ab94b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Aug 6 16:05:11 2015
-- Created : Thu Dec 3 18:39:19 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -25,7 +25,8 @@ package spll_wbgen2_pkg is
csr_n_out_i : std_logic_vector(2 downto 0);
csr_dbg_supported_i : std_logic;
eccr_ext_supported_i : std_logic;
eccr_ext_ref_present_i : std_logic;
eccr_ext_ref_locked_i : std_logic;
eccr_ext_ref_stopped_i : std_logic;
al_cr_valid_i : std_logic_vector(8 downto 0);
al_cr_required_i : std_logic_vector(8 downto 0);
al_cref_i : std_logic_vector(31 downto 0);
......@@ -53,7 +54,8 @@ package spll_wbgen2_pkg is
csr_n_out_i => (others => '0'),
csr_dbg_supported_i => '0',
eccr_ext_supported_i => '0',
eccr_ext_ref_present_i => '0',
eccr_ext_ref_locked_i => '0',
eccr_ext_ref_stopped_i => '0',
al_cr_valid_i => (others => '0'),
al_cr_required_i => (others => '0'),
al_cref_i => (others => '0'),
......@@ -80,6 +82,7 @@ package spll_wbgen2_pkg is
type t_spll_out_registers is record
eccr_ext_en_o : std_logic;
eccr_ext_ref_pllrst_o : std_logic;
al_cr_valid_o : std_logic_vector(8 downto 0);
al_cr_valid_load_o : std_logic;
f_dmtd_valid_o : std_logic;
......@@ -113,6 +116,7 @@ package spll_wbgen2_pkg is
constant c_spll_out_registers_init_value: t_spll_out_registers := (
eccr_ext_en_o => '0',
eccr_ext_ref_pllrst_o => '0',
al_cr_valid_o => (others => '0'),
al_cr_valid_load_o => '0',
f_dmtd_valid_o => '0',
......@@ -176,7 +180,8 @@ tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_
tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i);
tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
tmp.eccr_ext_ref_present_i := f_x_to_zero(left.eccr_ext_ref_present_i) or f_x_to_zero(right.eccr_ext_ref_present_i);
tmp.eccr_ext_ref_locked_i := f_x_to_zero(left.eccr_ext_ref_locked_i) or f_x_to_zero(right.eccr_ext_ref_locked_i);
tmp.eccr_ext_ref_stopped_i := f_x_to_zero(left.eccr_ext_ref_stopped_i) or f_x_to_zero(right.eccr_ext_ref_stopped_i);
tmp.al_cr_valid_i := f_x_to_zero(left.al_cr_valid_i) or f_x_to_zero(right.al_cr_valid_i);
tmp.al_cr_required_i := f_x_to_zero(left.al_cr_required_i) or f_x_to_zero(right.al_cr_required_i);
tmp.al_cref_i := f_x_to_zero(left.al_cref_i) or f_x_to_zero(right.al_cref_i);
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ 230ab94b
......@@ -112,6 +112,8 @@ entity wr_softpll_ng is
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
-- External clock sync/alignment singnal. SoftPLL will align clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
......@@ -525,7 +527,9 @@ begin -- rtl
);
regs_out.eccr_ext_supported_i <= '1';
regs_out.eccr_ext_ref_present_i <= clk_ext_mul_locked_i;
regs_out.eccr_ext_ref_locked_i <= clk_ext_mul_locked_i;
regs_out.eccr_ext_ref_stopped_i <= clk_ext_stopped_i;
clk_ext_rst_o <= regs_in.eccr_ext_ref_pllrst_o;
end generate gen_with_ext_clock_input;
aligner_sample_valid(g_num_outputs-1 downto 0) <= (others => '0');
......@@ -533,6 +537,9 @@ begin -- rtl
gen_without_ext_clock_input : if(not g_with_ext_clock_input) generate
tags_p(g_num_ref_inputs + g_num_outputs) <= '0';
regs_out.eccr_ext_supported_i <= '0';
regs_out.eccr_ext_ref_locked_i <= '0';
regs_out.eccr_ext_ref_stopped_i <= '0';
clk_ext_rst_o <= '0';
end generate gen_without_ext_clock_input;
p_ack_aligner_samples: process(regs_in, aligner_sample_valid)
......
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ 230ab94b
......@@ -101,6 +101,8 @@ entity xwr_softpll_ng is
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
......@@ -153,7 +155,9 @@ architecture wrapper of xwr_softpll_ng is
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_stopped_i : in std_logic;
clk_ext_rst_o : out std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -204,6 +208,8 @@ begin -- behavioral
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_stopped_i => clk_ext_stopped_i,
clk_ext_rst_o => clk_ext_rst_o,
pps_csync_p1_i => pps_csync_p1_i,
pps_ext_a_i => pps_ext_a_i,
dac_dmtd_data_o => dac_dmtd_data_o,
......
modules/wrc_core/wr_core.vhd
View file @ 230ab94b
......@@ -117,6 +117,8 @@ entity wr_core is
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
-- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
clk_ext_i : in std_logic := '0';
......@@ -556,6 +558,8 @@ begin
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_stopped_i => clk_ext_stopped_i,
clk_ext_rst_o => clk_ext_rst_o,
pps_csync_p1_i => s_pps_csync,
pps_ext_a_i => pps_ext_i,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 230ab94b
......@@ -271,6 +271,8 @@ package wrcore_pkg is
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_stopped_i : in std_logic;
clk_ext_rst_o : out std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -318,6 +320,8 @@ package wrcore_pkg is
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
......@@ -448,7 +452,9 @@ package wrcore_pkg is
clk_ext_i : in std_logic := '0';
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i : in std_logic := '0';
......
modules/wrc_core/xwr_core.vhd
View file @ 230ab94b
......@@ -104,6 +104,8 @@ entity xwr_core is
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
-- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
pps_ext_i : in std_logic := '0';
......@@ -261,6 +263,8 @@ begin
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_stopped_i => clk_ext_stopped_i,
clk_ext_rst_o => clk_ext_rst_o,
pps_ext_i => pps_ext_i,
rst_n_i => rst_n_i,
......
platform/xilinx/ext_pll_10_to_125m.vhd
View file @ 230ab94b
......@@ -79,13 +79,14 @@ port
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
clk_in_stopped_o : out std_logic;
locked_o : out std_logic
);
end ext_pll_10_to_125m;
architecture xilinx of ext_pll_10_to_125m is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_125m,clk_wiz_v3_6,{component_name=ext_pll_10_to_125m,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=100.0,clkin2_period=100.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
......@@ -117,7 +118,7 @@ begin
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 100.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
......@@ -147,14 +148,17 @@ begin
-- Unused pin, tie low
DSSEN => '0');
clk_in_stopped_o <= status_internal(1);
locked_o <= locked_internal;
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
......
sim/softpll_regs_ng.vh
View file @ 230ab94b
......@@ -12,8 +12,12 @@
`define SPLL_ECCR_EXT_EN 32'h00000001
`define SPLL_ECCR_EXT_SUPPORTED_OFFSET 1
`define SPLL_ECCR_EXT_SUPPORTED 32'h00000002
`define SPLL_ECCR_EXT_REF_PRESENT_OFFSET 2
`define SPLL_ECCR_EXT_REF_PRESENT 32'h00000004
`define SPLL_ECCR_EXT_REF_LOCKED_OFFSET 2
`define SPLL_ECCR_EXT_REF_LOCKED 32'h00000004
`define SPLL_ECCR_EXT_REF_STOPPED_OFFSET 3
`define SPLL_ECCR_EXT_REF_STOPPED 32'h00000008
`define SPLL_ECCR_EXT_REF_PLLRST_OFFSET 31
`define SPLL_ECCR_EXT_REF_PLLRST 32'h80000000
`define ADDR_SPLL_AL_CR 8'h8
`define SPLL_AL_CR_VALID_OFFSET 0
`define SPLL_AL_CR_VALID 32'h000001ff
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 230ab94b
......@@ -163,6 +163,7 @@ architecture rtl of spec_top is
clk_ext_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
clk_in_stopped_o: out std_logic;
locked_o : out std_logic);
end component;
......@@ -295,21 +296,23 @@ architecture rtl of spec_top is
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
signal local_reset, ext_pll_reset : std_logic;
signal ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_mul_locked : std_logic;
signal clk_ext_stopped : std_logic;
signal clk_ext_rst : std_logic;
signal clk_ref_div2 : std_logic;
begin
local_reset <= not local_reset_n;
U_Ext_PLL : ext_pll_10_to_125m
port map (
clk_ext_i => clk_ext,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
locked_o => clk_ext_mul_locked);
clk_ext_i => clk_ext,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
clk_in_stopped_o => clk_ext_stopped,
locked_o => clk_ext_mul_locked);
U_Extend_EXT_Reset : gc_extend_pulse
generic map (
......@@ -317,7 +320,7 @@ begin
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
pulse_i => local_reset,
pulse_i => clk_ext_rst,
extended_o => ext_pll_reset);
cmp_sys_clk_pll : PLL_BASE
......@@ -585,6 +588,8 @@ begin
clk_ext_i => clk_ext,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i => clk_ext_mul_locked,
clk_ext_stopped_i => clk_ext_stopped,
clk_ext_rst_o => clk_ext_rst,
pps_ext_i => dio_in(3),
rst_n_i => local_reset_n,
......
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