Commit 23add6ef authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk

wrsw_nic: adapted SVN version to pipelined WB fabric

parents
files = [ "nic_constants_pkg.vhd" ,
"nic_descriptors_pkg.vhd" ,
"nic_wishbone_slave.vhd" ,
"nic_descriptor_manager.vhd" ,
"nic_rx_fsm.vhd" ,
"nic_tx_fsm.vhd" ,
"nic_buffer.vhd" ,
"nic_elastic_buffer.vhd",
"nic_wbgen2_pkg.vhd",
"xwrsw_nic.vhd",
"wrsw_nic.vhd"];
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrsw_nic.html -V nic_wishbone_slave.vhd --cstyle defines --lang vhdl -K ../../sim/regs/nic_regs.vh -p nic_wbgen2_pkg.vhd --hstyle record wr_nic.wb
-------------------------------------------------------------------------------
-- Title : Mini Embedded DMA Network Interface Controller
-- Project : WhiteRabbit Core
-------------------------------------------------------------------------------
-- File : nic_buffer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2011-03-15
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: RAM-based packet buffer for the NIC
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-07-26 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
entity nic_buffer is
generic (
g_memsize_log2 : integer := 14);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
addr_i : in std_logic_vector(g_memsize_log2-1 downto 0);
data_i : in std_logic_vector(31 downto 0);
wr_i : in std_logic;
data_o : out std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_addr_i : in std_logic_vector(g_memsize_log2-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end nic_buffer;
architecture syn of nic_buffer is
signal host_we : std_logic;
signal host_ack : std_logic;
begin -- syn
ack_gen : process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
host_ack <= '0';
else
host_ack <= (wb_cyc_i and wb_stb_i) and (not host_ack);
end if;
end if;
end process;
wb_ack_o <= host_ack;
host_we <= wb_cyc_i and wb_stb_i and (wb_we_i and not host_ack);
RAM : generic_dpram
generic map (
g_data_width => 32,
g_size => 2**g_memsize_log2,
g_dual_clock => false)
port map (
-- host port
rst_n_i => rst_n_i,
clka_i => clk_sys_i,
clkb_i => clk_sys_i,
wea_i => host_we,
bwea_i => x"0",
aa_i => wb_addr_i,
da_i => wb_data_i,
qa_o => wb_data_o,
web_i => wr_i,
bweb_i => x"f",
ab_i => addr_i,
db_i => data_i,
qb_o => data_o);
end syn;
-------------------------------------------------------------------------------
-- Title : WR NIC - constants package
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_constants_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2010-11-27
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Package with global NIC constants
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package nic_constants_pkg is
-- number of TX descriptors. Must be a power of 2.
constant c_nic_num_tx_descriptors : integer := 8;
-- log2(c_nic_num_tx_descriptors)
constant c_nic_num_tx_descriptors_log2 : integer := 3;
-- number of RX descriptors. Must be a power of 2.
constant c_nic_num_rx_descriptors : integer := 8;
-- log2(c_nic_num_rx_descriptors)
constant c_nic_num_rx_descriptors_log2 : integer := 3;
-- endianess of the packet buffer
constant c_nic_buf_little_endian : boolean := true;
-- log2(size of the packet buffer)
constant c_nic_buf_size_log2 : integer := 15;
end package nic_constants_pkg;
-------------------------------------------------------------------------------
-- Title : WR NIC - RX descriptor management unit
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_descriptor_manager.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2012-01-13
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-- 2010-11-27 1.0 twlostow Unified RX and TX descriptor mgmt
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.nic_constants_pkg.all;
use work.nic_descriptors_pkg.all;
entity nic_descriptor_manager is
generic (
g_desc_mode : string := "tx";
g_num_descriptors : integer;
g_num_descriptors_log2 : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
enable_i : in std_logic;
bna_o : out std_logic;
bna_clear_i : in std_logic;
cur_desc_idx_o : out std_logic_vector(g_num_descriptors_log2-1 downto 0);
-------------------------------------------------------------------------------
-- Descriptor RAM interface
-------------------------------------------------------------------------------
dtbl_addr_o : out std_logic_vector(g_num_descriptors_log2+1 downto 0);
dtbl_data_i : in std_logic_vector(31 downto 0);
dtbl_rd_o : out std_logic;
dtbl_data_o : out std_logic_vector(31 downto 0);
dtbl_wr_o : out std_logic;
-------------------------------------------------------------------------------
-- RX/TX FSM Interface
-------------------------------------------------------------------------------
desc_reload_current_i : in std_logic;
desc_request_next_i : in std_logic;
desc_grant_o : out std_logic;
rxdesc_current_o : out t_rx_descriptor;
rxdesc_new_i : in t_rx_descriptor;
txdesc_current_o : out t_tx_descriptor;
txdesc_new_i : in t_tx_descriptor;
desc_write_i : in std_logic;
desc_write_done_o : out std_logic
);
end nic_descriptor_manager;
architecture behavioral of nic_descriptor_manager is
type t_desc_arb_state is (ARB_DISABLED, ARB_START_SCAN, ARB_CHECK_EMPTY, ARB_FETCH, ARB_GRANT, ARB_UPDATE, ARB_WRITE_DESC);
signal state : t_desc_arb_state;
signal granted_desc_tx : t_tx_descriptor;
signal granted_desc_rx : t_rx_descriptor;
signal granted_desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_idx_d0 : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_idx : unsigned(g_num_descriptors_log2-1 downto 0);
signal desc_subreg : unsigned(1 downto 0);
signal cntr : unsigned(1 downto 0);
signal check_count : unsigned(g_num_descriptors_log2 downto 0);
signal stupid_hack : std_logic;
impure function f_write_marshalling(index : integer)
return std_logic_vector is
begin
if(g_desc_mode = "rx") then
return f_marshall_rx_descriptor(granted_desc_rx, index);
elsif (g_desc_mode = "tx") then
return f_marshall_tx_descriptor(granted_desc_tx, index);
end if;
end function;
begin -- behavioral
dtbl_addr_o <= std_logic_vector(desc_idx & desc_subreg);
dtbl_rd_o <= '1';
cur_desc_idx_o <= std_logic_vector(desc_idx);
p_rxdesc_arbiter : process(clk_sys_i, rst_n_i)
variable tmp_desc_rx : t_rx_descriptor;
variable tmp_desc_tx : t_tx_descriptor;
-- variable l:line ;
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
desc_write_done_o <= '0';
desc_grant_o <= '0';
state <= ARB_DISABLED;
desc_idx <= (others => '0');
desc_subreg <= (others => '0');
dtbl_wr_o <= '0';
-- dtbl_rd_o <= '0';
dtbl_data_o <= (others => '0');
else
case state is
when ARB_DISABLED =>
desc_idx <= (others => '0');
desc_subreg <= (others => '0');
if(enable_i = '1') then
-- dtbl_rd_o <= '1';
state <= ARB_START_SCAN;
desc_idx <= (others => '0');
check_count <= (others => '0');
end if;
when ARB_START_SCAN =>
if(enable_i = '0') then
state <= ARB_DISABLED;
else
-- wait until the current descriptor is read from the memorry
state <= ARB_CHECK_EMPTY;
-- dtbl_rd_o <='1';
dtbl_wr_o <= '0';
end if;
when ARB_CHECK_EMPTY =>
p_unmarshall_rx_descriptor(dtbl_data_i, 1, tmp_desc_rx);
p_unmarshall_tx_descriptor(dtbl_data_i, 1, tmp_desc_tx);
if((tmp_desc_rx.empty = '1' and g_desc_mode = "rx") or (tmp_desc_tx.ready = '1' and g_desc_mode = "tx")) then
granted_desc_tx <= tmp_desc_tx;
granted_desc_rx <= tmp_desc_rx;
desc_subreg <= "01";
state <= ARB_FETCH;
bna_o <= '0';
else
bna_o <= '1';
end if;
when ARB_FETCH =>
case desc_subreg is
when "10" => -- ignore the timestamps for RX
-- descriptors (they're
-- write-only by the NIC)
p_unmarshall_tx_descriptor(dtbl_data_i, 2, tmp_desc_tx);
granted_desc_tx.len <= tmp_desc_tx.len;
granted_desc_tx.offset <= tmp_desc_tx.offset;
when "11" =>
p_unmarshall_tx_descriptor(dtbl_data_i, 3, tmp_desc_tx); -- TX
granted_desc_tx.dpm <= tmp_desc_tx.dpm;
p_unmarshall_rx_descriptor(dtbl_data_i, 3, tmp_desc_rx); -- RX
granted_desc_rx.len <= tmp_desc_rx.len;
granted_desc_rx.offset <= tmp_desc_rx.offset;
state <= ARB_GRANT;
when others => null;
end case;
desc_subreg <= desc_subreg + 1;
when ARB_GRANT =>
if(desc_request_next_i = '1') then
desc_grant_o <= '1';
if(g_desc_mode = "tx") then
txdesc_current_o <= granted_desc_tx;
elsif (g_desc_mode = "rx") then
rxdesc_current_o <= granted_desc_rx;
end if;
state <= ARB_UPDATE;
end if;
desc_write_done_o <= '0';
when ARB_UPDATE =>
desc_grant_o <= '0';
if(desc_write_i = '1') then
if(g_desc_mode = "rx") then
granted_desc_rx <= rxdesc_new_i;
elsif(g_desc_mode = "tx") then
granted_desc_tx <= txdesc_new_i;
end if;
desc_subreg <= (others => '0');
-- dtbl_rd_o <= '0';
state <= ARB_WRITE_DESC;
cntr <= "00";
end if;
when ARB_WRITE_DESC =>
cntr <= cntr + 1;
-- fprint(output,l, "WriteDesc %b %b\n",fo(cntr),fo(f_write_marshalling(1)));
case cntr is
when "00" =>
desc_subreg <= "00";
dtbl_data_o <= f_write_marshalling(1);
dtbl_wr_o <= '1';
when "01" =>
desc_subreg <= "01";
dtbl_data_o <= f_write_marshalling(2);
dtbl_wr_o <= '1';
when "10" =>
desc_subreg <= "10";
dtbl_data_o <= f_write_marshalling(3);
dtbl_wr_o <= '1';
when "11" =>
dtbl_wr_o <= '0';
desc_subreg <= (others => '0');
state <= ARB_START_SCAN;
if(desc_reload_current_i = '0') then
desc_idx <= desc_idx + 1;
end if;
desc_write_done_o <= '1';
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
end behavioral;
-------------------------------------------------------------------------------
-- Title : WR NIC - descriptors package
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : nic_descriptors_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Last update: 2010-12-01
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: Package declares RX/TX descriptor data types and functions for
-- marshalling/unmarshalling the descriptors to/from SLVs
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.nic_constants_pkg.all;
package nic_descriptors_pkg is
type t_tx_descriptor is record
ts_id : std_logic_vector(15 downto 0); -- OOB frame id (for TX timestamping)
pad_e : std_logic; -- padding enable
ts_e : std_logic; -- timestamp enable
error : std_logic; -- TX error indication
ready : std_logic; -- Descriptor ready for transmission flag
len : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Length of the packet
offset : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Offset of the packet in the buffer
dpm : std_logic_vector(31 downto 0); -- Destination port mask
end record;
type t_rx_descriptor is record
empty : std_logic; -- Descriptor empty (ready for
-- reception) flag
error : std_logic; -- RX error indication
port_id : std_logic_vector(5 downto 0); -- Packet source port ID
got_ts : std_logic; -- Got a timestamp?
ts_r : std_logic_vector(27 downto 0); -- Rising edge timestamp
ts_f : std_logic_vector(3 downto 0); -- Falling edge timestamp
len : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Length of the allocated buffer
-- (or length of the received
-- packet when the desc is not empty)
offset : std_logic_vector(c_nic_buf_size_log2-1 downto 0); -- Address of the buffer;
end record;
function f_marshall_tx_descriptor(desc : t_tx_descriptor;
regnum : integer) return std_logic_vector;
function f_marshall_rx_descriptor(desc : t_rx_descriptor;
regnum : integer) return std_logic_vector;
procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_tx_descriptor);
procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_rx_descriptor);
function f_resize_slv(x : std_logic_vector;
newsize : integer) return std_logic_vector;
end NIC_descriptors_pkg;
package body NIC_descriptors_pkg is
function f_resize_slv(x : std_logic_vector; newsize : integer) return std_logic_vector is
variable tmp:std_logic_vector(newsize-1 downto 0);
begin
tmp(x'length-1 downto 0) := x;
tmp(newsize-1 downto x'length) := (others => '0');
return tmp;
end f_resize_slv;
function f_marshall_tx_descriptor(desc : t_tx_descriptor; regnum : integer) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
begin
case regnum is
when 1 => tmp := desc.ts_id & x"000" & desc.pad_e & desc.ts_e & desc.error & desc.ready;
when 2 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when 3 => tmp := desc.dpm;
when others => null;
end case;
return tmp;
end f_marshall_tx_descriptor;
function f_marshall_rx_descriptor(desc : t_rx_descriptor; regnum : integer) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
begin
case regnum is
when 1 => tmp := "00000000000000000" & desc.got_ts & desc.port_id & "000000" & desc.error & desc.empty;
when 2 => tmp := desc.ts_f & desc.ts_r;
when 3 => tmp := f_resize_slv(desc.len, 16) & f_resize_slv(desc.offset, 16);
when others => null;
end case;
return tmp;
end f_marshall_rx_descriptor;
procedure p_unmarshall_tx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_tx_descriptor) is
begin
case regnum is
when 1 =>
desc.ts_id := mem_input(31 downto 16);
desc.pad_e := mem_input(3);
desc.ts_e := mem_input(2);
desc.error := mem_input(1);
desc.ready := mem_input(0);
when 2 =>
desc.len := mem_input(16+c_nic_buf_size_log2-1 downto 16);
desc.offset := mem_input(c_nic_buf_size_log2-1 downto 0);
when 3 =>
desc.dpm := mem_input;
when others => null;
end case;
end p_unmarshall_tx_descriptor;
procedure p_unmarshall_rx_descriptor(mem_input : in std_logic_vector(31 downto 0);
regnum : in integer;
desc : inout t_rx_descriptor) is
begin
case regnum is
when 1 =>
desc.empty := mem_input(0);
desc.error := mem_input(1);
desc.port_id := mem_input(13 downto 8);
desc.got_ts := mem_input(14);
when 2 =>
desc.ts_f := mem_input(31 downto 28);
desc.ts_r := mem_input(27 downto 0);
when 3 =>
desc.len := mem_input(16+c_nic_buf_size_log2-1 downto 16);
desc.offset := mem_input(c_nic_buf_size_log2-1 downto 0);
when others => null;
end case;
end p_unmarshall_rx_descriptor;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.endpoint_private_pkg.all; -- dirty hack, again
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity nic_elastic_buffer is
generic (
g_depth : integer := 64);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
fab_o : out t_ep_internal_fabric;
dreq_i : in std_logic
);
end nic_elastic_buffer;
architecture rtl of nic_elastic_buffer is
function log2 (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 32 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function log2;
constant c_fifo_width : integer := 16 + 2 + 5;
signal fifo_write : std_logic;
signal fifo_read : std_logic;
signal fifo_in_ser : std_logic_vector(c_fifo_width-1 downto 0);
signal fifo_out_ser : std_logic_vector(c_fifo_width-1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_usedw : std_logic_vector(log2(g_depth)-1 downto 0);
signal output_valid : std_logic;
signal got_empty : std_logic;
signal cyc_d0 : std_logic;
signal fifo_in : t_ep_internal_fabric;
signal fifo_out : t_ep_internal_fabric;
signal snk_out : t_wrf_sink_out;
signal stall_int : std_logic;
begin -- rtl
p_delay_cyc : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
else
cyc_d0 <= snk_i.cyc;
end if;
end if;
end process;
snk_o <= snk_out;
snk_out.err <= fifo_full and snk_i.cyc and snk_i.stb;
snk_out.rty <= '0';
p_gen_ack : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and not snk_out.stall;
end if;
end if;
end process;
fifo_in.sof <= not cyc_d0 and snk_i.cyc;
fifo_in.eof <= cyc_d0 and not snk_i.cyc;
fifo_in.data <= snk_i.dat;
fifo_in.dvalid <= snk_i.stb and snk_i.cyc and not snk_out.stall;
fifo_in.addr <= snk_i.adr;
fifo_in.error <= '1' when (fifo_in.dvalid = '1') and
snk_i.adr = c_WRF_STATUS and
(f_unmarshall_wrf_status(snk_i.dat).error = '1') else '0';
fifo_in.bytesel <= not snk_i.sel(0);
fifo_write <= fifo_in.sof or fifo_in.eof or fifo_in.dvalid or fifo_in.error;
fifo_in_ser <= fifo_in.bytesel & fifo_in.sof & fifo_in.eof & fifo_in.dvalid & fifo_in.error & fifo_in.addr & fifo_in.data;
p_gen_stall : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
stall_int <= '0';
else
if (unsigned(fifo_usedw) < g_depth/2) then
stall_int <= '0';
elsif (unsigned(fifo_usedw) > g_depth-5) then
stall_int <= '1';
end if;
end if;
end if;
end process;
snk_out.stall <= fifo_in.sof or stall_int;
fifo_read <= not fifo_empty and dreq_i;
p_gen_valid_flag : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
output_valid <= '0';
else
output_valid <= fifo_read;
end if;
end if;
end process;
U_fifo : generic_sync_fifo
generic map (
g_data_width => c_fifo_width,
g_size => g_depth,
g_with_count => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
we_i => fifo_write,
d_i => fifo_in_ser,
rd_i => fifo_read,
q_o => fifo_out_ser,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => fifo_usedw
);
fab_o.data <= fifo_out_ser(15 downto 0);
fab_o.addr <= fifo_out_ser(17 downto 16);
fab_o.error <= fifo_out_ser(18) and output_valid;
fab_o.dvalid <= fifo_out_ser(19) and output_valid;
fab_o.eof <= fifo_out_ser(20) and output_valid;
fab_o.sof <= fifo_out_ser(21) and output_valid;
fab_o.bytesel <= fifo_out_ser(22);
end rtl;
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for White Rabbit Switch NIC's spec
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Thu Jan 12 17:37:53 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package nic_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_nic_in_registers is record
sr_bna_i : std_logic;
sr_rec_i : std_logic;
sr_tx_done_i : std_logic;
sr_tx_error_i : std_logic;
sr_cur_tx_desc_i : std_logic_vector(2 downto 0);
sr_cur_rx_desc_i : std_logic_vector(2 downto 0);
end record;
constant c_nic_in_registers_init_value: t_nic_in_registers := (
sr_bna_i => '0',
sr_rec_i => '0',
sr_tx_done_i => '0',
sr_tx_error_i => '0',
sr_cur_tx_desc_i => (others => '0'),
sr_cur_rx_desc_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_nic_out_registers is record
cr_rx_en_o : std_logic;
cr_tx_en_o : std_logic;
sr_rec_o : std_logic;
sr_rec_load_o : std_logic;
sr_tx_done_o : std_logic;
sr_tx_done_load_o : std_logic;
sr_tx_error_o : std_logic;
sr_tx_error_load_o : std_logic;
reset_o : std_logic_vector(31 downto 0);
reset_wr_o : std_logic;
end record;
constant c_nic_out_registers_init_value: t_nic_out_registers := (
cr_rx_en_o => '0',
cr_tx_en_o => '0',
sr_rec_o => '0',
sr_rec_load_o => '0',
sr_tx_done_o => '0',
sr_tx_done_load_o => '0',
sr_tx_error_o => '0',
sr_tx_error_load_o => '0',
reset_o => (others => '0'),
reset_wr_o => '0'
);
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
end package;
package body nic_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers is
variable tmp: t_nic_in_registers;
begin
tmp.sr_bna_i := left.sr_bna_i or right.sr_bna_i;
tmp.sr_rec_i := left.sr_rec_i or right.sr_rec_i;
tmp.sr_tx_done_i := left.sr_tx_done_i or right.sr_tx_done_i;
tmp.sr_tx_error_i := left.sr_tx_error_i or right.sr_tx_error_i;
tmp.sr_cur_tx_desc_i := left.sr_cur_tx_desc_i or right.sr_cur_tx_desc_i;
tmp.sr_cur_rx_desc_i := left.sr_cur_rx_desc_i or right.sr_cur_rx_desc_i;
return tmp;
end function;
end package body;
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library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity wrsw_nic is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- Pipelined Wishbone interface
-------------------------------------------------------------------------------
-- WBP Master (TX)
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_err_i : in std_logic;
src_ack_i : in std_logic;
-- WBP Slave (RX)
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_err_o : out std_logic;
snk_ack_o : out std_logic;
-------------------------------------------------------------------------------
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic
);
end wrsw_nic;
architecture rtl of wrsw_nic is
component xwrsw_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
signal snk_out : t_wrf_sink_out;
signal snk_in : t_wrf_sink_in;
signal src_out : t_wrf_source_out;
signal src_in : t_wrf_source_in;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin
U_Wrapped_NIC : xwrsw_nic
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
src_i => src_in,
src_o => src_out,
rtu_dst_port_mask_o => rtu_dst_port_mask_o,
rtu_prio_o => rtu_prio_o,
rtu_drop_o => rtu_drop_o,
rtu_rsp_valid_o => rtu_rsp_valid_o,
rtu_rsp_ack_i => rtu_rsp_ack_i,
wb_i => wb_in,
wb_o => wb_out);
-- WBP Master (TX)
src_dat_o <= src_out.dat;
src_adr_o <= src_out.adr;
src_sel_o <= src_out.sel;
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_in.stall <= src_stall_i;
src_in.err <= src_err_i;
src_in.ack <= src_ack_i;
-- WBP Slave (RX)
snk_in.dat <= snk_dat_i;
snk_in.adr <= snk_adr_i;
snk_in.sel <= snk_sel_i;
snk_in.cyc <= snk_cyc_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_stall_o <= snk_out.stall;
snk_err_o <= snk_out.err;
snk_ack_o <= snk_out.ack;
wb_in.cyc <= wb_cyc_i;
wb_in.stb <= wb_stb_i;
wb_in.we <= wb_we_i;
wb_in.sel <= wb_sel_i;
wb_in.adr <= wb_adr_i;
wb_in.dat <= wb_dat_i;
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
wb_irq_o <= wb_out.int;
end rtl;
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