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Commits
26a3f9ea
Commit
26a3f9ea
authored
Dec 11, 2019
by
Tomasz Wlostowski
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svec7: bring back PLL aux clock, pll reference is 125 MHz
parent
53dd7e43
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2 changed files
with
63 additions
and
39 deletions
+63
-39
xwrc_board_svec7.vhd
board/svec7/xwrc_board_svec7.vhd
+25
-19
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+38
-20
No files found.
board/svec7/xwrc_board_svec7.vhd
View file @
26a3f9ea
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2019-1
0-17
-- Last update: 2019-1
2-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -93,8 +93,8 @@ entity xwrc_board_svec7 is
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
-- Clock inputs from the board
clk_20m_vcxo_i
:
in
std_logic
;
clk_
62m5
_pllref_p_i
:
in
std_logic
;
clk_
62m5
_pllref_n_i
:
in
std_logic
;
clk_
125m
_pllref_p_i
:
in
std_logic
;
clk_
125m
_pllref_n_i
:
in
std_logic
;
clk_125m_gtx_n_i
:
in
std_logic
;
clk_125m_gtx_p_i
:
in
std_logic
;
-- Aux clocks, which can be disciplined by the WR Core
...
...
@@ -105,6 +105,8 @@ entity xwrc_board_svec7 is
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz sys clock output
clk_sys_125m_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_62m5_o
:
out
std_logic
;
-- 125.x MHz DDMTD clock
...
...
@@ -115,6 +117,7 @@ entity xwrc_board_svec7 is
rst_pll_aux_n_o
:
out
std_logic_vector
(
3
downto
0
);
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o
:
out
std_logic
;
rst_sys_125m_n_o
:
out
std_logic
;
rst_ref_62m5_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
...
...
@@ -270,10 +273,11 @@ architecture struct of xwrc_board_svec7 is
-----------------------------------------------------------------------------
-- IBUFDS
signal
clk_
62m5
_pllref_buf
:
std_logic
;
signal
clk_
125m
_pllref_buf
:
std_logic
;
-- PLLs
signal
clk_pll_sys_62m5
:
std_logic
;
signal
clk_pll_sys_125m
:
std_logic
;
signal
clk_pll_ref_62m5
:
std_logic
;
signal
clk_pll_dmtd
:
std_logic
;
signal
pll_locked
:
std_logic
;
...
...
@@ -287,8 +291,8 @@ architecture struct of xwrc_board_svec7 is
signal
areset_edge_ppulse
:
std_logic
;
signal
rst_62m5_n
:
std_logic
;
signal
rstlogic_arst
:
std_logic
;
signal
rstlogic_clk_in
:
std_logic_vector
(
5
downto
0
);
signal
rstlogic_rst_out
:
std_logic_vector
(
5
downto
0
);
signal
rstlogic_clk_in
:
std_logic_vector
(
6
downto
0
);
signal
rstlogic_rst_out
:
std_logic_vector
(
6
downto
0
);
-- PLL DAC ARB
signal
dac_sync_n
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -312,7 +316,6 @@ architecture struct of xwrc_board_svec7 is
signal
ext_ref_mul_locked
:
std_logic
;
signal
ext_ref_mul_stopped
:
std_logic
;
signal
ext_ref_rst
:
std_logic
;
signal
clk_pll_62m5
:
std_logic
;
...
...
@@ -328,9 +331,9 @@ begin -- architecture struct
IBUF_LOW_PWR
=>
TRUE
,
IOSTANDARD
=>
"DEFAULT"
)
port
map
(
O
=>
clk_
62m5
_pllref_buf
,
I
=>
clk_
62m5
_pllref_p_i
,
IB
=>
clk_
62m5
_pllref_n_i
);
O
=>
clk_
125m
_pllref_buf
,
I
=>
clk_
125m
_pllref_p_i
,
IB
=>
clk_
125m
_pllref_n_i
);
cmp_xwrc_platform
:
entity
work
.
xwrc_platform_xilinx
generic
map
(
...
...
@@ -343,8 +346,7 @@ begin -- architecture struct
areset_n_i
=>
areset_n_i
,
clk_10m_ext_i
=>
clk_10m_ext_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_62m5_pllref_i
=>
clk_62m5_pllref_buf
,
-- fixme : different clock
-- freq
clk_125m_pllref_i
=>
clk_125m_pllref_buf
,
clk_125m_gtp_p_i
=>
clk_125m_gtx_p_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtx_n_i
,
sfp_txn_o
=>
sfp_txn_o
,
...
...
@@ -356,6 +358,7 @@ begin -- architecture struct
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
clk_pll_aux_o
=>
clk_pll_aux
,
clk_62m5_sys_o
=>
clk_pll_sys_62m5
,
clk_125m_sys_o
=>
clk_pll_sys_125m
,
clk_62m5_ref_o
=>
clk_pll_ref_62m5
,
clk_62m5_dmtd_o
=>
clk_pll_dmtd
,
pll_locked_o
=>
pll_locked
,
...
...
@@ -368,6 +371,7 @@ begin -- architecture struct
ext_ref_rst_i
=>
ext_ref_rst
);
clk_sys_62m5_o
<=
clk_pll_sys_62m5
;
clk_sys_125m_o
<=
clk_pll_sys_125m
;
clk_ref_62m5_o
<=
clk_pll_ref_62m5
;
clk_pll_aux_o
<=
clk_pll_aux
;
...
...
@@ -382,7 +386,7 @@ begin -- architecture struct
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_pll_
62m5
,
clk_i
=>
clk_pll_
sys_125m
,
rst_n_i
=>
'1'
,
data_i
=>
areset_edge_n_i
,
ppulse_o
=>
areset_edge_ppulse
);
...
...
@@ -392,12 +396,13 @@ begin -- architecture struct
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in
(
0
)
<=
clk_pll_sys_62m5
;
rstlogic_clk_in
(
1
)
<=
clk_pll_ref_62m5
;
rstlogic_clk_in
(
5
downto
2
)
<=
clk_pll_aux
;
rstlogic_clk_in
(
1
)
<=
clk_pll_sys_125m
;
rstlogic_clk_in
(
2
)
<=
clk_pll_ref_62m5
;
rstlogic_clk_in
(
6
downto
3
)
<=
clk_pll_aux
;
cmp_rstlogic_reset
:
gc_reset_multi_aasd
generic
map
(
g_CLOCKS
=>
6
,
-- 62.5MHz, 125MHz, + 4x pll_aux
g_CLOCKS
=>
7
,
-- 62.5MHz, 125MHz, + 4x pll_aux
g_RST_LEN
=>
16
)
-- 16 clock cycles
port
map
(
arst_i
=>
rstlogic_arst
,
...
...
@@ -407,9 +412,10 @@ begin -- architecture struct
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n
<=
rstlogic_rst_out
(
0
);
rst_sys_125m_n_o
<=
rstlogic_rst_out
(
1
);
rst_sys_62m5_n_o
<=
rst_62m5_n
;
rst_ref_62m5_n_o
<=
rstlogic_rst_out
(
1
);
rst_pll_aux_n_o
<=
rstlogic_rst_out
(
5
downto
2
);
rst_ref_62m5_n_o
<=
rstlogic_rst_out
(
2
);
rst_pll_aux_n_o
<=
rstlogic_rst_out
(
6
downto
3
);
-----------------------------------------------------------------------------
-- 2x SPI DAC
...
...
@@ -420,7 +426,7 @@ begin -- architecture struct
g_invert_sclk
=>
FALSE
,
g_num_extra_bits
=>
8
)
port
map
(
clk_i
=>
clk_pll_
62m5
,
clk_i
=>
clk_pll_
sys_125m
,
rst_n_i
=>
rst_62m5_n
,
val1_i
=>
dac_dpll_data
,
load1_i
=>
dac_dpll_load_p1
,
...
...
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
26a3f9ea
...
...
@@ -66,6 +66,9 @@ entity xwrc_platform_xilinx is
-- Select GTP channel to use
g_gtp_enable_ch0
:
integer
:
=
0
;
g_gtp_enable_ch1
:
integer
:
=
1
;
-- Use 125 MHz PLL reference (SVEC7)
g_use_125m_pllref
:
integer
:
=
1
;
-- Select PHY reference clock
-- default value of 4 selects CLK10 / CLK11 (see UG386, Fig 2-3, page 41)
g_phy_refclk_sel
:
integer
range
0
to
7
:
=
4
;
...
...
@@ -154,6 +157,8 @@ entity xwrc_platform_xilinx is
-- PLL outputs
clk_62m5_sys_o
:
out
std_logic
;
clk_125m_ref_o
:
out
std_logic
;
clk_125m_sys_o
:
out
std_logic
;
clk_62m5_ref_o
:
out
std_logic
;
clk_20m_o
:
out
std_logic
;
clk_ref_locked_o
:
out
std_logic
;
...
...
@@ -183,6 +188,7 @@ architecture rtl of xwrc_platform_xilinx is
signal
pll_arst
:
std_logic
:
=
'0'
;
signal
clk_125m_pllref_buf
:
std_logic
;
signal
clk_pll_aux
:
std_logic_vector
(
3
downto
0
);
begin
-- architecture rtl
...
...
@@ -231,6 +237,25 @@ begin -- architecture rtl
-- active high async reset for PLLs
pll_arst
<=
not
areset_n_i
;
-- PLL aux clocks buffers
gen_auxclk_bufs
:
for
I
in
0
to
3
generate
-- Aux PLL_BASE clocks with BUFG enabled
gen_auxclk_bufg_en
:
if
g_aux_pll_cfg
(
I
)
.
enabled
=
TRUE
and
g_aux_pll_cfg
(
I
)
.
bufg_en
=
TRUE
generate
cmp_auxclk_bufg
:
BUFG
port
map
(
O
=>
clk_pll_aux_o
(
I
),
I
=>
clk_pll_aux
(
I
));
end
generate
;
-- Aux PLL_BASE clocks with BUFG disabled
gen_auxclk_no_bufg
:
if
g_aux_pll_cfg
(
I
)
.
enabled
=
TRUE
and
g_aux_pll_cfg
(
I
)
.
bufg_en
=
FALSE
generate
clk_pll_aux_o
(
I
)
<=
clk_pll_aux
(
I
);
end
generate
;
-- Disabled aux PLL_BASE clocks
gen_auxclk_disabled
:
if
g_aux_pll_cfg
(
I
)
.
enabled
=
FALSE
generate
clk_pll_aux_o
(
I
)
<=
'0'
;
end
generate
;
end
generate
;
gen_default_plls
:
if
(
g_use_default_plls
=
TRUE
)
generate
-- Default PLL setup consists of two PLLs.
...
...
@@ -253,7 +278,6 @@ begin -- architecture rtl
signal
clk_dmtd_fb
:
std_logic
;
signal
pll_dmtd_locked
:
std_logic
;
signal
clk_20m_vcxo_buf
:
std_logic
;
signal
clk_pll_aux
:
std_logic_vector
(
3
downto
0
);
signal
clk_125m_pllref_buf_int1
:
std_logic
;
signal
clk_125m_pllref_buf_int2
:
std_logic
;
...
...
@@ -313,24 +337,7 @@ begin -- architecture rtl
O
=>
clk_125m_pllref_buf_int1
,
I
=>
clk_125m_pllref_i
);
-- PLL aux clocks buffers
gen_auxclk_bufs
:
for
I
in
0
to
3
generate
-- Aux PLL_BASE clocks with BUFG enabled
gen_auxclk_bufg_en
:
if
g_aux_pll_cfg
(
I
)
.
enabled
=
TRUE
and
g_aux_pll_cfg
(
I
)
.
bufg_en
=
TRUE
generate
cmp_auxclk_bufg
:
BUFG
port
map
(
O
=>
clk_pll_aux_o
(
I
),
I
=>
clk_pll_aux
(
I
));
end
generate
;
-- Aux PLL_BASE clocks with BUFG disabled
gen_auxclk_no_bufg
:
if
g_aux_pll_cfg
(
I
)
.
enabled
=
TRUE
and
g_aux_pll_cfg
(
I
)
.
bufg_en
=
FALSE
generate
clk_pll_aux_o
(
I
)
<=
clk_pll_aux
(
I
);
end
generate
;
-- Disabled aux PLL_BASE clocks
gen_auxclk_disabled
:
if
g_aux_pll_cfg
(
I
)
.
enabled
=
FALSE
generate
clk_pll_aux_o
(
I
)
<=
'0'
;
end
generate
;
end
generate
;
-- System PLL output clock buffer
cmp_clk_sys_buf_o
:
BUFG
...
...
@@ -588,12 +595,21 @@ begin -- architecture rtl
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT0_USE_FINE_PS
=>
false
,
CLKOUT1_DIVIDE
=>
g_aux_pll_cfg
(
0
)
.
divide
,
CLKOUT1_PHASE
=>
0
.
000
,
CLKOUT1_DUTY_CYCLE
=>
0
.
500
,
CLKOUT2_DIVIDE
=>
g_aux_pll_cfg
(
1
)
.
divide
,
CLKOUT2_PHASE
=>
0
.
000
,
CLKOUT2_DUTY_CYCLE
=>
0
.
500
,
CLKIN1_PERIOD
=>
8
.
000
,
-- 8 ns means 125 MHz
REF_JITTER1
=>
0
.
010
)
port
map
(
-- Output clocks
CLKFBOUT
=>
clk_sys_fb
,
CLKOUT0
=>
clk_sys
,
CLKOUT1
=>
clk_pll_aux
(
0
),
CLKOUT2
=>
clk_pll_aux
(
1
),
-- Input clock control
CLKFBIN
=>
clk_sys_fb
,
CLKIN1
=>
clk_125m_pllref_buf
,
...
...
@@ -1347,6 +1363,8 @@ begin -- architecture rtl
I
=>
clk_125m_gtx_buf
,
O
=>
clk_125m_pllref_buf
);
clk_125m_sys_o
<=
clk_125m_pllref_buf
;
cmp_gtx
:
wr_gtx_phy_family7
generic
map
(
g_simulation
=>
g_simulation
)
...
...
@@ -1374,7 +1392,7 @@ begin -- architecture rtl
tx_locked_o
=>
clk_ref_locked
);
clk_
125m
_ref_o
<=
clk_ref
;
clk_
62m5
_ref_o
<=
clk_ref
;
clk_ref_locked_o
<=
clk_ref_locked
;
phy16_o
.
ref_clk
<=
clk_ref
;
phy16_o
.
sfp_tx_fault
<=
sfp_tx_fault_i
;
...
...
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