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White Rabbit core collection
Commits
295f4a86
Commit
295f4a86
authored
Aug 01, 2016
by
Grzegorz Daniluk
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Plain Diff
wrsw_nic: adding enable bit for b/w throttling
parent
7d0948af
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5 changed files
with
28 additions
and
4 deletions
+28
-4
nic_bw_throttling.vhd
modules/wrsw_nic/nic_bw_throttling.vhd
+7
-1
nic_rx_fsm.vhd
modules/wrsw_nic/nic_rx_fsm.vhd
+2
-0
nic_wbgen2_pkg.vhd
modules/wrsw_nic/nic_wbgen2_pkg.vhd
+3
-1
nic_wishbone_slave.vhd
modules/wrsw_nic/nic_wishbone_slave.vhd
+7
-2
wr_nic.wb
modules/wrsw_nic/wr_nic.wb
+9
-0
No files found.
modules/wrsw_nic/nic_bw_throttling.vhd
View file @
295f4a86
...
...
@@ -56,6 +56,7 @@ entity nic_bw_throttling is
src_o
:
out
t_wrf_source_out
;
src_i
:
in
t_wrf_source_in
;
en_i
:
in
std_logic
;
new_limit_i
:
in
std_logic
;
bwmax_kbps_i
:
in
unsigned
(
15
downto
0
);
bw_bps_o
:
out
std_logic_vector
(
31
downto
0
));
...
...
@@ -127,7 +128,7 @@ begin
thr_step_kbps
<=
shift_right
(
bwmax_kbps_i
-
bwmin_kbps
,
3
);
-- both max and min b/w we divide by 8 (because we want 8 steps like with
-- c_DROP_STEP = 64 for range 0-255)
els
e
els
if
en_i
=
'1'
then
if
(
bwcur_kbps
>
last_thr_kbps
and
drop_thr
<
c_DROP_THR_MAX
)
then
-- current b/w is larger than the last crossed threshold
-- we increase the probability of drop
...
...
@@ -141,6 +142,11 @@ begin
last_thr_kbps
<=
last_thr_kbps
-
thr_step_kbps
;
end
if
;
else
-- If the module is disabled, keep drop_thr at 0 so that we don't drop
-- any frames.
drop_thr
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
process
;
...
...
modules/wrsw_nic/nic_rx_fsm.vhd
View file @
295f4a86
...
...
@@ -133,6 +133,7 @@ architecture behavioral of NIC_RX_FSM is
snk_o
:
out
t_wrf_sink_out
;
src_o
:
out
t_wrf_source_out
;
src_i
:
in
t_wrf_source_in
;
en_i
:
in
std_logic
;
new_limit_i
:
in
std_logic
;
bwmax_kbps_i
:
in
unsigned
(
15
downto
0
);
bw_bps_o
:
out
std_logic_vector
(
31
downto
0
));
...
...
@@ -181,6 +182,7 @@ begin
snk_o
=>
snk_o
,
src_o
=>
bw_src_out
,
src_i
=>
bw_src_in
,
en_i
=>
regs_i
.
cr_rxthr_en_o
,
new_limit_i
=>
regs_i
.
maxrxbw_load_o
,
bwmax_kbps_i
=>
unsigned
(
regs_i
.
maxrxbw_o
),
bw_bps_o
=>
regs_o
.
rxbw_i
);
...
...
modules/wrsw_nic/nic_wbgen2_pkg.vhd
View file @
295f4a86
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Mon Aug 1 16:
03:57
2016
-- Created : Mon Aug 1 16:
26:56
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
...
@@ -47,6 +47,7 @@ package nic_wbgen2_pkg is
type
t_nic_out_registers
is
record
cr_rx_en_o
:
std_logic
;
cr_tx_en_o
:
std_logic
;
cr_rxthr_en_o
:
std_logic
;
cr_sw_rst_o
:
std_logic
;
sr_rec_o
:
std_logic
;
sr_rec_load_o
:
std_logic
;
...
...
@@ -61,6 +62,7 @@ package nic_wbgen2_pkg is
constant
c_nic_out_registers_init_value
:
t_nic_out_registers
:
=
(
cr_rx_en_o
=>
'0'
,
cr_tx_en_o
=>
'0'
,
cr_rxthr_en_o
=>
'0'
,
cr_sw_rst_o
=>
'0'
,
sr_rec_o
=>
'0'
,
sr_rec_load_o
=>
'0'
,
...
...
modules/wrsw_nic/nic_wishbone_slave.vhd
View file @
295f4a86
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Mon Aug 1 16:
03:57
2016
-- Created : Mon Aug 1 16:
26:56
2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
...
@@ -69,6 +69,7 @@ architecture syn of nic_wishbone_slave is
signal
nic_cr_rx_en_int
:
std_logic
;
signal
nic_cr_tx_en_int
:
std_logic
;
signal
nic_cr_rxthr_en_int
:
std_logic
;
signal
nic_cr_sw_rst_dly0
:
std_logic
;
signal
nic_cr_sw_rst_int
:
std_logic
;
signal
nic_dtx_rddata_int
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -116,6 +117,7 @@ begin
rddata_reg
<=
"00000000000000000000000000000000"
;
nic_cr_rx_en_int
<=
'0'
;
nic_cr_tx_en_int
<=
'0'
;
nic_cr_rxthr_en_int
<=
'0'
;
nic_cr_sw_rst_int
<=
'0'
;
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
...
...
@@ -154,12 +156,13 @@ begin
if
(
wb_we_i
=
'1'
)
then
nic_cr_rx_en_int
<=
wrdata_reg
(
0
);
nic_cr_tx_en_int
<=
wrdata_reg
(
1
);
nic_cr_rxthr_en_int
<=
wrdata_reg
(
2
);
nic_cr_sw_rst_int
<=
wrdata_reg
(
31
);
end
if
;
rddata_reg
(
0
)
<=
nic_cr_rx_en_int
;
rddata_reg
(
1
)
<=
nic_cr_tx_en_int
;
rddata_reg
(
2
)
<=
nic_cr_rxthr_en_int
;
rddata_reg
(
31
)
<=
'0'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
...
...
@@ -470,6 +473,8 @@ begin
regs_o
.
cr_rx_en_o
<=
nic_cr_rx_en_int
;
-- Transmit enable
regs_o
.
cr_tx_en_o
<=
nic_cr_tx_en_int
;
-- Rx bandwidth throttling enable
regs_o
.
cr_rxthr_en_o
<=
nic_cr_rxthr_en_int
;
-- Software Reset
process
(
clk_sys_i
,
rst_n_i
)
begin
...
...
modules/wrsw_nic/wr_nic.wb
View file @
295f4a86
...
...
@@ -63,6 +63,15 @@ top = peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx bandwidth throttling enable";
description = "Enables bandwidth throttling for received traffic. \
This is to prevent blocking ARM CPU with interrupts coming from NIC";
prefix = "rxthr_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Software Reset";
...
...
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