wr_streamers: fixed parse error in tx/rx software reset signal assignments

2d9130e5 · Tomasz Wlostowski · 7ed6e81a · 2d9130e5
Commit 2d9130e5 authored Oct 19, 2018 by Tomasz Wlostowski
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xwr_streamers.vhd modules/wr_streamers/xwr_streamers.vhd +3 -3

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--- a/modules/wr_streamers/xwr_streamers.vhd
+++ b/modules/wr_streamers/xwr_streamers.vhd
@@ -390,7 +390,7 @@ begin
      master_i   => wb_regs_slave_out,
      master_o   => wb_regs_slave_in);

-  U_WB:  wr_streamers_wb
+  U_WB: entity work.wr_streamers_wb
    port map (
      rst_n_i      => rst_n_i,
      clk_sys_i    => clk_sys_i,
@@ -490,7 +490,7 @@ begin
                                       rx_streamer_cfg_i.fixed_latency;


-  rx_streamer_cfg.reset_sw <= from_wb.rstr_rst_sw_o;
-  tx_streamer_cfg.reset_sw <= from_wb.rstr_rst_sw_o;
+  rx_streamer_cfg.sw_reset <= from_wb.rstr_rst_sw_o;
+  tx_streamer_cfg.sw_reset <= from_wb.rstr_rst_sw_o;

 end rtl;