Make the 500MHz clock output from PLL_BASE(clkout1).

The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL (CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a BUFG (O) when using ENABLE_SYNC (FALSE)." I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but the 10MHz output is still missing. So I have to change the setting of "cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from CLKOUT2.

Make the 500MHz clock output from PLL_BASE(clkout1).
The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL (CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a BUFG (O) when using ENABLE_SYNC (FALSE)." I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but the 10MHz output is still missing. So I have to change the setting of "cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from CLKOUT2.
2e037cba · li hongming · Grzegorz Daniluk · c418861a · 2e037cba · 2e037cba
Commit 2e037cba authored Jan 22, 2019 by li hongming Committed by Grzegorz Daniluk Jan 22, 2019
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xwrc_platform_xilinx.vhd platform/xilinx/xwrc_platform_xilinx.vhd +8 -5

cute_wr_ref.xise syn/cute_ref_design/cute_wr_ref.xise +359 -349

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--- a/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/platform/xilinx/xwrc_platform_xilinx.vhd
@@ -267,11 +267,11 @@ begin  -- architecture rtl
          CLKOUT0_DIVIDE     => 16,
          CLKOUT0_PHASE      => 0.000,
          CLKOUT0_DUTY_CYCLE => 0.500,
-          CLKOUT1_DIVIDE     => 8,
+          CLKOUT1_DIVIDE     => g_aux_pll_cfg(0).divide,
          CLKOUT1_PHASE      => 0.000,
          CLKOUT1_DUTY_CYCLE => 0.500,
          -- Aux user clocks parameters
-          CLKOUT2_DIVIDE     => g_aux_pll_cfg(0).divide,
+          CLKOUT2_DIVIDE     => 8,
          CLKOUT2_PHASE      => 0.000,
          CLKOUT2_DUTY_CYCLE => 0.500,
          CLKOUT3_DIVIDE     => g_aux_pll_cfg(1).divide,
@@ -289,8 +289,8 @@ begin  -- architecture rtl
        port map (
          CLKFBOUT => clk_sys_fb,
          CLKOUT0  => clk_sys,
-          CLKOUT1  => clk_125m_pllref_buf_int2,
-          CLKOUT2  => clk_pll_aux(0),
+          CLKOUT1  => clk_pll_aux(0),
+          CLKOUT2  => clk_125m_pllref_buf_int2,
          CLKOUT3  => clk_pll_aux(1),
          CLKOUT4  => clk_pll_aux(2),
          CLKOUT5  => clk_pll_aux(3),
@@ -305,8 +305,11 @@ begin  -- architecture rtl
          O => clk_125m_pllref_buf_int1,
          I => clk_125m_pllref_i);

+      -- direct output
+      clk_pll_aux_o(0) <= clk_pll_aux(0);
+
      -- DDR PLL global clock buffers
-      gen_auxclk_bufs: for I in 0 to 3 generate
+      gen_auxclk_bufs: for I in 1 to 3 generate
        gen_auxclk_enabled: if g_aux_pll_cfg(I).enabled = TRUE generate
          cmp_auxclk_bufg : BUFG
            port map (

--- a/syn/cute_ref_design/cute_wr_ref.xise
+++ b/syn/cute_ref_design/cute_wr_ref.xise