no technical change, cleanup copyright holders as instructed by Javier

2fa6bed8 · Grzegorz Daniluk · 0618fbe4 · 2fa6bed8 · 2fa6bed8 · 2fa6bed8
Commit 2fa6bed8 authored Dec 13, 2017 by Grzegorz Daniluk
34 changed files
--- a/modules/fabric/xwrf_mux.vhd
+++ b/modules/fabric/xwrf_mux.vhd
@@ -18,7 +18,7 @@
 -- has to be forwarded to Mini-NIC (if it is the PTP message) or to the 
 -- external interface (others).
 -------------------------------------------------------------------------------
-- Copyright (c) 2012 Grzegorz Daniluk
+-- Copyright (c) 2012 - 2017 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/timing/hpll_period_detect.vhd
+++ b/modules/timing/hpll_period_detect.vhd
@@ -18,7 +18,7 @@
 -- - positive when clk_fbck_i is slower than selected frequency setpoint
 -- - negative when clk_fbck_i is faster than selected frequency setpoint
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+++ b/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
@@ -17,7 +17,7 @@
 -- It also generates deterministic timestamping pulses for RXed packets.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011-2017 Tomasz Wlostowski / CERN
+-- Copyright (c) 2011-2017 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+++ b/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
@@ -17,7 +17,7 @@
 -- pulses for RXed packets.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009-2017 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009-2017 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wr_endpoint/ep_rx_wb_master.vhd
+++ b/modules/wr_endpoint/ep_rx_wb_master.vhd
@@ -13,7 +13,7 @@
 -- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
 -- throttling) to Pipelined Wishbone (b4)
 -------------------------------------------------------------------------------
-- Copyright (c) 2011-2017 CERN/Tomasz Wlostowski
+-- Copyright (c) 2011-2017 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author  Description

--- a/modules/wr_endpoint/ep_sync_detect.vhd
+++ b/modules/wr_endpoint/ep_sync_detect.vhd
@@ -13,7 +13,7 @@
 -- Description: Module implements a link synchronization detect state machine
 -- compatible with 802.3x spec.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wr_endpoint/ep_sync_detect_16bit.vhd
+++ b/modules/wr_endpoint/ep_sync_detect_16bit.vhd
@@ -13,7 +13,7 @@
 -- Description: Module implements a link synchronization detect state machine
 -- compatible with 802.3x spec.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wr_endpoint/ep_ts_counter.vhd
+++ b/modules/wr_endpoint/ep_ts_counter.vhd
@@ -15,7 +15,7 @@
 -- rising edge counter. For space reasons only some LSBs of falling edge
 -- counter are outputted.
 -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski
+-- Copyright (c) 2009 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author    Description

--- a/modules/wr_endpoint/ep_tx_framer.vhd
+++ b/modules/wr_endpoint/ep_tx_framer.vhd
@@ -17,7 +17,7 @@
 -- - strips 802.1q headers when necessary
 -- - decodes TX OOB data and passes it to the timestamping unit
 -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski
+-- Copyright (c) 2009 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+++ b/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : ep_tx_pcs_tbi.vhd
 -- Author     : Tomasz Wlostowski
-- Company    : CERN BE-CO-HT section
+-- Company    : CERN BE-CO-HT
 -- Created    : 2009-06-16
 -- Last update: 2017-02-20
 -- Platform   : FPGA-generic
@@ -23,7 +23,7 @@
 --
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009-2017 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009-2017 CERN
 --
 -- This source file is free software; you can redistribute it
 -- and/or modify it under the terms of the GNU Lesser General

--- a/modules/wr_mini_nic/minic_packet_buffer.vhd
+++ b/modules/wr_mini_nic/minic_packet_buffer.vhd
@@ -13,7 +13,7 @@
 -- Description: RAM-based packet buffer for miNIC implementations which don't
 -- use the DMA access to the system memory
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wr_softpll_ng/spll_bangbang_pd.vhd
+++ b/modules/wr_softpll_ng/spll_bangbang_pd.vhd
@@ -16,7 +16,7 @@
 -- clk_fbck_i cycles. Divider counters can be synchronized at any moment 
 -- by pulsing the sync_p_i signal.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wr_softpll_ng/spll_period_detect.vhd
+++ b/modules/wr_softpll_ng/spll_period_detect.vhd
@@ -18,7 +18,7 @@
 -- - positive when clk_fbck_i is slower than selected frequency setpoint
 -- - negative when clk_fbck_i is faster than selected frequency setpoint
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wr_tbi_phy/wr_tbi_phy.vhd
+++ b/modules/wr_tbi_phy/wr_tbi_phy.vhd
@@ -11,7 +11,7 @@
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wr_core.vhd
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company    : CERN (BE-CO-HT), Elproma
+-- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
 -- Last update: 2017-05-29
 -- Platform   : FPGA-generics
@@ -23,8 +23,7 @@
 -- MAC interface.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012, 2017 CERN
+-- Copyright (c) 2012 - 2017 CERN
 --
 -- This source file is free software; you can redistribute it
 -- and/or modify it under the terms of the GNU Lesser General

--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wrc_periph.vhd
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company    : CERN (BE-CO-HT), Elproma
+-- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-04-04
 -- Last update: 2017-04-25
 -- Platform   : FPGA-generics
@@ -15,8 +15,7 @@
 -- 
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012, 2017 CERN
+-- Copyright (c) 2012 - 2017 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -4,15 +4,14 @@
 -------------------------------------------------------------------------------
 -- File       : wrcore_pkg.vhd
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company    : CERN (BE-CO-HT), Elproma
+-- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-05-11
 -- Last update: 2017-05-29
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012, 2017 CERN
+-- Copyright (c) 2012 - 2017 CERN
 --
 -- This source file is free software; you can redistribute it
 -- and/or modify it under the terms of the GNU Lesser General

--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : xwr_core.vhd
 -- Author     : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company    : CERN (BE-CO-HT), Elproma
+-- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-02
 -- Last update: 2017-05-29
 -- Platform   : FPGA-generics
@@ -23,8 +23,7 @@
 -- and External MAC interface.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012, 2017 CERN
+-- Copyright (c) 2012 - 2017 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
@@ -14,7 +14,7 @@
 -- deterministic delays at 1.25 Gbps.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
@@ -14,7 +14,7 @@
 -- deterministic delays at 1.25 Gbps.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
@@ -14,7 +14,7 @@
 -- deterministic delays at 1.25 Gbps.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
@@ -15,7 +15,7 @@
 -- GTP transceivers.  
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
@@ -14,7 +14,7 @@
 -- defined in IEEE802.3.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
@@ -14,7 +14,7 @@
 -- TX and RX path of the MAC. 
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
@@ -14,7 +14,7 @@
 -- RMON statistics. The block is RAM-based to reduce the FPGA footprint
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
@@ -12,7 +12,7 @@
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
@@ -16,7 +16,7 @@
 -- - parses packet headers and generates RTU requests
 -- - embeds RX OOB block with timestamp information
 -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski
+-- Copyright (c) 2009 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author  Description

--- a/testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
@@ -17,7 +17,7 @@
 -- pulses for RXed packets.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
@@ -13,7 +13,7 @@
 -- Description: Module implements a link synchronization detect state machine
 -- compatible with 802.3x spec.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
@@ -20,7 +20,7 @@
 --   occur during sampling asynchronous timestamp strobes.
 -- Both timestamps are taken using refclk_i.
 -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski
+-- Copyright (c) 2009 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author  Description

--- a/testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
@@ -15,7 +15,7 @@
 -- rising edge counter. For space reasons only some LSBs of falling edge
 -- counter are outputted.
 -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski
+-- Copyright (c) 2009 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author    Description

--- a/testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
@@ -17,7 +17,7 @@
 -- - strips 802.1q headers when necessary
 -- - decodes TX OOB data and passes it to the timestamping unit
 -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski
+-- Copyright (c) 2009 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
+++ b/testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
@@ -23,7 +23,7 @@
 --
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
+-- Copyright (c) 2009 CERN
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   

--- a/testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
+++ b/testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
@@ -20,7 +20,7 @@
 -- - clock phase measurement (DMTD)
 -- - decodes MAC addresses, VIDs and priorities and passes them to the RTU.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description