Commit 2fa6bed8 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

no technical change, cleanup copyright holders as instructed by Javier

parent 0618fbe4
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
-- has to be forwarded to Mini-NIC (if it is the PTP message) or to the -- has to be forwarded to Mini-NIC (if it is the PTP message) or to the
-- external interface (others). -- external interface (others).
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2012 Grzegorz Daniluk -- Copyright (c) 2012 - 2017 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
-- - positive when clk_fbck_i is slower than selected frequency setpoint -- - positive when clk_fbck_i is slower than selected frequency setpoint
-- - negative when clk_fbck_i is faster than selected frequency setpoint -- - negative when clk_fbck_i is faster than selected frequency setpoint
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
-- It also generates deterministic timestamping pulses for RXed packets. -- It also generates deterministic timestamping pulses for RXed packets.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2011-2017 Tomasz Wlostowski / CERN -- Copyright (c) 2011-2017 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
-- pulses for RXed packets. -- pulses for RXed packets.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2017 Tomasz Wlostowski / CERN -- Copyright (c) 2009-2017 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
-- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID -- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
-- throttling) to Pipelined Wishbone (b4) -- throttling) to Pipelined Wishbone (b4)
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2011-2017 CERN/Tomasz Wlostowski -- Copyright (c) 2011-2017 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
-- Description: Module implements a link synchronization detect state machine -- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec. -- compatible with 802.3x spec.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
-- Description: Module implements a link synchronization detect state machine -- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec. -- compatible with 802.3x spec.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- rising edge counter. For space reasons only some LSBs of falling edge -- rising edge counter. For space reasons only some LSBs of falling edge
-- counter are outputted. -- counter are outputted.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski -- Copyright (c) 2009 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
-- - strips 802.1q headers when necessary -- - strips 802.1q headers when necessary
-- - decodes TX OOB data and passes it to the timestamping unit -- - decodes TX OOB data and passes it to the timestamping unit
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski -- Copyright (c) 2009 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : ep_tx_pcs_tbi.vhd -- File : ep_tx_pcs_tbi.vhd
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT section -- Company : CERN BE-CO-HT
-- Created : 2009-06-16 -- Created : 2009-06-16
-- Last update: 2017-02-20 -- Last update: 2017-02-20
-- Platform : FPGA-generic -- Platform : FPGA-generic
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2017 Tomasz Wlostowski / CERN -- Copyright (c) 2009-2017 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
-- Description: RAM-based packet buffer for miNIC implementations which don't -- Description: RAM-based packet buffer for miNIC implementations which don't
-- use the DMA access to the system memory -- use the DMA access to the system memory
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
-- clk_fbck_i cycles. Divider counters can be synchronized at any moment -- clk_fbck_i cycles. Divider counters can be synchronized at any moment
-- by pulsing the sync_p_i signal. -- by pulsing the sync_p_i signal.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
-- - positive when clk_fbck_i is slower than selected frequency setpoint -- - positive when clk_fbck_i is slower than selected frequency setpoint
-- - negative when clk_fbck_i is faster than selected frequency setpoint -- - negative when clk_fbck_i is faster than selected frequency setpoint
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : wr_core.vhd -- File : wr_core.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT), Elproma -- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02 -- Created : 2011-02-02
-- Last update: 2017-05-29 -- Last update: 2017-05-29
-- Platform : FPGA-generics -- Platform : FPGA-generics
...@@ -23,8 +23,7 @@ ...@@ -23,8 +23,7 @@
-- MAC interface. -- MAC interface.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2011, 2012 Elproma Elektronika -- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : wrc_periph.vhd -- File : wrc_periph.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT), Elproma -- Company : CERN (BE-CO-HT)
-- Created : 2011-04-04 -- Created : 2011-04-04
-- Last update: 2017-04-25 -- Last update: 2017-04-25
-- Platform : FPGA-generics -- Platform : FPGA-generics
...@@ -15,8 +15,7 @@ ...@@ -15,8 +15,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2011, 2012 Elproma Elektronika -- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -4,15 +4,14 @@ ...@@ -4,15 +4,14 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : wrcore_pkg.vhd -- File : wrcore_pkg.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT), Elproma -- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11 -- Created : 2011-05-11
-- Last update: 2017-05-29 -- Last update: 2017-05-29
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2011, 2012 Elproma Elektronika -- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : xwr_core.vhd -- File : xwr_core.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT), Elproma -- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02 -- Created : 2011-02-02
-- Last update: 2017-05-29 -- Last update: 2017-05-29
-- Platform : FPGA-generics -- Platform : FPGA-generics
...@@ -23,8 +23,7 @@ ...@@ -23,8 +23,7 @@
-- and External MAC interface. -- and External MAC interface.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2011, 2012 Elproma Elektronika -- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
-- deterministic delays at 1.25 Gbps. -- deterministic delays at 1.25 Gbps.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2010 CERN / Tomasz Wlostowski -- Copyright (c) 2010 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
-- deterministic delays at 1.25 Gbps. -- deterministic delays at 1.25 Gbps.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2010 CERN / Tomasz Wlostowski -- Copyright (c) 2010 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
-- deterministic delays at 1.25 Gbps. -- deterministic delays at 1.25 Gbps.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2010 CERN / Tomasz Wlostowski -- Copyright (c) 2010 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- GTP transceivers. -- GTP transceivers.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN -- Copyright (c) 2009 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
-- defined in IEEE802.3. -- defined in IEEE802.3.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN -- Copyright (c) 2009 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
-- TX and RX path of the MAC. -- TX and RX path of the MAC.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN -- Copyright (c) 2009 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
-- RMON statistics. The block is RAM-based to reduce the FPGA footprint -- RMON statistics. The block is RAM-based to reduce the FPGA footprint
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN -- Copyright (c) 2009 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: -- Description:
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
-- - parses packet headers and generates RTU requests -- - parses packet headers and generates RTU requests
-- - embeds RX OOB block with timestamp information -- - embeds RX OOB block with timestamp information
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski -- Copyright (c) 2009 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
-- pulses for RXed packets. -- pulses for RXed packets.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN -- Copyright (c) 2009 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
-- Description: Module implements a link synchronization detect state machine -- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec. -- compatible with 802.3x spec.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
-- occur during sampling asynchronous timestamp strobes. -- occur during sampling asynchronous timestamp strobes.
-- Both timestamps are taken using refclk_i. -- Both timestamps are taken using refclk_i.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski -- Copyright (c) 2009 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- rising edge counter. For space reasons only some LSBs of falling edge -- rising edge counter. For space reasons only some LSBs of falling edge
-- counter are outputted. -- counter are outputted.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski -- Copyright (c) 2009 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
-- - strips 802.1q headers when necessary -- - strips 802.1q headers when necessary
-- - decodes TX OOB data and passes it to the timestamping unit -- - decodes TX OOB data and passes it to the timestamping unit
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2009 Tomasz Wlostowski -- Copyright (c) 2009 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009 Tomasz Wlostowski / CERN -- Copyright (c) 2009 CERN
-- --
-- This source file is free software; you can redistribute it -- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General -- and/or modify it under the terms of the GNU Lesser General
......
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
-- - clock phase measurement (DMTD) -- - clock phase measurement (DMTD)
-- - decodes MAC addresses, VIDs and priorities and passes them to the RTU. -- - decodes MAC addresses, VIDs and priorities and passes them to the RTU.
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski -- Copyright (c) 2010 CERN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : -- Revisions :
-- Date Version Author Description -- Date Version Author Description
......
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