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White Rabbit core collection
Commits
2fa6bed8
Commit
2fa6bed8
authored
Dec 13, 2017
by
Grzegorz Daniluk
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no technical change, cleanup copyright holders as instructed by Javier
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34 changed files
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39 additions
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43 deletions
+39
-43
xwrf_mux.vhd
modules/fabric/xwrf_mux.vhd
+1
-1
hpll_period_detect.vhd
modules/timing/hpll_period_detect.vhd
+1
-1
ep_rx_pcs_16bit.vhd
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+1
-1
ep_rx_pcs_8bit.vhd
modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+1
-1
ep_rx_wb_master.vhd
modules/wr_endpoint/ep_rx_wb_master.vhd
+1
-1
ep_sync_detect.vhd
modules/wr_endpoint/ep_sync_detect.vhd
+1
-1
ep_sync_detect_16bit.vhd
modules/wr_endpoint/ep_sync_detect_16bit.vhd
+1
-1
ep_ts_counter.vhd
modules/wr_endpoint/ep_ts_counter.vhd
+1
-1
ep_tx_framer.vhd
modules/wr_endpoint/ep_tx_framer.vhd
+1
-1
ep_tx_pcs_8bit.vhd
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+2
-2
minic_packet_buffer.vhd
modules/wr_mini_nic/minic_packet_buffer.vhd
+1
-1
spll_bangbang_pd.vhd
modules/wr_softpll_ng/spll_bangbang_pd.vhd
+1
-1
spll_period_detect.vhd
modules/wr_softpll_ng/spll_period_detect.vhd
+1
-1
wr_tbi_phy.vhd
modules/wr_tbi_phy/wr_tbi_phy.vhd
+1
-1
wr_core.vhd
modules/wrc_core/wr_core.vhd
+2
-3
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+2
-3
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+2
-3
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+2
-3
wr_gtp_phy_spartan6.vhd
platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+1
-1
wr_gtx_phy_kintex7.vhd
platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
+1
-1
wr_gtx_phy_virtex6.vhd
platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+1
-1
old_ep_1000basex_pcs.vhd
testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
+1
-1
old_ep_autonegotiation.vhd
testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
+1
-1
old_ep_flow_control.vhd
testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
+1
-1
old_ep_rmon_counters.vhd
testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
+1
-1
old_ep_rx_buffer.vhd
testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
+1
-1
old_ep_rx_deframer.vhd
testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
+1
-1
old_ep_rx_pcs_tbi.vhd
testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
+1
-1
old_ep_sync_detect.vhd
testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
+1
-1
old_ep_timestamping_unit.vhd
testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
+1
-1
old_ep_ts_counter.vhd
testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
+1
-1
old_ep_tx_framer.vhd
testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
+1
-1
old_ep_tx_pcs_tbi.vhd
testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
+1
-1
old_wrsw_endpoint.vhd
testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
+1
-1
No files found.
modules/fabric/xwrf_mux.vhd
View file @
2fa6bed8
...
@@ -18,7 +18,7 @@
...
@@ -18,7 +18,7 @@
-- has to be forwarded to Mini-NIC (if it is the PTP message) or to the
-- has to be forwarded to Mini-NIC (if it is the PTP message) or to the
-- external interface (others).
-- external interface (others).
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2012
Grzegorz Daniluk
-- Copyright (c) 2012
- 2017 CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/timing/hpll_period_detect.vhd
View file @
2fa6bed8
...
@@ -18,7 +18,7 @@
...
@@ -18,7 +18,7 @@
-- - positive when clk_fbck_i is slower than selected frequency setpoint
-- - positive when clk_fbck_i is slower than selected frequency setpoint
-- - negative when clk_fbck_i is faster than selected frequency setpoint
-- - negative when clk_fbck_i is faster than selected frequency setpoint
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @
2fa6bed8
...
@@ -17,7 +17,7 @@
...
@@ -17,7 +17,7 @@
-- It also generates deterministic timestamping pulses for RXed packets.
-- It also generates deterministic timestamping pulses for RXed packets.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2011-2017
Tomasz Wlostowski /
CERN
-- Copyright (c) 2011-2017 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wr_endpoint/ep_rx_pcs_8bit.vhd
View file @
2fa6bed8
...
@@ -17,7 +17,7 @@
...
@@ -17,7 +17,7 @@
-- pulses for RXed packets.
-- pulses for RXed packets.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009-2017
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009-2017 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @
2fa6bed8
...
@@ -13,7 +13,7 @@
...
@@ -13,7 +13,7 @@
-- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
-- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
-- throttling) to Pipelined Wishbone (b4)
-- throttling) to Pipelined Wishbone (b4)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2017 CERN
/Tomasz Wlostowski
-- Copyright (c) 2011-2017 CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_sync_detect.vhd
View file @
2fa6bed8
...
@@ -13,7 +13,7 @@
...
@@ -13,7 +13,7 @@
-- Description: Module implements a link synchronization detect state machine
-- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec.
-- compatible with 802.3x spec.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_sync_detect_16bit.vhd
View file @
2fa6bed8
...
@@ -13,7 +13,7 @@
...
@@ -13,7 +13,7 @@
-- Description: Module implements a link synchronization detect state machine
-- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec.
-- compatible with 802.3x spec.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_ts_counter.vhd
View file @
2fa6bed8
...
@@ -15,7 +15,7 @@
...
@@ -15,7 +15,7 @@
-- rising edge counter. For space reasons only some LSBs of falling edge
-- rising edge counter. For space reasons only some LSBs of falling edge
-- counter are outputted.
-- counter are outputted.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2009
Tomasz Wlostowski
-- Copyright (c) 2009
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_tx_framer.vhd
View file @
2fa6bed8
...
@@ -17,7 +17,7 @@
...
@@ -17,7 +17,7 @@
-- - strips 802.1q headers when necessary
-- - strips 802.1q headers when necessary
-- - decodes TX OOB data and passes it to the timestamping unit
-- - decodes TX OOB data and passes it to the timestamping unit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2009
Tomasz Wlostowski
-- Copyright (c) 2009
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @
2fa6bed8
...
@@ -4,7 +4,7 @@
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : ep_tx_pcs_tbi.vhd
-- File : ep_tx_pcs_tbi.vhd
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
section
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Created : 2009-06-16
-- Last update: 2017-02-20
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Platform : FPGA-generic
...
@@ -23,7 +23,7 @@
...
@@ -23,7 +23,7 @@
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009-2017
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009-2017 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wr_mini_nic/minic_packet_buffer.vhd
View file @
2fa6bed8
...
@@ -13,7 +13,7 @@
...
@@ -13,7 +13,7 @@
-- Description: RAM-based packet buffer for miNIC implementations which don't
-- Description: RAM-based packet buffer for miNIC implementations which don't
-- use the DMA access to the system memory
-- use the DMA access to the system memory
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_softpll_ng/spll_bangbang_pd.vhd
View file @
2fa6bed8
...
@@ -16,7 +16,7 @@
...
@@ -16,7 +16,7 @@
-- clk_fbck_i cycles. Divider counters can be synchronized at any moment
-- clk_fbck_i cycles. Divider counters can be synchronized at any moment
-- by pulsing the sync_p_i signal.
-- by pulsing the sync_p_i signal.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_softpll_ng/spll_period_detect.vhd
View file @
2fa6bed8
...
@@ -18,7 +18,7 @@
...
@@ -18,7 +18,7 @@
-- - positive when clk_fbck_i is slower than selected frequency setpoint
-- - positive when clk_fbck_i is slower than selected frequency setpoint
-- - negative when clk_fbck_i is faster than selected frequency setpoint
-- - negative when clk_fbck_i is faster than selected frequency setpoint
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wr_tbi_phy/wr_tbi_phy.vhd
View file @
2fa6bed8
...
@@ -11,7 +11,7 @@
...
@@ -11,7 +11,7 @@
-- Standard : VHDL
-- Standard : VHDL
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
modules/wrc_core/wr_core.vhd
View file @
2fa6bed8
...
@@ -4,7 +4,7 @@
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wr_core.vhd
-- File : wr_core.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
, Elproma
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Created : 2011-02-02
-- Last update: 2017-05-29
-- Last update: 2017-05-29
-- Platform : FPGA-generics
-- Platform : FPGA-generics
...
@@ -23,8 +23,7 @@
...
@@ -23,8 +23,7 @@
-- MAC interface.
-- MAC interface.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrc_core/wrc_periph.vhd
View file @
2fa6bed8
...
@@ -4,7 +4,7 @@
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wrc_periph.vhd
-- File : wrc_periph.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
, Elproma
-- Company : CERN (BE-CO-HT)
-- Created : 2011-04-04
-- Created : 2011-04-04
-- Last update: 2017-04-25
-- Last update: 2017-04-25
-- Platform : FPGA-generics
-- Platform : FPGA-generics
...
@@ -15,8 +15,7 @@
...
@@ -15,8 +15,7 @@
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
2fa6bed8
...
@@ -4,15 +4,14 @@
...
@@ -4,15 +4,14 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wrcore_pkg.vhd
-- File : wrcore_pkg.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
, Elproma
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Created : 2011-05-11
-- Last update: 2017-05-29
-- Last update: 2017-05-29
-- Platform : FPGA-generics
-- Platform : FPGA-generics
-- Standard : VHDL
-- Standard : VHDL
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wrc_core/xwr_core.vhd
View file @
2fa6bed8
...
@@ -4,7 +4,7 @@
...
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : xwr_core.vhd
-- File : xwr_core.vhd
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
, Elproma
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Created : 2011-02-02
-- Last update: 2017-05-29
-- Last update: 2017-05-29
-- Platform : FPGA-generics
-- Platform : FPGA-generics
...
@@ -23,8 +23,7 @@
...
@@ -23,8 +23,7 @@
-- and External MAC interface.
-- and External MAC interface.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012, 2017 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
View file @
2fa6bed8
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
-- deterministic delays at 1.25 Gbps.
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2010 CERN
/ Tomasz Wlostowski
-- Copyright (c) 2010 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
View file @
2fa6bed8
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
-- deterministic delays at 1.25 Gbps.
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2010 CERN
/ Tomasz Wlostowski
-- Copyright (c) 2010 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
View file @
2fa6bed8
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
-- deterministic delays at 1.25 Gbps.
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2010 CERN
/ Tomasz Wlostowski
-- Copyright (c) 2010 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
testbench/wr_endpoint/old_ep/old_ep_1000basex_pcs.vhd
View file @
2fa6bed8
...
@@ -15,7 +15,7 @@
...
@@ -15,7 +15,7 @@
-- GTP transceivers.
-- GTP transceivers.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
testbench/wr_endpoint/old_ep/old_ep_autonegotiation.vhd
View file @
2fa6bed8
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
-- defined in IEEE802.3.
-- defined in IEEE802.3.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
testbench/wr_endpoint/old_ep/old_ep_flow_control.vhd
View file @
2fa6bed8
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
-- TX and RX path of the MAC.
-- TX and RX path of the MAC.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
testbench/wr_endpoint/old_ep/old_ep_rmon_counters.vhd
View file @
2fa6bed8
...
@@ -14,7 +14,7 @@
...
@@ -14,7 +14,7 @@
-- RMON statistics. The block is RAM-based to reduce the FPGA footprint
-- RMON statistics. The block is RAM-based to reduce the FPGA footprint
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
testbench/wr_endpoint/old_ep/old_ep_rx_buffer.vhd
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2fa6bed8
...
@@ -12,7 +12,7 @@
...
@@ -12,7 +12,7 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Description:
-- Description:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
testbench/wr_endpoint/old_ep/old_ep_rx_deframer.vhd
View file @
2fa6bed8
...
@@ -16,7 +16,7 @@
...
@@ -16,7 +16,7 @@
-- - parses packet headers and generates RTU requests
-- - parses packet headers and generates RTU requests
-- - embeds RX OOB block with timestamp information
-- - embeds RX OOB block with timestamp information
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2009
Tomasz Wlostowski
-- Copyright (c) 2009
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
testbench/wr_endpoint/old_ep/old_ep_rx_pcs_tbi.vhd
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2fa6bed8
...
@@ -17,7 +17,7 @@
...
@@ -17,7 +17,7 @@
-- pulses for RXed packets.
-- pulses for RXed packets.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
testbench/wr_endpoint/old_ep/old_ep_sync_detect.vhd
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@@ -13,7 +13,7 @@
...
@@ -13,7 +13,7 @@
-- Description: Module implements a link synchronization detect state machine
-- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec.
-- compatible with 802.3x spec.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
testbench/wr_endpoint/old_ep/old_ep_timestamping_unit.vhd
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@@ -20,7 +20,7 @@
...
@@ -20,7 +20,7 @@
-- occur during sampling asynchronous timestamp strobes.
-- occur during sampling asynchronous timestamp strobes.
-- Both timestamps are taken using refclk_i.
-- Both timestamps are taken using refclk_i.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2009
Tomasz Wlostowski
-- Copyright (c) 2009
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
testbench/wr_endpoint/old_ep/old_ep_ts_counter.vhd
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@@ -15,7 +15,7 @@
...
@@ -15,7 +15,7 @@
-- rising edge counter. For space reasons only some LSBs of falling edge
-- rising edge counter. For space reasons only some LSBs of falling edge
-- counter are outputted.
-- counter are outputted.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2009
Tomasz Wlostowski
-- Copyright (c) 2009
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
testbench/wr_endpoint/old_ep/old_ep_tx_framer.vhd
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2fa6bed8
...
@@ -17,7 +17,7 @@
...
@@ -17,7 +17,7 @@
-- - strips 802.1q headers when necessary
-- - strips 802.1q headers when necessary
-- - decodes TX OOB data and passes it to the timestamping unit
-- - decodes TX OOB data and passes it to the timestamping unit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2009
Tomasz Wlostowski
-- Copyright (c) 2009
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
testbench/wr_endpoint/old_ep/old_ep_tx_pcs_tbi.vhd
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2fa6bed8
...
@@ -23,7 +23,7 @@
...
@@ -23,7 +23,7 @@
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (c) 2009
Tomasz Wlostowski /
CERN
-- Copyright (c) 2009 CERN
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
...
...
testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
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@@ -20,7 +20,7 @@
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@@ -20,7 +20,7 @@
-- - clock phase measurement (DMTD)
-- - clock phase measurement (DMTD)
-- - decodes MAC addresses, VIDs and priorities and passes them to the RTU.
-- - decodes MAC addresses, VIDs and priorities and passes them to the RTU.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2010
Tomasz Wlostowski
-- Copyright (c) 2010
CERN
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Revisions :
-- Date Version Author Description
-- Date Version Author Description
...
...
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