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White Rabbit core collection
Commit 30363ccd authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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fasec: fix eeprom, sfp, thermometer tristate buffers

parent 63580516
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board/fasec/component.xml
View file @ 30363ccd
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" <spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>CERN</spirit:vendor> <spirit:vendor>CERN</spirit:vendor>
<spirit:library>white_rabbit</spirit:library> <spirit:library>white_rabbit</spirit:library>
<spirit:name>wrc_board_fasec</spirit:name> <spirit:name>wrc_board_fasec</spirit:name>
...@@ -9,14 +7,8 @@ ...@@ -9,14 +7,8 @@
<spirit:busInterfaces> <spirit:busInterfaces>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>s00_axi</spirit:name> <spirit:name>s00_axi</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
spirit:library="interface" <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
spirit:name="aximm"
spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com"
spirit:library="interface"
spirit:name="aximm_rtl"
spirit:version="1.0"/>
<spirit:slave> <spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="s00_axi"/> <spirit:memoryMapRef spirit:memoryMapRef="s00_axi"/>
</spirit:slave> </spirit:slave>
...@@ -176,14 +168,8 @@ ...@@ -176,14 +168,8 @@
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>s00_axi_aresetn</spirit:name> <spirit:name>s00_axi_aresetn</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
spirit:library="signal" <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
spirit:name="reset"
spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com"
spirit:library="signal"
spirit:name="reset_rtl"
spirit:version="1.0"/>
<spirit:slave/> <spirit:slave/>
<spirit:portMaps> <spirit:portMaps>
<spirit:portMap> <spirit:portMap>
...@@ -198,21 +184,14 @@ ...@@ -198,21 +184,14 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>POLARITY</spirit:name> <spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ARESETN.POLARITY" <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>s00_axi_aclk_o</spirit:name> <spirit:name>s00_axi_aclk_o</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
spirit:library="signal" <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
spirit:name="clock"
spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com"
spirit:library="signal"
spirit:name="clock_rtl"
spirit:version="1.0"/>
<spirit:master/> <spirit:master/>
<spirit:portMaps> <spirit:portMaps>
<spirit:portMap> <spirit:portMap>
...@@ -241,24 +220,10 @@ ...@@ -241,24 +220,10 @@
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>SFP</spirit:name> <spirit:name>SFP</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="sfp" spirit:version="1.0"/>
spirit:library="interface" <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="sfp_rtl" spirit:version="1.0"/>
spirit:name="sfp"
spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com"
spirit:library="interface"
spirit:name="sfp_rtl"
spirit:version="1.0"/>
<spirit:master/> <spirit:master/>
<spirit:portMaps> <spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sfp_sda_b</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap> <spirit:portMap>
<spirit:logicalPort> <spirit:logicalPort>
<spirit:name>TX_DISABLE</spirit:name> <spirit:name>TX_DISABLE</spirit:name>
...@@ -323,42 +288,172 @@ ...@@ -323,42 +288,172 @@
<spirit:name>sfp_tx_p_o</spirit:name> <spirit:name>sfp_tx_p_o</spirit:name>
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>UART</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap> <spirit:portMap>
<spirit:logicalPort> <spirit:logicalPort>
<spirit:name>SCL</spirit:name> <spirit:name>TxD</spirit:name>
</spirit:logicalPort> </spirit:logicalPort>
<spirit:physicalPort> <spirit:physicalPort>
<spirit:name>sfp_scl_b</spirit:name> <spirit:name>uart_txd_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RxD</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>uart_rxd_i</spirit:name>
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
</spirit:busInterface> </spirit:busInterface>
<spirit:busInterface> <spirit:busInterface>
<spirit:name>UART</spirit:name> <spirit:name>sfp_i2c</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic" spirit:version="1.0"/>
spirit:library="interface" <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic_rtl" spirit:version="1.0"/>
spirit:name="uart"
spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com"
spirit:library="interface"
spirit:name="uart_rtl"
spirit:version="1.0"/>
<spirit:master/> <spirit:master/>
<spirit:portMaps> <spirit:portMaps>
<spirit:portMap> <spirit:portMap>
<spirit:logicalPort> <spirit:logicalPort>
<spirit:name>TxD</spirit:name> <spirit:name>SCL_T</spirit:name>
</spirit:logicalPort> </spirit:logicalPort>
<spirit:physicalPort> <spirit:physicalPort>
<spirit:name>uart_txd_o</spirit:name> <spirit:name>sfp_scl_t</spirit:name>
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
<spirit:portMap> <spirit:portMap>
<spirit:logicalPort> <spirit:logicalPort>
<spirit:name>RxD</spirit:name> <spirit:name>SDA_O</spirit:name>
</spirit:logicalPort> </spirit:logicalPort>
<spirit:physicalPort> <spirit:physicalPort>
<spirit:name>uart_rxd_i</spirit:name> <spirit:name>sfp_sda_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDA_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sfp_sda_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDA_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sfp_sda_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SCL_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sfp_scl_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SCL_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sfp_scl_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>eeprom_i2c</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SCL_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eeprom_scl_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDA_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eeprom_sda_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDA_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eeprom_sda_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDA_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eeprom_sda_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SCL_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eeprom_scl_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SCL_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eeprom_scl_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>thermo_id</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>thermo_id_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>thermo_id_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>thermo_id_i</spirit:name>
</spirit:physicalPort> </spirit:physicalPort>
</spirit:portMap> </spirit:portMap>
</spirit:portMaps> </spirit:portMaps>
...@@ -369,15 +464,9 @@ ...@@ -369,15 +464,9 @@
<spirit:name>s00_axi</spirit:name> <spirit:name>s00_axi</spirit:name>
<spirit:addressBlock> <spirit:addressBlock>
<spirit:name>reg0</spirit:name> <spirit:name>reg0</spirit:name>
<spirit:baseAddress spirit:format="bitString" <spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
spirit:resolve="user" <spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">135168</spirit:range>
spirit:bitStringLength="32">0</spirit:baseAddress> <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
<spirit:range spirit:format="long"
spirit:resolve="user"
spirit:minimum="4096"
spirit:rangeType="long">135168</spirit:range>
<spirit:width spirit:format="long"
spirit:resolve="user">32</spirit:width>
<spirit:usage>register</spirit:usage> <spirit:usage>register</spirit:usage>
</spirit:addressBlock> </spirit:addressBlock>
</spirit:memoryMap> </spirit:memoryMap>
...@@ -396,7 +485,7 @@ ...@@ -396,7 +485,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>bd78fe9f</spirit:value> <spirit:value>0649a5f4</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -412,7 +501,7 @@ ...@@ -412,7 +501,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>38aec1b8</spirit:value> <spirit:value>3365b256</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -426,7 +515,7 @@ ...@@ -426,7 +515,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>viewChecksum</spirit:name> <spirit:name>viewChecksum</spirit:name>
<spirit:value>3bc04777</spirit:value> <spirit:value>939d4b1a</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
</spirit:view> </spirit:view>
...@@ -522,8 +611,7 @@ ...@@ -522,8 +611,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -539,8 +627,7 @@ ...@@ -539,8 +627,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -712,15 +799,27 @@ ...@@ -712,15 +799,27 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
spirit:bitStringLength="1">0x1</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:name>sfp_sda_b</spirit:name> <spirit:name>sfp_sda_i</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>sfp_sda_o</spirit:name>
<spirit:wire> <spirit:wire>
<spirit:direction>inout</spirit:direction> <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs> <spirit:wireTypeDefs>
<spirit:wireTypeDef> <spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName> <spirit:typeName>std_logic</spirit:typeName>
...@@ -731,9 +830,48 @@ ...@@ -731,9 +830,48 @@
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:name>sfp_scl_b</spirit:name> <spirit:name>sfp_sda_t</spirit:name>
<spirit:wire> <spirit:wire>
<spirit:direction>inout</spirit:direction> <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>sfp_scl_i</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>sfp_scl_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>sfp_scl_t</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs> <spirit:wireTypeDefs>
<spirit:wireTypeDef> <spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName> <spirit:typeName>std_logic</spirit:typeName>
...@@ -768,8 +906,7 @@ ...@@ -768,8 +906,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -798,15 +935,27 @@ ...@@ -798,15 +935,27 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:name>eeprom_scl_b</spirit:name> <spirit:name>eeprom_sda_i</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>eeprom_sda_o</spirit:name>
<spirit:wire> <spirit:wire>
<spirit:direction>inout</spirit:direction> <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs> <spirit:wireTypeDefs>
<spirit:wireTypeDef> <spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName> <spirit:typeName>std_logic</spirit:typeName>
...@@ -817,9 +966,9 @@ ...@@ -817,9 +966,9 @@
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:name>eeprom_sda_b</spirit:name> <spirit:name>eeprom_sda_t</spirit:name>
<spirit:wire> <spirit:wire>
<spirit:direction>inout</spirit:direction> <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs> <spirit:wireTypeDefs>
<spirit:wireTypeDef> <spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName> <spirit:typeName>std_logic</spirit:typeName>
...@@ -830,9 +979,74 @@ ...@@ -830,9 +979,74 @@
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:name>thermo_id</spirit:name> <spirit:name>eeprom_scl_i</spirit:name>
<spirit:wire> <spirit:wire>
<spirit:direction>inout</spirit:direction> <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>eeprom_scl_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>eeprom_scl_t</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>thermo_id_i</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>thermo_id_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>thermo_id_t</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs> <spirit:wireTypeDefs>
<spirit:wireTypeDef> <spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName> <spirit:typeName>std_logic</spirit:typeName>
...@@ -893,8 +1107,7 @@ ...@@ -893,8 +1107,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
spirit:bitStringLength="1">0x1</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -930,8 +1143,7 @@ ...@@ -930,8 +1143,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -1000,8 +1212,7 @@ ...@@ -1000,8 +1212,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -1060,8 +1271,7 @@ ...@@ -1060,8 +1271,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -1097,8 +1307,7 @@ ...@@ -1097,8 +1307,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -1174,8 +1383,7 @@ ...@@ -1174,8 +1383,7 @@
</spirit:wireTypeDef> </spirit:wireTypeDef>
</spirit:wireTypeDefs> </spirit:wireTypeDefs>
<spirit:driver> <spirit:driver>
<spirit:defaultValue spirit:format="bitString" <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver> </spirit:driver>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
...@@ -1272,67 +1480,50 @@ ...@@ -1272,67 +1480,50 @@
</spirit:port> </spirit:port>
</spirit:ports> </spirit:ports>
<spirit:modelParameters> <spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
spirit:dataType="integer">
<spirit:name>g_simulation</spirit:name> <spirit:name>g_simulation</spirit:name>
<spirit:displayName>G Simulation</spirit:displayName> <spirit:displayName>G Simulation</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_simulation">0</spirit:value>
spirit:resolve="generated"
spirit:id="MODELPARAM_VALUE.g_simulation">0</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer"> <spirit:modelParameter spirit:dataType="integer">
<spirit:name>g_with_external_clock_input</spirit:name> <spirit:name>g_with_external_clock_input</spirit:name>
<spirit:displayName>G With External Clock Input</spirit:displayName> <spirit:displayName>G With External Clock Input</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_with_external_clock_input">0</spirit:value>
spirit:resolve="generated"
spirit:id="MODELPARAM_VALUE.g_with_external_clock_input">0</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer"> <spirit:modelParameter spirit:dataType="integer">
<spirit:name>g_aux_clks</spirit:name> <spirit:name>g_aux_clks</spirit:name>
<spirit:displayName>G Aux Clks</spirit:displayName> <spirit:displayName>G Aux Clks</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_aux_clks">0</spirit:value>
spirit:resolve="generated"
spirit:id="MODELPARAM_VALUE.g_aux_clks">0</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string"> <spirit:modelParameter spirit:dataType="string">
<spirit:name>g_fabric_iface</spirit:name> <spirit:name>g_fabric_iface</spirit:name>
<spirit:displayName>G Fabric Iface</spirit:displayName> <spirit:displayName>G Fabric Iface</spirit:displayName>
<spirit:value spirit:resolve="generated" <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_fabric_iface">plainfbrc</spirit:value>
spirit:id="MODELPARAM_VALUE.g_fabric_iface">plainfbrc</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string"> <spirit:modelParameter spirit:dataType="string">
<spirit:name>g_dpram_initf</spirit:name> <spirit:name>g_dpram_initf</spirit:name>
<spirit:displayName>G Dpram Initf</spirit:displayName> <spirit:displayName>G Dpram Initf</spirit:displayName>
<spirit:value spirit:resolve="generated" <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_dpram_initf">../../../../bin/wrpc/wrc_phy16.bram</spirit:value>
spirit:id="MODELPARAM_VALUE.g_dpram_initf">../../../../bin/wrpc/wrc_phy16.bram</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer"> <spirit:modelParameter spirit:dataType="integer">
<spirit:name>g_diag_id</spirit:name> <spirit:name>g_diag_id</spirit:name>
<spirit:displayName>G Diag Id</spirit:displayName> <spirit:displayName>G Diag Id</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_id">0</spirit:value>
spirit:resolve="generated"
spirit:id="MODELPARAM_VALUE.g_diag_id">0</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer"> <spirit:modelParameter spirit:dataType="integer">
<spirit:name>g_diag_ver</spirit:name> <spirit:name>g_diag_ver</spirit:name>
<spirit:displayName>G Diag Ver</spirit:displayName> <spirit:displayName>G Diag Ver</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_ver">0</spirit:value>
spirit:resolve="generated"
spirit:id="MODELPARAM_VALUE.g_diag_ver">0</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer"> <spirit:modelParameter spirit:dataType="integer">
<spirit:name>g_diag_ro_vector_width</spirit:name> <spirit:name>g_diag_ro_vector_width</spirit:name>
<spirit:displayName>G Diag Ro Vector Width</spirit:displayName> <spirit:displayName>G Diag Ro Vector Width</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_ro_vector_width">0</spirit:value>
spirit:resolve="generated"
spirit:id="MODELPARAM_VALUE.g_diag_ro_vector_width">0</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer"> <spirit:modelParameter spirit:dataType="integer">
<spirit:name>g_diag_rw_vector_width</spirit:name> <spirit:name>g_diag_rw_vector_width</spirit:name>
<spirit:displayName>G Diag Rw Vector Width</spirit:displayName> <spirit:displayName>G Diag Rw Vector Width</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.g_diag_rw_vector_width">0</spirit:value>
spirit:resolve="generated"
spirit:id="MODELPARAM_VALUE.g_diag_rw_vector_width">0</spirit:value>
</spirit:modelParameter> </spirit:modelParameter>
</spirit:modelParameters> </spirit:modelParameters>
</spirit:model> </spirit:model>
...@@ -2035,7 +2226,7 @@ ...@@ -2035,7 +2226,7 @@
<spirit:file> <spirit:file>
<spirit:name>board/fasec/wrc_board_fasec.vhd</spirit:name> <spirit:name>board/fasec/wrc_board_fasec.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType> <spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_df8d02e3</spirit:userFileType> <spirit:userFileType>CHECKSUM_56627f08</spirit:userFileType>
</spirit:file> </spirit:file>
</spirit:fileSet> </spirit:fileSet>
<spirit:fileSet> <spirit:fileSet>
...@@ -2740,69 +2931,51 @@ ...@@ -2740,69 +2931,51 @@
<spirit:parameter> <spirit:parameter>
<spirit:name>g_simulation</spirit:name> <spirit:name>g_simulation</spirit:name>
<spirit:displayName>G Simulation</spirit:displayName> <spirit:displayName>G Simulation</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_simulation">0</spirit:value>
spirit:resolve="user"
spirit:id="PARAM_VALUE.g_simulation">0</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_with_external_clock_input</spirit:name> <spirit:name>g_with_external_clock_input</spirit:name>
<spirit:displayName>G With External Clock Input</spirit:displayName> <spirit:displayName>G With External Clock Input</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_with_external_clock_input">0</spirit:value>
spirit:resolve="user"
spirit:id="PARAM_VALUE.g_with_external_clock_input">0</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_aux_clks</spirit:name> <spirit:name>g_aux_clks</spirit:name>
<spirit:displayName>G Aux Clks</spirit:displayName> <spirit:displayName>G Aux Clks</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_aux_clks">0</spirit:value>
spirit:resolve="user"
spirit:id="PARAM_VALUE.g_aux_clks">0</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_fabric_iface</spirit:name> <spirit:name>g_fabric_iface</spirit:name>
<spirit:displayName>G Fabric Iface</spirit:displayName> <spirit:displayName>G Fabric Iface</spirit:displayName>
<spirit:value spirit:resolve="user" <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.g_fabric_iface">plainfbrc</spirit:value>
spirit:id="PARAM_VALUE.g_fabric_iface">plainfbrc</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_dpram_initf</spirit:name> <spirit:name>g_dpram_initf</spirit:name>
<spirit:displayName>G Dpram Initf</spirit:displayName> <spirit:displayName>G Dpram Initf</spirit:displayName>
<spirit:value spirit:resolve="user" <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.g_dpram_initf">../../../../bin/wrpc/wrc_phy16.bram</spirit:value>
spirit:id="PARAM_VALUE.g_dpram_initf">../../../../bin/wrpc/wrc_phy16.bram</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_diag_id</spirit:name> <spirit:name>g_diag_id</spirit:name>
<spirit:displayName>G Diag Id</spirit:displayName> <spirit:displayName>G Diag Id</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_id">0</spirit:value>
spirit:resolve="user"
spirit:id="PARAM_VALUE.g_diag_id">0</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_diag_ver</spirit:name> <spirit:name>g_diag_ver</spirit:name>
<spirit:displayName>G Diag Ver</spirit:displayName> <spirit:displayName>G Diag Ver</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_ver">0</spirit:value>
spirit:resolve="user"
spirit:id="PARAM_VALUE.g_diag_ver">0</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_diag_ro_vector_width</spirit:name> <spirit:name>g_diag_ro_vector_width</spirit:name>
<spirit:displayName>G Diag Ro Vector Width</spirit:displayName> <spirit:displayName>G Diag Ro Vector Width</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_ro_vector_width">0</spirit:value>
spirit:resolve="user"
spirit:id="PARAM_VALUE.g_diag_ro_vector_width">0</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>g_diag_rw_vector_width</spirit:name> <spirit:name>g_diag_rw_vector_width</spirit:name>
<spirit:displayName>G Diag Rw Vector Width</spirit:displayName> <spirit:displayName>G Diag Rw Vector Width</spirit:displayName>
<spirit:value spirit:format="long" <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.g_diag_rw_vector_width">0</spirit:value>
spirit:resolve="user"
spirit:id="PARAM_VALUE.g_diag_rw_vector_width">0</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>Component_Name</spirit:name> <spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">wrc_board_fasec_v1_0</spirit:value>
spirit:id="PARAM_VALUE.Component_Name"
spirit:order="1">wrc_board_fasec_v1_0</spirit:value>
</spirit:parameter> </spirit:parameter>
</spirit:parameters> </spirit:parameters>
<spirit:vendorExtensions> <spirit:vendorExtensions>
...@@ -2820,8 +2993,8 @@ ...@@ -2820,8 +2993,8 @@
<xilinx:definitionSource>package_project</xilinx:definitionSource> <xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:vendorDisplayName>CERN BE-CO-HT</xilinx:vendorDisplayName> <xilinx:vendorDisplayName>CERN BE-CO-HT</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://www.ohwr.org/projects/wr-cores/wiki/wrpc_core</xilinx:vendorURL> <xilinx:vendorURL>https://www.ohwr.org/projects/wr-cores/wiki/wrpc_core</xilinx:vendorURL>
<xilinx:coreRevision>3</xilinx:coreRevision> <xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-08-17T15:50:57Z</xilinx:coreCreationDateTime> <xilinx:coreCreationDateTime>2017-11-30T13:45:28Z</xilinx:coreCreationDateTime>
<xilinx:tags> <xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag> <xilinx:tag xilinx:name="user.org:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
<xilinx:tag xilinx:name="CERN:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag> <xilinx:tag xilinx:name="CERN:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
...@@ -2831,18 +3004,12 @@ ...@@ -2831,18 +3004,12 @@
</xilinx:coreExtensions> </xilinx:coreExtensions>
<xilinx:packagingInfo> <xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion> <xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8250889b"/>
xilinx:value="f4b0f601"/> <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="115d9c61"/>
<xilinx:checksum xilinx:scope="memoryMaps" <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5a92504c"/>
xilinx:value="115d9c61"/> <xilinx:checksum xilinx:scope="ports" xilinx:value="6a9e6a93"/>
<xilinx:checksum xilinx:scope="fileGroups" <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c3b40ce5"/>
xilinx:value="0f8cd824"/> <xilinx:checksum xilinx:scope="parameters" xilinx:value="5460d5ef"/>
<xilinx:checksum xilinx:scope="ports"
xilinx:value="2166d522"/>
<xilinx:checksum xilinx:scope="hdlParameters"
xilinx:value="c3b40ce5"/>
<xilinx:checksum xilinx:scope="parameters"
xilinx:value="5460d5ef"/>
</xilinx:packagingInfo> </xilinx:packagingInfo>
</spirit:vendorExtensions> </spirit:vendorExtensions>
</spirit:component> </spirit:component>
board/fasec/wr_fasec_pkg.vhd
View file @ 30363ccd
...@@ -51,17 +51,27 @@ package wr_fasec_pkg is ...@@ -51,17 +51,27 @@ package wr_fasec_pkg is
sfp_rxp_i : in std_logic; sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic; sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1'; sfp_det_i : in std_logic := '1';
sfp_sda_b : inout std_logic; sfp_sda_i : in std_logic;
sfp_scl_b : inout std_logic; sfp_sda_o : out std_logic;
sfp_sda_t : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_t : out std_logic;
sfp_rate_select_o : out std_logic; sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0'; sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic; sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0'; sfp_los_i : in std_logic := '0';
eeprom_scl_b : inout std_logic; eeprom_sda_i : in std_logic;
eeprom_sda_b : inout std_logic; eeprom_sda_o : out std_logic;
eeprom_sda_t : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
eeprom_scl_t : out std_logic;
thermo_id : inout std_logic; thermo_id_i : in std_logic;
thermo_id_o : out std_logic;
thermo_id_t : out std_logic;
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
......
board/fasec/wrc_board_fasec.vhd
View file @ 30363ccd
...@@ -121,8 +121,12 @@ entity wrc_board_fasec is ...@@ -121,8 +121,12 @@ entity wrc_board_fasec is
sfp_rx_p_i : in std_logic; sfp_rx_p_i : in std_logic;
sfp_rx_n_i : in std_logic; sfp_rx_n_i : in std_logic;
sfp_det_i : in std_logic := '1'; sfp_det_i : in std_logic := '1';
sfp_sda_b : inout std_logic; sfp_sda_i : in std_logic;
sfp_scl_b : inout std_logic; sfp_sda_o : out std_logic;
sfp_sda_t : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_t : out std_logic;
sfp_rate_select_o : out std_logic; sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0'; sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic; sfp_tx_disable_o : out std_logic;
...@@ -131,13 +135,19 @@ entity wrc_board_fasec is ...@@ -131,13 +135,19 @@ entity wrc_board_fasec is
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- I2C EEPROM -- I2C EEPROM
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
eeprom_scl_b : inout std_logic; eeprom_sda_i : in std_logic;
eeprom_sda_b : inout std_logic; eeprom_sda_o : out std_logic;
eeprom_sda_t : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
eeprom_scl_t : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Onewire interface -- Onewire interface
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
thermo_id : inout std_logic; thermo_id_i : in std_logic;
thermo_id_o : out std_logic;
thermo_id_t : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- UART -- UART
...@@ -475,17 +485,27 @@ begin -- architecture struct ...@@ -475,17 +485,27 @@ begin -- architecture struct
sfp_rxp_i => sfp_rx_p_i, sfp_rxp_i => sfp_rx_p_i,
sfp_rxn_i => sfp_rx_n_i, sfp_rxn_i => sfp_rx_n_i,
sfp_det_i => sfp_det_i, sfp_det_i => sfp_det_i,
sfp_sda_b => sfp_sda_b, sfp_sda_i => sfp_sda_i,
sfp_scl_b => sfp_scl_b, sfp_sda_o => sfp_sda_o,
sfp_sda_t => sfp_sda_t,
sfp_scl_i => sfp_scl_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_t => sfp_scl_t,
sfp_rate_select_o => sfp_rate_select_o, sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i, sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o, sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i, sfp_los_i => sfp_los_i,
-- --
eeprom_scl_b => eeprom_scl_b, eeprom_sda_i => eeprom_sda_i,
eeprom_sda_b => eeprom_sda_b, eeprom_sda_o => eeprom_sda_o,
eeprom_sda_t => eeprom_sda_t,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
eeprom_scl_t => eeprom_scl_t,
-- --
thermo_id => thermo_id, thermo_id_i => thermo_id_i,
thermo_id_o => thermo_id_o,
thermo_id_t => thermo_id_t,
-- --
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
......
board/fasec/xwrc_board_fasec.vhd
View file @ 30363ccd
...@@ -125,8 +125,12 @@ entity xwrc_board_fasec is ...@@ -125,8 +125,12 @@ entity xwrc_board_fasec is
sfp_rxp_i : in std_logic; sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic; sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1'; sfp_det_i : in std_logic := '1';
sfp_sda_b : inout std_logic; sfp_sda_i : in std_logic;
sfp_scl_b : inout std_logic; sfp_sda_o : out std_logic;
sfp_sda_t : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_t : out std_logic;
sfp_rate_select_o : out std_logic; sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0'; sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic; sfp_tx_disable_o : out std_logic;
...@@ -135,13 +139,19 @@ entity xwrc_board_fasec is ...@@ -135,13 +139,19 @@ entity xwrc_board_fasec is
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- I2C EEPROM -- I2C EEPROM
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
eeprom_scl_b : inout std_logic; eeprom_sda_i : in std_logic;
eeprom_sda_b : inout std_logic; eeprom_sda_o : out std_logic;
eeprom_sda_t : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
eeprom_scl_t : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Onewire interface -- Onewire interface
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
thermo_id : inout std_logic; thermo_id_i : in std_logic;
thermo_id_o : out std_logic;
thermo_id_t : out std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- UART -- UART
...@@ -307,18 +317,6 @@ architecture struct of xwrc_board_fasec is ...@@ -307,18 +317,6 @@ architecture struct of xwrc_board_fasec is
signal dac_dpll_load_p1 : std_logic; signal dac_dpll_load_p1 : std_logic;
signal dac_dpll_data : std_logic_vector(15 downto 0); signal dac_dpll_data : std_logic_vector(15 downto 0);
-- EEPROM
signal eeprom_sda_out : std_logic;
signal eeprom_sda_in : std_logic;
signal eeprom_scl_out : std_logic;
signal eeprom_scl_in : std_logic;
-- SFP EEPROM
signal sfp_sda_out : std_logic;
signal sfp_sda_in : std_logic;
signal sfp_scl_out : std_logic;
signal sfp_scl_in : std_logic;
-- OneWire -- OneWire
signal onewire_in : std_logic_vector(1 downto 0); signal onewire_in : std_logic_vector(1 downto 0);
signal onewire_en : std_logic_vector(1 downto 0); signal onewire_en : std_logic_vector(1 downto 0);
...@@ -498,14 +496,14 @@ begin -- architecture struct ...@@ -498,14 +496,14 @@ begin -- architecture struct
dac_dpll_data_o => dac_dpll_data, dac_dpll_data_o => dac_dpll_data,
phy16_o => phy16_from_wrc, phy16_o => phy16_from_wrc,
phy16_i => phy16_to_wrc, phy16_i => phy16_to_wrc,
scl_o => eeprom_scl_out, scl_o => eeprom_scl_t,
scl_i => eeprom_scl_in, scl_i => eeprom_scl_i,
sda_o => eeprom_sda_out, sda_o => eeprom_sda_t,
sda_i => eeprom_sda_in, sda_i => eeprom_sda_i,
sfp_scl_o => sfp_scl_out, sfp_scl_o => sfp_scl_t,
sfp_scl_i => sfp_scl_in, sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_out, sfp_sda_o => sfp_sda_t,
sfp_sda_i => sfp_sda_in, sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i, sfp_det_i => sfp_det_i,
spi_sclk_o => flash_sclk_o, spi_sclk_o => flash_sclk_o,
spi_ncs_o => flash_ncs_o, spi_ncs_o => flash_ncs_o,
...@@ -569,19 +567,15 @@ begin -- architecture struct ...@@ -569,19 +567,15 @@ begin -- architecture struct
--onewire_in(0) <= onewire_i; --onewire_in(0) <= onewire_i;
--onewire_in(1) <= '1'; --onewire_in(1) <= '1';
thermo_id <= '0' when onewire_en(0) = '1' else 'Z'; thermo_id_t <= '0' when onewire_en(0) = '1' else '1';
onewire_in(0) <= thermo_id; thermo_id_o <= '0';
onewire_in(0) <= thermo_id_i;
onewire_in(1) <= '1'; onewire_in(1) <= '1';
eeprom_scl_b <= '0' when eeprom_scl_out = '0' else 'Z'; eeprom_sda_o <= '0';
eeprom_sda_b <= '0' when eeprom_sda_out = '0' else 'Z'; eeprom_scl_o <= '0';
eeprom_scl_in <= eeprom_scl_b; sfp_sda_o <= '0';
eeprom_sda_in <= eeprom_sda_b; sfp_scl_o <= '0';
sfp_scl_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_sda_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_scl_b;
sfp_sda_in <= sfp_sda_b;
s00_axi_aclk_o <= clk_pll_62m5; s00_axi_aclk_o <= clk_pll_62m5;
......
top/fasec_ref_design/fasec_ref_design.xdc
View file @ 30363ccd
...@@ -20,25 +20,25 @@ set_property IOSTANDARD LVCMOS18 [get_ports pll25dac_cs_n_o] ...@@ -20,25 +20,25 @@ set_property IOSTANDARD LVCMOS18 [get_ports pll25dac_cs_n_o]
set_property PACKAGE_PIN N7 [get_ports pll20dac_cs_n_o] set_property PACKAGE_PIN N7 [get_ports pll20dac_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll20dac_cs_n_o] set_property IOSTANDARD LVCMOS18 [get_ports pll20dac_cs_n_o]
set_property PACKAGE_PIN J14 [get_ports eeprom_sda_b] set_property PACKAGE_PIN J14 [get_ports eeprom_i2c_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_sda_b] set_property IOSTANDARD LVCMOS18 [get_ports eeprom_i2c_sda_io]
set_property SLEW FAST [get_ports eeprom_sda_b] set_property SLEW FAST [get_ports eeprom_i2c_sda_io]
set_property PACKAGE_PIN H14 [get_ports eeprom_scl_b] set_property PACKAGE_PIN H14 [get_ports eeprom_i2c_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_scl_b] set_property IOSTANDARD LVCMOS18 [get_ports eeprom_i2c_scl_io]
set_property SLEW FAST [get_ports eeprom_scl_b] set_property SLEW FAST [get_ports eeprom_i2c_scl_io]
set_property PACKAGE_PIN K10 [get_ports thermo_id] set_property PACKAGE_PIN K10 [get_ports thermo_id_tri_io]
set_property IOSTANDARD LVCMOS18 [get_ports thermo_id] set_property IOSTANDARD LVCMOS18 [get_ports thermo_id_tri_io]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_sda] set_property IOSTANDARD LVCMOS25 [get_ports sfp_i2c_sda_io]
set_property PACKAGE_PIN AB17 [get_ports SFP_sda] set_property PACKAGE_PIN AB17 [get_ports sfp_i2c_sda_io]
set_property PACKAGE_PIN G16 [get_ports SFP_rx_los] set_property PACKAGE_PIN G16 [get_ports SFP_rx_los]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_rx_los] set_property IOSTANDARD LVCMOS18 [get_ports SFP_rx_los]
set_property PACKAGE_PIN V4 [get_ports SFP_rxp] set_property PACKAGE_PIN V4 [get_ports SFP_rxp]
set_property PACKAGE_PIN K15 [get_ports SFP_tx_fault] set_property PACKAGE_PIN K15 [get_ports SFP_tx_fault]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_fault] set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_fault]
set_property PACKAGE_PIN AB16 [get_ports SFP_scl] set_property PACKAGE_PIN AB16 [get_ports sfp_i2c_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_scl] set_property IOSTANDARD LVCMOS25 [get_ports sfp_i2c_scl_io]
set_property PACKAGE_PIN J15 [get_ports SFP_mod_abs] set_property PACKAGE_PIN J15 [get_ports SFP_mod_abs]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_mod_abs] set_property IOSTANDARD LVCMOS18 [get_ports SFP_mod_abs]
set_property PACKAGE_PIN G14 [get_ports sfp_rate_select_o] set_property PACKAGE_PIN G14 [get_ports sfp_rate_select_o]
...@@ -70,3 +70,5 @@ set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[2]}] ...@@ -70,3 +70,5 @@ set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[2]}]
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_sys] set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_sys]
top/fasec_ref_design/system_top.tcl
View file @ 30363ccd
...@@ -156,6 +156,9 @@ proc create_root_design { parentCell } { ...@@ -156,6 +156,9 @@ proc create_root_design { parentCell } {
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
set SFP [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 SFP ] set SFP [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 SFP ]
set eeprom_i2c [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 eeprom_i2c ]
set sfp_i2c [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 sfp_i2c ]
set thermo_id [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 thermo_id ]
# Create ports # Create ports
set areset_n_i [ create_bd_port -dir I areset_n_i ] set areset_n_i [ create_bd_port -dir I areset_n_i ]
...@@ -170,8 +173,6 @@ proc create_root_design { parentCell } { ...@@ -170,8 +173,6 @@ proc create_root_design { parentCell } {
set clk_sys_62m5_p [ create_bd_port -dir O -from 0 -to 0 -type clk clk_sys_62m5_p ] set clk_sys_62m5_p [ create_bd_port -dir O -from 0 -to 0 -type clk clk_sys_62m5_p ]
set dio_oe_n [ create_bd_port -dir O -from 2 -to 0 dio_oe_n ] set dio_oe_n [ create_bd_port -dir O -from 2 -to 0 dio_oe_n ]
set dio_term [ create_bd_port -dir O -from 2 -to 0 dio_term ] set dio_term [ create_bd_port -dir O -from 2 -to 0 dio_term ]
set eeprom_scl_b [ create_bd_port -dir IO eeprom_scl_b ]
set eeprom_sda_b [ create_bd_port -dir IO eeprom_sda_b ]
set pll20dac_cs_n_o [ create_bd_port -dir O pll20dac_cs_n_o ] set pll20dac_cs_n_o [ create_bd_port -dir O pll20dac_cs_n_o ]
set pll25dac_cs_n_o [ create_bd_port -dir O pll25dac_cs_n_o ] set pll25dac_cs_n_o [ create_bd_port -dir O pll25dac_cs_n_o ]
set plldac_din_o [ create_bd_port -dir O plldac_din_o ] set plldac_din_o [ create_bd_port -dir O plldac_din_o ]
...@@ -179,7 +180,6 @@ proc create_root_design { parentCell } { ...@@ -179,7 +180,6 @@ proc create_root_design { parentCell } {
set pps_n [ create_bd_port -dir O -from 0 -to 0 -type clk pps_n ] set pps_n [ create_bd_port -dir O -from 0 -to 0 -type clk pps_n ]
set pps_p [ create_bd_port -dir O -from 0 -to 0 -type clk pps_p ] set pps_p [ create_bd_port -dir O -from 0 -to 0 -type clk pps_p ]
set sfp_rate_select_o [ create_bd_port -dir O sfp_rate_select_o ] set sfp_rate_select_o [ create_bd_port -dir O sfp_rate_select_o ]
set thermo_id [ create_bd_port -dir IO thermo_id ]
# Create instance: axi_uartlite_0, and set properties # Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
...@@ -309,6 +309,14 @@ CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {10} \ ...@@ -309,6 +309,14 @@ CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {10} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \ CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
...@@ -924,6 +932,14 @@ CONFIG.PCW_FCLK_CLK3_BUF.VALUE_SRC {DEFAULT} \ ...@@ -924,6 +932,14 @@ CONFIG.PCW_FCLK_CLK3_BUF.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FPGA_FCLK0_ENABLE.VALUE_SRC {DEFAULT} \ CONFIG.PCW_FPGA_FCLK0_ENABLE.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_IN0.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_IN1.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_IN2.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_IN3.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_OUT0.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_OUT1.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_OUT2.VALUE_SRC {DEFAULT} \
CONFIG.PCW_FTM_CTI_OUT3.VALUE_SRC {DEFAULT} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE.VALUE_SRC {DEFAULT} \ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE.VALUE_SRC {DEFAULT} \
CONFIG.PCW_GPIO_EMIO_GPIO_IO.VALUE_SRC {DEFAULT} \ CONFIG.PCW_GPIO_EMIO_GPIO_IO.VALUE_SRC {DEFAULT} \
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
...@@ -1259,11 +1275,11 @@ CONFIG.CONST_WIDTH {4} \ ...@@ -1259,11 +1275,11 @@ CONFIG.CONST_WIDTH {4} \
connect_bd_intf_net -intf_net ps7_0_axi_periph_1_M00_AXI [get_bd_intf_pins ps7_0_axi_periph_1/M00_AXI] [get_bd_intf_pins wrc_board_fasec_0/s00_axi] connect_bd_intf_net -intf_net ps7_0_axi_periph_1_M00_AXI [get_bd_intf_pins ps7_0_axi_periph_1/M00_AXI] [get_bd_intf_pins wrc_board_fasec_0/s00_axi]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net wrc_board_fasec_0_SFP [get_bd_intf_ports SFP] [get_bd_intf_pins wrc_board_fasec_0/SFP] connect_bd_intf_net -intf_net wrc_board_fasec_0_SFP [get_bd_intf_ports SFP] [get_bd_intf_pins wrc_board_fasec_0/SFP]
connect_bd_intf_net -intf_net wrc_board_fasec_0_eeprom_i2c [get_bd_intf_ports eeprom_i2c] [get_bd_intf_pins wrc_board_fasec_0/eeprom_i2c]
connect_bd_intf_net -intf_net wrc_board_fasec_0_sfp_i2c [get_bd_intf_ports sfp_i2c] [get_bd_intf_pins wrc_board_fasec_0/sfp_i2c]
connect_bd_intf_net -intf_net wrc_board_fasec_0_thermo_id [get_bd_intf_ports thermo_id] [get_bd_intf_pins wrc_board_fasec_0/thermo_id]
# Create port connections # Create port connections
connect_bd_net -net Net [get_bd_ports eeprom_scl_b] [get_bd_pins wrc_board_fasec_0/eeprom_scl_b]
connect_bd_net -net Net1 [get_bd_ports eeprom_sda_b] [get_bd_pins wrc_board_fasec_0/eeprom_sda_b]
connect_bd_net -net Net2 [get_bd_ports thermo_id] [get_bd_pins wrc_board_fasec_0/thermo_id]
connect_bd_net -net areset_n_i_1 [get_bd_ports areset_n_i] [get_bd_pins wrc_board_fasec_0/areset_n_i] connect_bd_net -net areset_n_i_1 [get_bd_ports areset_n_i] [get_bd_pins wrc_board_fasec_0/areset_n_i]
connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In1] connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In1]
connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins wrc_board_fasec_0/uart_rxd_i] connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins wrc_board_fasec_0/uart_rxd_i]
...@@ -1307,90 +1323,90 @@ CONFIG.CONST_WIDTH {4} \ ...@@ -1307,90 +1323,90 @@ CONFIG.CONST_WIDTH {4} \
regenerate_bd_layout -layout_string { regenerate_bd_layout -layout_string {
guistr: "# # String gsaved with Nlview 6.6.5b 2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6 guistr: "# # String gsaved with Nlview 6.6.5b 2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6
# -string -flagsOSRD # -string -flagsOSRD
preplace port sfp_rate_select_o -pg 1 -y 620 -defaultsOSRD preplace port sfp_rate_select_o -pg 1 -y 870 -defaultsOSRD
preplace port DDR -pg 1 -y 50 -defaultsOSRD preplace port DDR -pg 1 -y 480 -defaultsOSRD
preplace port plldac_din_o -pg 1 -y 600 -defaultsOSRD preplace port plldac_din_o -pg 1 -y 810 -defaultsOSRD
preplace port clk_20m_vcxo_i -pg 1 -y 620 -defaultsOSRD preplace port clk_20m_vcxo_i -pg 1 -y 740 -defaultsOSRD
preplace port clk_125m_pllref_n_i -pg 1 -y 700 -defaultsOSRD preplace port clk_125m_pllref_n_i -pg 1 -y 780 -defaultsOSRD
preplace port SFP -pg 1 -y 420 -defaultsOSRD preplace port SFP -pg 1 -y 570 -defaultsOSRD
preplace port thermo_id -pg 1 -y 680 -defaultsOSRD preplace port thermo_id -pg 1 -y 690 -defaultsOSRD
preplace port eeprom_sda_b -pg 1 -y 700 -defaultsOSRD preplace port pll25dac_cs_n_o -pg 1 -y 830 -defaultsOSRD
preplace port eeprom_scl_b -pg 1 -y 660 -defaultsOSRD preplace port pll20dac_cs_n_o -pg 1 -y 850 -defaultsOSRD
preplace port areset_n_i -pg 1 -y 640 -defaultsOSRD preplace port areset_n_i -pg 1 -y 720 -defaultsOSRD
preplace port pll20dac_cs_n_o -pg 1 -y 640 -defaultsOSRD preplace port eeprom_i2c -pg 1 -y 670 -defaultsOSRD
preplace port pll25dac_cs_n_o -pg 1 -y 820 -defaultsOSRD preplace port FIXED_IO -pg 1 -y 510 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 20 -defaultsOSRD preplace port clk_125m_pllref_p_i -pg 1 -y 760 -defaultsOSRD
preplace port clk_125m_gtp_p_i -pg 1 -y 680 -defaultsOSRD preplace port clk_125m_gtp_p_i -pg 1 -y 820 -defaultsOSRD
preplace port clk_125m_pllref_p_i -pg 1 -y 720 -defaultsOSRD preplace port plldac_sclk_o -pg 1 -y 790 -defaultsOSRD
preplace port clk_125m_gtp_n_i -pg 1 -y 660 -defaultsOSRD preplace port clk_125m_gtp_n_i -pg 1 -y 800 -defaultsOSRD
preplace port plldac_sclk_o -pg 1 -y 580 -defaultsOSRD preplace port sfp_i2c -pg 1 -y 650 -defaultsOSRD
preplace portBus clk_ref_125m_p -pg 1 -y 540 -defaultsOSRD preplace portBus clk_ref_125m_p -pg 1 -y 80 -defaultsOSRD
preplace portBus dio_oe_n -pg 1 -y 870 -defaultsOSRD preplace portBus dio_oe_n -pg 1 -y 1210 -defaultsOSRD
preplace portBus pps_n -pg 1 -y 770 -defaultsOSRD preplace portBus pps_n -pg 1 -y 1130 -defaultsOSRD
preplace portBus pps_p -pg 1 -y 750 -defaultsOSRD preplace portBus pps_p -pg 1 -y 1110 -defaultsOSRD
preplace portBus clk_sys_62m5_n -pg 1 -y 490 -defaultsOSRD preplace portBus clk_sys_62m5_n -pg 1 -y 410 -defaultsOSRD
preplace portBus dio_term -pg 1 -y 950 -defaultsOSRD preplace portBus dio_term -pg 1 -y 1290 -defaultsOSRD
preplace portBus clk_sys_62m5_p -pg 1 -y 470 -defaultsOSRD preplace portBus clk_sys_62m5_p -pg 1 -y 390 -defaultsOSRD
preplace portBus clk_ref_125m_n -pg 1 -y 560 -defaultsOSRD preplace portBus clk_ref_125m_n -pg 1 -y 100 -defaultsOSRD
preplace inst util_ds_buf_1 -pg 1 -lvl 6 -y 480 -defaultsOSRD preplace inst util_ds_buf_1 -pg 1 -lvl 6 -y 400 -defaultsOSRD
preplace inst util_ds_buf_2 -pg 1 -lvl 6 -y 580 -defaultsOSRD preplace inst util_ds_buf_2 -pg 1 -lvl 6 -y 90 -defaultsOSRD
preplace inst xlconstant_0 -pg 1 -lvl 6 -y 870 -defaultsOSRD preplace inst xlconstant_0 -pg 1 -lvl 6 -y 1210 -defaultsOSRD
preplace inst xlconstant_1 -pg 1 -lvl 6 -y 950 -defaultsOSRD preplace inst xlconstant_1 -pg 1 -lvl 6 -y 1290 -defaultsOSRD
preplace inst xlconstant_2 -pg 1 -lvl 1 -y 140 -defaultsOSRD preplace inst xlconstant_2 -pg 1 -lvl 1 -y 580 -defaultsOSRD
preplace inst xlconcat_0 -pg 1 -lvl 2 -y 150 -defaultsOSRD preplace inst xlconcat_0 -pg 1 -lvl 2 -y 590 -defaultsOSRD
preplace inst wrc_board_fasec_0 -pg 1 -lvl 5 -y 640 -defaultsOSRD preplace inst wrc_board_fasec_0 -pg 1 -lvl 6 -y 790 -defaultsOSRD
preplace inst ps7_0_axi_periph -pg 1 -lvl 4 -y 190 -defaultsOSRD preplace inst ps7_0_axi_periph -pg 1 -lvl 5 -y 110 -defaultsOSRD
preplace inst axi_uartlite_0 -pg 1 -lvl 5 -y 210 -defaultsOSRD preplace inst axi_uartlite_0 -pg 1 -lvl 6 -y 210 -defaultsOSRD
preplace inst rst_wrc_board_fasec_0_62M -pg 1 -lvl 3 -y 570 -defaultsOSRD preplace inst rst_wrc_board_fasec_0_62M -pg 1 -lvl 3 -y 330 -defaultsOSRD
preplace inst rst_ps7_0_100M -pg 1 -lvl 3 -y 370 -defaultsOSRD preplace inst rst_ps7_0_100M -pg 1 -lvl 3 -y 90 -defaultsOSRD
preplace inst util_ds_buf_0 -pg 1 -lvl 6 -y 760 -defaultsOSRD preplace inst util_ds_buf_0 -pg 1 -lvl 6 -y 1120 -defaultsOSRD
preplace inst ps7_0_axi_periph_1 -pg 1 -lvl 4 -y 550 -defaultsOSRD preplace inst ps7_0_axi_periph_1 -pg 1 -lvl 5 -y 350 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 3 -y 130 -defaultsOSRD preplace inst processing_system7_0 -pg 1 -lvl 4 -y 570 -defaultsOSRD
preplace netloc processing_system7_0_DDR 1 3 4 NJ 50 NJ 50 NJ 50 NJ preplace netloc processing_system7_0_DDR 1 4 3 1180J 480 NJ 480 NJ
preplace netloc xlconstant_1_dout 1 6 1 NJ preplace netloc xlconstant_1_dout 1 6 1 NJ
preplace netloc wrc_board_fasec_0_pll25dac_cs_n_o 1 5 2 1630J 820 NJ preplace netloc wrc_board_fasec_0_pll25dac_cs_n_o 1 6 1 NJ
preplace netloc xlconstant_2_dout 1 1 1 NJ preplace netloc xlconstant_2_dout 1 1 1 NJ
preplace netloc wrc_board_fasec_0_clk_ref_125m_o 1 5 2 1470 30 1840
preplace netloc util_ds_buf_1_OBUF_DS_P 1 6 1 NJ preplace netloc util_ds_buf_1_OBUF_DS_P 1 6 1 NJ
preplace netloc wrc_board_fasec_0_clk_ref_125m_o 1 5 1 1660 preplace netloc clk_125m_gtp_p_i_1 1 0 6 NJ 820 NJ 820 NJ 820 NJ 820 NJ 820 NJ
preplace netloc clk_125m_gtp_p_i_1 1 0 5 -10J 700 NJ 700 NJ 700 NJ 700 1160J preplace netloc wrc_board_fasec_0_SFP 1 6 1 NJ
preplace netloc wrc_board_fasec_0_SFP 1 5 2 NJ 420 NJ
preplace netloc axi_uartlite_0_interrupt 1 1 5 160 270 NJ 270 800J 310 NJ 310 1610
preplace netloc util_ds_buf_0_OBUF_DS_N 1 6 1 NJ preplace netloc util_ds_buf_0_OBUF_DS_N 1 6 1 NJ
preplace netloc processing_system7_0_M_AXI_GP0 1 3 1 820 preplace netloc axi_uartlite_0_interrupt 1 1 6 160 420 NJ 420 NJ 420 1130J 470 NJ 470 1790
preplace netloc clk_20m_vcxo_i_1 1 0 5 10J 670 NJ 670 NJ 670 NJ 670 1120J preplace netloc wrc_board_fasec_0_thermo_id 1 6 1 NJ
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 3 2 820 410 1110 preplace netloc processing_system7_0_M_AXI_GP0 1 4 1 1120
preplace netloc processing_system7_0_M_AXI_GP1 1 3 1 810 preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 3 3 N 130 1190 230 NJ
preplace netloc areset_n_i_1 1 0 5 0J 680 NJ 680 NJ 680 NJ 680 1110J preplace netloc clk_20m_vcxo_i_1 1 0 6 NJ 740 NJ 740 NJ 740 NJ 740 NJ 740 NJ
preplace netloc processing_system7_0_M_AXI_GP1 1 4 1 1170
preplace netloc wrc_board_fasec_0_uart_txd_o 1 6 1 1830
preplace netloc wrc_board_fasec_0_plldac_sclk_o 1 6 1 NJ
preplace netloc util_ds_buf_0_OBUF_DS_P 1 6 1 NJ preplace netloc util_ds_buf_0_OBUF_DS_P 1 6 1 NJ
preplace netloc wrc_board_fasec_0_plldac_sclk_o 1 5 2 1650J 650 2090J preplace netloc processing_system7_0_FCLK_RESET0_N 1 2 3 370 240 NJ 240 1110
preplace netloc wrc_board_fasec_0_uart_txd_o 1 5 1 1660 preplace netloc areset_n_i_1 1 0 6 NJ 720 NJ 720 NJ 720 NJ 720 NJ 720 NJ
preplace netloc processing_system7_0_FCLK_RESET0_N 1 2 2 360 280 770 preplace netloc wrc_board_fasec_0_clk_sys_62m5_o 1 5 2 1490 460 1800
preplace netloc wrc_board_fasec_0_clk_sys_62m5_o 1 5 1 1660 preplace netloc rst_wrc_board_fasec_0_62M_peripheral_aresetn 1 3 3 NJ 370 1140 520 1470J
preplace netloc rst_wrc_board_fasec_0_62M_peripheral_aresetn 1 3 2 820 730 NJ preplace netloc util_ds_buf_2_OBUF_DS_N 1 6 1 NJ
preplace netloc util_ds_buf_2_OBUF_DS_N 1 6 1 2080J preplace netloc clk_125m_gtp_n_i_1 1 0 6 NJ 800 NJ 800 NJ 800 NJ 800 NJ 800 NJ
preplace netloc clk_125m_gtp_n_i_1 1 0 5 NJ 660 NJ 660 NJ 660 780J 690 1130J preplace netloc axi_uartlite_0_tx 1 6 1 1820
preplace netloc axi_uartlite_0_tx 1 5 1 1650 preplace netloc wrc_board_fasec_0_eeprom_i2c 1 6 1 NJ
preplace netloc xlconcat_0_dout 1 2 1 N preplace netloc wrc_board_fasec_0_sfp_i2c 1 6 1 NJ
preplace netloc xlconstant_0_dout 1 6 1 NJ preplace netloc xlconstant_0_dout 1 6 1 NJ
preplace netloc wrc_board_fasec_0_pll20dac_cs_n_o 1 5 2 1610J 670 2120J preplace netloc xlconcat_0_dout 1 2 2 N 590 NJ
preplace netloc processing_system7_0_FIXED_IO 1 3 4 770J 20 NJ 20 NJ 20 NJ preplace netloc wrc_board_fasec_0_pll20dac_cs_n_o 1 6 1 NJ
preplace netloc util_ds_buf_2_OBUF_DS_P 1 6 1 2070J preplace netloc processing_system7_0_FIXED_IO 1 4 3 NJ 510 NJ 510 NJ
preplace netloc wrc_board_fasec_0_sfp_rate_select_o 1 5 2 NJ 660 2110J preplace netloc wrc_board_fasec_0_sfp_rate_select_o 1 6 1 NJ
preplace netloc rst_wrc_board_fasec_0_62M_interconnect_aresetn 1 3 1 780 preplace netloc util_ds_buf_2_OBUF_DS_P 1 6 1 NJ
preplace netloc ps7_0_axi_periph_1_M00_AXI 1 4 1 N preplace netloc rst_wrc_board_fasec_0_62M_interconnect_aresetn 1 3 2 NJ 350 1160
preplace netloc clk_125m_pllref_p_i_1 1 0 5 NJ 720 NJ 720 NJ 720 NJ 720 1140J preplace netloc ps7_0_axi_periph_1_M00_AXI 1 5 1 1480
preplace netloc clk_125m_pllref_n_i_1 1 0 5 -20J 710 NJ 710 NJ 710 NJ 710 1150J preplace netloc clk_125m_pllref_p_i_1 1 0 6 NJ 760 NJ 760 NJ 760 NJ 760 NJ 760 NJ
preplace netloc Net1 1 5 2 NJ 700 NJ preplace netloc wrc_board_fasec_0_plldac_din_o 1 6 1 NJ
preplace netloc Net 1 5 2 NJ 680 2130J preplace netloc processing_system7_0_FCLK_CLK0 1 2 4 350 430 710 430 1150 500 1470J
preplace netloc wrc_board_fasec_0_plldac_din_o 1 5 2 1640J 640 2100J preplace netloc clk_125m_pllref_n_i_1 1 0 6 NJ 780 NJ 780 NJ 780 NJ 780 NJ 780 NJ
preplace netloc processing_system7_0_FCLK_CLK0 1 2 3 350 260 780 70 1110 preplace netloc ps7_0_axi_periph_M00_AXI 1 5 1 1470
preplace netloc ps7_0_axi_periph_M00_AXI 1 4 1 N preplace netloc wrc_board_fasec_0_pps_p_o 1 5 2 1480 1060 1790
preplace netloc wrc_board_fasec_0_pps_p_o 1 5 1 1620 preplace netloc wrc_board_fasec_0_s00_axi_aclk_o 1 2 5 360 890 710 890 1190 890 1490J 490 1810
preplace netloc Net2 1 5 2 1650J 690 2140J
preplace netloc util_ds_buf_1_OBUF_DS_N 1 6 1 NJ preplace netloc util_ds_buf_1_OBUF_DS_N 1 6 1 NJ
preplace netloc wrc_board_fasec_0_s00_axi_aclk_o 1 2 4 340 910 800 910 NJ 910 1610 preplace netloc rst_ps7_0_100M_interconnect_aresetn 1 3 2 N 110 1110J
preplace netloc rst_ps7_0_100M_interconnect_aresetn 1 3 1 790 levelinfo -pg 1 0 90 260 540 910 1330 1640 1860 -top 0 -bot 1340
levelinfo -pg 1 -40 90 250 570 970 1460 1940 2160 -top 0 -bot 1000
", ",
} }
......
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