Skip to content

W
White Rabbit core collection
Commit 35b77aba authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
Browse files
Options

altera: improve Makefile clean rule

parent f9ff1af1
Hide whitespace changes
Inline Side-by-side
Showing with 2 additions and 4 deletions
syn/gsi_exploder/wr_core_demo/Makefile
View file @ 35b77aba
...@@ -10,7 +10,7 @@ all: $(TARGET).sof $(TARGET).jic $(TARGET).rpd ...@@ -10,7 +10,7 @@ all: $(TARGET).sof $(TARGET).jic $(TARGET).rpd
clean: clean:
rm -rf db incremental_db PLLJ_PLLSPE_INFO.txt rm -rf db incremental_db PLLJ_PLLSPE_INFO.txt
rm -f $(TARGET).*.rpt $(TARGET).*.summary $(TARGET).map* $(TARGET).fit.* $(TARGET).pin $(TARGET).jdi $(TARGET)*.qdf $(TARGET).done $(TARGET).qws rm -f $(TARGET).*.rpt $(TARGET).*.summary $(TARGET).map* $(TARGET).fit.* $(TARGET).pin $(TARGET).jdi $(TARGET)*.qdf $(TARGET).done $(TARGET).qws
rm -f $(TARGET).jam $(TARGET).jic $(TARGET).pof $(TARGET).sof $(TARGET).dep rm -f $(TARGET).rpd $(TARGET).jic $(TARGET).pof $(TARGET).sof $(TARGET).dep
%.sof: %.qsf %.sof: %.qsf
$(QUARTUS_BIN)/quartus_map $* $(QUARTUS_BIN)/quartus_map $*
......
syn/gsi_exploder/wr_core_demo/exploder_top.qsf
View file @ 35b77aba
...@@ -433,7 +433,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/co ...@@ -433,7 +433,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/co
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
......
syn/gsi_scu/wr_core_demo/Makefile
View file @ 35b77aba
...@@ -10,7 +10,7 @@ all: $(TARGET).sof $(TARGET).jic $(TARGET).rpd ...@@ -10,7 +10,7 @@ all: $(TARGET).sof $(TARGET).jic $(TARGET).rpd
clean: clean:
rm -rf db incremental_db PLLJ_PLLSPE_INFO.txt rm -rf db incremental_db PLLJ_PLLSPE_INFO.txt
rm -f $(TARGET).*.rpt $(TARGET).*.summary $(TARGET).map* $(TARGET).fit.* $(TARGET).pin $(TARGET).jdi $(TARGET)*.qdf $(TARGET).done $(TARGET).qws rm -f $(TARGET).*.rpt $(TARGET).*.summary $(TARGET).map* $(TARGET).fit.* $(TARGET).pin $(TARGET).jdi $(TARGET)*.qdf $(TARGET).done $(TARGET).qws
rm -f $(TARGET).jam $(TARGET).jic $(TARGET).pof $(TARGET).sof $(TARGET).dep rm -f $(TARGET).rpd $(TARGET).jic $(TARGET).pof $(TARGET).sof $(TARGET).dep
%.sof: %.qsf %.sof: %.qsf
$(QUARTUS_BIN)/quartus_map $* $(QUARTUS_BIN)/quartus_map $*
......
syn/gsi_scu/wr_core_demo/scu.qsf
View file @ 35b77aba
...@@ -832,7 +832,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/co ...@@ -832,7 +832,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/co
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment