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White Rabbit core collection
Commit 376d54ad authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski
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streamers wip

parent 749dee53
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Showing with 261 additions and 127 deletions
.gitignore
View file @ 376d54ad
......@@ -19,3 +19,8 @@ doc/
Makefile
*.xml
xgui/
*.jou
*.log
*.pb
*.str
*.orig
\ No newline at end of file
general-cores @ 5205d975
Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe
ip_cores/general-cores 0 → 120000
View file @ 376d54ad
../../general-cores
\ No newline at end of file
modules/timing/Manifest.py
View file @ 376d54ad
......@@ -3,5 +3,6 @@ files = ["dmtd_phase_meas.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"pulse_stamper.vhd" ]
"pulse_stamper.vhd",
"pulse_stamper_sync.vhd"]
modules/wr_streamers/dropping_buffer.vhd
View file @ 376d54ad
......@@ -58,7 +58,8 @@ entity dropping_buffer is
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
d_req_i : in std_logic;
d_full_o : out std_logic);
end dropping_buffer;
......@@ -104,6 +105,7 @@ begin -- behavioral
full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
d_req_o <= not full;
d_full_o <= full;
p_empty_reg : process(clk_i)
begin
......
modules/wr_streamers/fixed_latency_delay.vhd
View file @ 376d54ad
......@@ -31,7 +31,9 @@ entity fixed_latency_delay is
d_last_i : in std_logic;
d_sync_i : in std_logic;
d_target_ts_en_i : in std_logic;
d_target_ts_i : in std_logic_vector(27 downto 0);
d_target_ts_tai_i : in std_logic_vector(39 downto 0);
d_target_ts_cycles_i : in std_logic_vector(27 downto 0);
d_target_ts_error_i : in std_logic;
d_valid_i : in std_logic;
d_drop_i : in std_logic;
......@@ -81,6 +83,9 @@ architecture rtl of fixed_latency_delay is
signal delay_match : std_logic;
signal delay_miss : std_logic;
signal fifo_target_ts_error : std_logic;
signal fifo_target_ts_tai : std_logic_vector(39 downto 0);
signal fifo_target_ts_cycles : std_logic_vector(27 downto 0);
begin
......@@ -102,8 +107,10 @@ begin
dbuf_d(g_data_width+1) <= d_sync_i;
dbuf_d(g_data_width+2) <= d_target_ts_en_i;
dbuf_d(g_data_width+3+27 downto g_data_width+3) <= d_target_ts_i;
dbuf_d(g_data_width+3+28+39 downto g_data_width+3+28) <= d_target_ts_tai_i;
dbuf_d(g_data_width+3+28+40) <= d_target_ts_error_i;
U_DropBuffer : entity work.dropping_buffer
generic map (
g_size => g_buffer_size,
......@@ -164,7 +171,7 @@ begin
when TS_SETUP_MATCH =>
if fifo_valid = '1' then
if fifo_target_ts_en = '1' then
if fifo_target_ts_en = '1' and fifo_target_ts_error = '0' then
state <= TS_WAIT_MATCH;
else
state <= SEND;
......@@ -208,7 +215,8 @@ begin
clk_i => clk_ref_i,
rst_n_i => rst_n_ref,
arm_i => delay_arm,
ts_origin_i => fifo_target_ts,
ts_tai_i => fifo_target_ts_tai,
ts_cycles_i => fifo_target_ts_cycles,
ts_latency_i => rx_streamer_cfg_i.fixed_latency,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
......@@ -246,7 +254,9 @@ begin
fifo_last <= fifo_q(g_data_width);
fifo_sync <= fifo_q(g_data_width+1);
fifo_target_ts_en <= fifo_q(g_data_width+2);
fifo_target_ts <= fifo_q(g_data_width + 3 + 27 downto g_data_width + 3);
fifo_target_ts_cycles <= fifo_q(g_data_width+3+27 downto g_data_width+3);
fifo_target_ts_tai <= fifo_q(g_data_width+3+28+39 downto g_data_width+3+28);
fifo_target_ts_error <= fifo_q(g_data_width+3+28+40);
rx_data_o <= fifo_data;
rx_valid_o <= rx_valid;
......
modules/wr_streamers/fixed_latency_ts_match.vhd
View file @ 376d54ad
......@@ -15,7 +15,9 @@ entity fixed_latency_ts_match is
rst_n_i : in std_logic;
arm_i : in std_logic;
ts_origin_i : in std_logic_vector(27 downto 0);
ts_tai_i : in std_logic_vector(39 downto 0);
ts_cycles_i : in std_logic_vector(27 downto 0);
ts_latency_i : in std_logic_vector(27 downto 0);
-- Time valid flag
......@@ -53,23 +55,44 @@ architecture rtl of fixed_latency_ts_match is
return 125000000;
end if;
end function;
constant c_rollover_threshold_lo : integer := f_cycles_counter_range / 4;
constant c_rollover_threshold_hi : integer := f_cycles_counter_range * 3 / 4;
signal ts_adjusted : unsigned(28 downto 0);
signal armed : std_logic;
signal ts_adjusted_cycles : unsigned(28 downto 0);
signal ts_adjusted_tai : unsigned(39 downto 0);
signal tm_cycles_scaled : unsigned(28 downto 0);
signal ts_latency_scaled : unsigned(28 downto 0);
signal match : std_logic;
signal tm_cycles_scaled_d : unsigned(28 downto 0);
signal ts_latency_scaled_d : unsigned(28 downto 0);
signal ts_adjusted_d : unsigned(28 downto 0);
signal match, late : std_logic;
signal state : t_state;
signal ts_adj_next_cycle, roll_lo, roll_hi : std_logic;
attribute mark_debug : string;
attribute mark_debug of ts_adjusted_d : signal is "TRUE";
attribute mark_debug of tm_cycles_scaled_d : signal is "TRUE";
attribute mark_debug of ts_latency_scaled_d : signal is "TRUE";
attribute mark_debug of state : signal is "TRUE";
attribute mark_debug of match : signal is "TRUE";
attribute mark_debug of late : signal is "TRUE";
begin
process(clk_i)
begin
if rising_edge(clk_i) then
ts_adjusted_d <= ts_adjusted_cycles;
tm_cycles_scaled_d <= tm_cycles_scaled;
ts_latency_scaled_d <= ts_latency_scaled;
end if;
end process;
process(tm_cycles_i, ts_latency_i)
begin
if g_clk_ref_rate = 62500000 then
......@@ -89,8 +112,7 @@ begin
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
armed <= '0';
late_o <= '0';
late <= '0';
match <= '0';
State <= IDLE;
......@@ -99,54 +121,44 @@ begin
case State is
when IDLE =>
match <= '0';
late_o <= '0';
armed <= '0';
late <= '0';
if arm_i = '1' then
ts_adjusted <= resize(unsigned(ts_origin_i) + unsigned(ts_latency_i), 29);
State <= WRAP_ADJ_TS;
armed <= '1';
ts_adjusted_cycles <= resize(unsigned(ts_cycles_i) + unsigned(ts_latency_i), 29);
ts_adjusted_tai <= resize(unsigned(ts_tai_i), 40);
State <= WRAP_ADJ_TS;
end if;
when WRAP_ADJ_TS =>
ts_adj_next_cycle <= '0';
roll_lo <= '0';
roll_hi <= '0';
if ts_adjusted >= f_cycles_counter_range then
ts_adj_next_cycle <= '1';
ts_adjusted <= ts_adjusted - f_cycles_counter_range;
if ts_adjusted_cycles >= f_cycles_counter_range then
ts_adjusted_cycles <= ts_adjusted_cycles - f_cycles_counter_range;
ts_adjusted_tai <= ts_adjusted_tai + 1;
end if;
if ts_adjusted < c_rollover_threshold_lo then
roll_lo <= '1';
end if;
State <= CHECK_LATE;
if tm_cycles_scaled > c_rollover_threshold_hi then
roll_hi <= '1';
when CHECK_LATE =>
if tm_time_valid_i = '0' then
late <= '1';
state <= IDLE;
end if;
State <= CHECK_LATE;
when CHECK_LATE =>
if roll_lo = '1' and roll_hi = '1' then
if ts_adj_next_cycle = '0' then
late_o <= '1';
State <= IDLE;
else
State <= WAIT_TRIG;
end if;
if ts_adjusted_tai < unsigned(tm_tai_i) then
late <= '1';
State <= IDLE;
elsif ts_adjusted_tai = unsigned(tm_tai_i) and ts_adjusted_cycles <= tm_cycles_scaled then
late <= '1';
State <= IDLE;
else
State <= WAIT_TRIG;
end if;
when WAIT_TRIG =>
if ts_adjusted = tm_cycles_scaled then
if ts_adjusted_cycles = tm_cycles_scaled and ts_adjusted_tai = unsigned(tm_tai_i) then
match <= '1';
State <= IDLE;
end if;
......@@ -157,5 +169,6 @@ begin
end process;
match_o <= match;
late_o <= late;
end rtl;
modules/wr_streamers/xrx_streamer.vhd
View file @ 376d54ad
......@@ -139,6 +139,8 @@ entity xrx_streamer is
rx_latency_o : out std_logic_vector(27 downto 0);
-- 1 when the latency on rx_latency_o is valid.
rx_latency_valid_o : out std_logic;
-- pulse when a frame was dropped due to buffer overflow
rx_overflow_p1_o : out std_logic;
-- received streamer frame (counts all frames, corrupted and not)
rx_frame_p1_o : out std_logic;
-- configuration
......@@ -149,7 +151,7 @@ end xrx_streamer;
architecture rtl of xrx_streamer is
type t_rx_state is (IDLE, HEADER, FRAME_SEQ_ID, PAYLOAD, SUBFRAME_HEADER, EOF);
type t_rx_state is (IDLE, HEADER, FRAME_SEQ_ID, PAYLOAD, EOF, DROP_FRAME);
signal fab, fsm_in : t_pipe;
......@@ -165,18 +167,27 @@ architecture rtl of xrx_streamer is
signal pack_data, fifo_data : std_logic_vector(g_data_width-1 downto 0);
signal fifo_drop, fifo_accept, fifo_accept_d0, fifo_dvalid : std_logic;
signal fifo_drop, fifo_accept, fifo_accept_d0, fifo_dvalid, fifo_full, fifo_dreq : std_logic;
signal fifo_sync, fifo_last, frames_lost, blocks_lost : std_logic;
signal fifo_dout, fifo_din : std_logic_vector(g_data_width + 1 + 28 + 1 downto 0);
attribute mark_debug : string;
attribute mark_debug of fifo_drop : signal is "true";
attribute mark_debug of fifo_accept : signal is "true";
attribute mark_debug of fifo_dvalid : signal is "true";
attribute mark_debug of state : signal is "true";
attribute mark_debug of fsm_in : signal is "true";
attribute mark_debug of fifo_full : signal is "true";
attribute mark_debug of fifo_dreq : signal is "true";
signal fifo_target_ts_en : std_logic;
signal fifo_target_ts : unsigned(27 downto 0);
signal fifo_target_ts : std_logic_vector(28 downto 0);
signal pending_write, fab_dvalid_pre : std_logic;
signal tx_tag_cycles, rx_tag_cycles : std_logic_vector(27 downto 0);
signal tx_tag_valid, rx_tag_valid : std_logic;
signal tx_tag_valid, tx_tag_present, rx_tag_valid : std_logic;
signal rx_tag_valid_stored : std_logic;
signal got_next_subframe : std_logic;
......@@ -195,6 +206,20 @@ architecture rtl of xrx_streamer is
signal fifo_last_int : std_logic;
signal rst_int_n : std_logic;
signal tx_tag_error : std_logic;
signal tx_tag_adj_valid : std_logic;
signal tx_tag_adj_error : std_logic;
signal tx_tag_adj_cycles : std_logic_vector(27 downto 0);
signal tx_tag_adj_tai : std_logic_vector(39 downto 0);
signal fifo_target_ts_tai : std_logic_vector(39 downto 0);
signal fifo_target_ts_cycles : std_logic_vector(27 downto 0);
signal fifo_target_ts_error : std_logic;
signal timestamp_pushed_to_fifo : std_logic;
begin -- rtl
......@@ -268,6 +293,7 @@ begin -- rtl
fab.dreq <= fsm_in.dreq;
is_escape <= '0';
end generate gen_no_escape;
fsm_in.eof <= fab.eof or fab.error;
fsm_in.sof <= fab.sof;
......@@ -306,11 +332,14 @@ begin -- rtl
d_last_i => fifo_last_int,
d_sync_i => fifo_sync,
d_target_ts_en_i => fifo_target_ts_en,
d_target_ts_i => std_logic_vector(fifo_target_ts),
d_target_ts_tai_i => fifo_target_ts_tai,
d_target_ts_cycles_i => fifo_target_ts_cycles,
d_target_ts_error_i => fifo_target_ts_error,
d_valid_i => fifo_dvalid,
d_drop_i => fifo_drop,
d_accept_i => fifo_accept_d0,
d_req_o => fsm_in.dreq,
d_req_o => fifo_dreq,
d_full_o => fifo_full,
rx_first_p1_o => rx_first_p1_o,
rx_last_p1_o => rx_last_p1_o,
rx_data_o => rx_data_o,
......@@ -319,6 +348,36 @@ begin -- rtl
rx_streamer_cfg_i => rx_streamer_cfg_i);
U_RestoreTAITimeFromRXTimestamp : entity work.ts_restore_tai
generic map (
g_tm_sample_period => 20,
g_clk_ref_rate => g_clk_ref_rate,
g_simulation => g_simulation,
g_sim_cycle_counter_range => g_sim_cycle_counter_range)
port map (
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
ts_valid_i => tx_tag_valid,
ts_cycles_i => tx_tag_cycles,
ts_valid_o => tx_tag_adj_valid,
ts_cycles_o => tx_tag_adj_cycles,
ts_error_o => tx_tag_adj_error,
ts_tai_o => tx_tag_adj_tai);
p_gen_fsm_dreq : process(fifo_full, state)
begin
if state = PAYLOAD then
fsm_in.dreq <= not fifo_full;
else
fsm_in.dreq <= '1';
end if;
end process;
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -348,6 +407,8 @@ begin -- rtl
pack_data <= (others=>'0');
is_vlan <= '0';
rx_tag_valid_stored <= '0';
tx_tag_present <= '0';
tx_tag_valid <= '0';
else
case state is
when IDLE =>
......@@ -368,14 +429,25 @@ begin -- rtl
rx_lost_frames_cnt_o <= (others => '0');
frames_lost <= '0';
blocks_lost <= '0';
rx_latency <= (others=>'0');
rx_latency_valid <= '0';
is_vlan <= '0';
rx_tag_valid_stored <= '0';
tx_tag_present <= '0';
tx_tag_valid <= '0';
if(fsm_in.sof = '1') then
state <= HEADER;
if(fifo_full = '1') then
state <= DROP_FRAME;
else
state <= HEADER;
end if;
end if;
when DROP_FRAME =>
if (fsm_in.eof = '1' or fsm_in.error = '1') then
state <= IDLE;
end if;
when HEADER =>
if(fsm_in.eof = '1') then
state <= IDLE;
......@@ -421,12 +493,14 @@ begin -- rtl
count <= count + 1;
when x"07" =>
if(is_vlan = '0') then
tx_tag_valid <= fsm_in.data(15);
tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
tx_tag_present <= fsm_in.data(15);
tx_tag_error <= fsm_in.data(14);
tx_tag_cycles(27 downto 16) <= fsm_in.data(11 downto 0);
end if;
count <= count + 1;
when x"08" =>
if(is_vlan = '0') then
tx_tag_valid <= '1';
tx_tag_cycles(15 downto 0) <= fsm_in.data;
count <= count + 1;
crc_en <= '1';
......@@ -438,10 +512,12 @@ begin -- rtl
end if;
count <= count + 1;
when x"09" =>
tx_tag_valid <= fsm_in.data(15);
tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
tx_tag_present <= fsm_in.data(15);
tx_tag_error <= fsm_in.data(14);
tx_tag_cycles(27 downto 16) <= fsm_in.data(11 downto 0);
count <= count + 1;
when x"0A" =>
tx_tag_valid <= '1';
tx_tag_cycles(15 downto 0) <= fsm_in.data;
count <= count + 1;
crc_en <= '1';
......@@ -465,30 +541,6 @@ begin -- rtl
ser_count <= (others => '0');
word_count <= word_count + 1; -- count words, increment in advance
got_next_subframe <= '1';
fifo_target_ts_en <= '0';
fifo_target_ts <= unsigned(tx_tag_cycles);
if(tx_tag_valid = '1' and unsigned(rx_streamer_cfg_i.fixed_latency) /= 0) then
fifo_target_ts_en <= '1';
end if;
-- latency measurement
if(tx_tag_valid = '1' and rx_tag_valid_stored = '1') then
rx_latency_valid <= '1';
if(unsigned(tx_tag_cycles) > unsigned(rx_tag_cycles)) then
rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles) + to_unsigned(125000000, 28);
else
rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles);
end if;
tx_tag_valid <= '0';
else
rx_latency_valid <= '0';
end if;
rx_tag_valid_stored <= '0';
if(std_logic_vector(seq_no) /= fsm_in.data(14 downto 0)) then
seq_no <= unsigned(fsm_in.data(14 downto 0))+1;
......@@ -507,37 +559,9 @@ begin -- rtl
end if;
end if;
when SUBFRAME_HEADER =>
if fifo_dvalid = '1' then
fifo_target_ts_en <= '0';
end if;
fifo_drop <= '0';
fifo_accept <= '0';
ser_count <= (others => '0');
if(fsm_in.eof = '1') then
state <= IDLE;
got_next_subframe <= '0';
blocks_lost <= '0';
elsif (fsm_in.dvalid = '1' and is_escape = '1') then
got_next_subframe <= '1';
if(std_logic_vector(count) /= fsm_in.data(14 downto 0)) then
count <= unsigned(fsm_in.data(14 downto 0))+1;
blocks_lost <= '1';
else
count <= count + 1;
blocks_lost <= '0';
end if;
state <= PAYLOAD;
end if;
when PAYLOAD =>
if fifo_dvalid = '1' then
fifo_target_ts_en <= '0';
end if;
frames_lost <= '0';
rx_lost_frames_cnt_o <= (others => '0');
rx_latency_valid <= '0';
......@@ -581,6 +605,8 @@ begin -- rtl
state <= EOF;
fifo_accept <= crc_match; --_latched;
fifo_drop <= not crc_match; --_latched;
fifo_dvalid <= pending_write and not fifo_dvalid;
else
blocks_lost <= '0';
......@@ -618,6 +644,7 @@ begin -- rtl
fifo_accept <= '1';
fifo_drop <= '0';
fifo_dvalid <= '1';
else
word_count <= word_count + 1;
end if;
......@@ -653,7 +680,58 @@ begin -- rtl
end if;
end process;
p_delay_fifo_accept : process(clk_sys_i)
p_handle_latency : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_int_n = '0' then
fifo_target_ts_en <= '0';
rx_latency_valid <= '0';
rx_tag_valid_stored <= '0';
timestamp_pushed_to_fifo <= '0';
else
case state is
when IDLE =>
timestamp_pushed_to_fifo <= '0';
when PAYLOAD =>
if(timestamp_pushed_to_fifo = '0' and tx_tag_adj_valid = '1' and tx_tag_present = '1' and unsigned(rx_streamer_cfg_i.fixed_latency) /= 0) then
fifo_target_ts_cycles <= tx_tag_adj_cycles;
fifo_target_ts_tai <= tx_tag_adj_tai;
fifo_target_ts_error <= tx_tag_adj_error or tx_tag_error;
fifo_target_ts_en <= '1';
end if;
if fifo_dvalid = '1' and fifo_target_ts_en = '1' then
timestamp_pushed_to_fifo <= '1';
end if;
-- latency measurement
if(tx_tag_present = '1' and rx_tag_valid_stored = '1') then
rx_latency_valid <= '1';
if(unsigned(tx_tag_cycles) > unsigned(rx_tag_cycles)) then
rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles) + to_unsigned(125000000, 28);
else
rx_latency <= unsigned(rx_tag_cycles) - unsigned(tx_tag_cycles);
end if;
else
rx_latency_valid <= '0';
end if;
rx_tag_valid_stored <= '0';
when others => null;
end case;
end if;
end if;
end process;
p_delay_signals : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
fifo_accept_d0 <= fifo_accept;
......
modules/wr_streamers/xtx_streamer.vhd
View file @ 376d54ad
......@@ -204,8 +204,17 @@ architecture rtl of xtx_streamer is
signal link_ok_delay_expired : std_logic;
signal link_ok_delay_expired_ref : std_logic;
signal link_ok_ref : std_logic;
signal clk_data : std_logic;
attribute mark_debug : string;
attribute mark_debug of link_ok_delay_cnt : signal is "true";
attribute mark_debug of link_ok_delay_expired_ref : signal is "true";
attribute mark_debug of link_ok_delay_expired : signal is "true";
attribute mark_debug of link_ok_ref : signal is "true";
signal clk_data : std_logic;
signal rst_n_ref : std_logic;
signal stamper_pulse_a : std_logic;
......@@ -413,20 +422,21 @@ begin -- rtl
tx_fifo_last <= tx_fifo_q(g_data_width);
U_Timestamper : pulse_stamper
U_Timestamper : entity work.pulse_stamper_sync
generic map(
g_ref_clk_rate => g_clk_ref_rate)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_int_n,
pulse_a_i => stamper_pulse_a,
pulse_i => stamper_pulse_a,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_tai_i,
tm_cycles_i => tm_cycles_i,
tag_tai_o => open,
tag_cycles_o => tag_cycles,
tag_valid_o => tag_valid);
tag_valid_o => tag_valid,
tag_error_o => tag_error);
buf_frame_count_inc_ref <= tx_fifo_we and tx_last_p1_i;
buf_frame_count_dec_sys <= tx_fifo_rd and tx_fifo_last;
......@@ -563,7 +573,12 @@ begin -- rtl
when x"07" =>
if(tx_streamer_cfg_i.qtag_ena = '0') then
fsm_out.data <= "1000" & tag_cycles(27 downto 16);
if tag_error = '1' then
fsm_out.data <= x"ffff";
else
fsm_out.data <= "1000" & tag_cycles(27 downto 16);
end if;
if tag_valid_latched = '1' then
count <= count + 1;
fsm_out.dvalid <= '1';
......@@ -589,7 +604,13 @@ begin -- rtl
else
fsm_out.dvalid <= '0';
end if;
fsm_out.data <= "1000" & tag_cycles(27 downto 16);
if tag_error = '1' then
fsm_out.data <= x"ffff";
else
fsm_out.data <= "1000" & tag_cycles(27 downto 16);
end if;
when x"0A" =>
fsm_out.data <= tag_cycles(15 downto 0);
state <= FRAME_SEQ_ID;
......
modules/wr_streamers/xwr_streamers.vhd
View file @ 376d54ad
......@@ -99,7 +99,8 @@ entity xwr_streamers is
-----------------------------------------------------------------------------------------
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE;
g_simulation : integer := 0
g_simulation : integer := 0;
g_sim_cycle_counter_range : integer := 125000
);
port (
......@@ -227,7 +228,7 @@ begin
-- Instantiate transmission streamer, if configured to do so
-------------------------------------------------------------------------------------------
gen_tx: if(g_streamers_op_mode=TX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
U_TX: xtx_streamer
U_TX: entity work.xtx_streamer
generic map(
g_data_width => g_tx_streamer_params.data_width,
g_tx_buffer_size => g_tx_streamer_params.buffer_size,
......@@ -268,13 +269,16 @@ begin
-- -- Instantiate reception streamer, if configured to do so
-------------------------------------------------------------------------------------------
gen_rx: if(g_streamers_op_mode=RX_ONLY OR g_streamers_op_mode=TX_AND_RX) generate
U_RX: xrx_streamer
U_RX: entity work.xrx_streamer
generic map(
g_data_width => g_rx_streamer_params.data_width,
g_buffer_size => g_rx_streamer_params.buffer_size,
g_escape_code_disable => g_rx_streamer_params.escape_code_disable,
g_expected_words_number => g_rx_streamer_params.expected_words_number,
g_clk_ref_rate => g_clk_ref_rate
g_clk_ref_rate => g_clk_ref_rate,
g_simulation => g_simulation,
g_sim_cycle_counter_range => g_sim_cycle_counter_range,
g_use_ref_clock_for_data => g_use_ref_clock_for_data
)
port map(
clk_sys_i => clk_sys_i,
......
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