Commit 38623a1a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

update

parent 423d90cc
modules = {"local" :
[ "platform/xilinx/wr_gtp_phy",
"modules/timing",
"modules/wr_mini_nic",
"modules/wr_softpll",
"modules/wrc_lm32",
"modules/wrc_core",
"modules/wrsw_endpoint",
"modules/wrsw_pps_gen" ]}
\ No newline at end of file
files = ["dmtd_phase_meas.vhd",
"dmtd_with_deglitcher.vhd",
"multi_dmtd_with_deglitcher.vhd" ]
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd" ]
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-04-18
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -45,7 +45,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.common_components.all;
use work.gencores_pkg.all;
entity dmtd_phase_meas is
generic (
......@@ -83,19 +83,17 @@ architecture syn of dmtd_phase_meas is
generic (
g_counter_bits : natural);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p_o : out std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_thr_lo_i : in std_logic_vector(11 downto 0);
deglitch_thr_hi_i : in std_logic_vector(11 downto 0);
deglitch_thr_glitch_i : in std_logic_vector(7 downto 0);
dbg_dmtdout_o : out std_logic);
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_in_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_threshold_i : in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p1_o : out std_logic);
end component;
type t_pd_state is (PD_WAIT_TAG, PD_WAIT_A, PD_WAIT_B);
......@@ -128,7 +126,7 @@ begin -- syn
rst_n_sysclk <= rst_n_i;
-- reset sync for DMTD sampling clock
sync_reset_dmtdclk : sync_ffs
sync_reset_dmtdclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -149,12 +147,10 @@ begin -- syn
clk_sys_i => clk_sys_i,
clk_in_i => clk_a_i,
tag_o => tag_a,
tag_stb_p_o => tag_a_p,
tag_stb_p1_o => tag_a_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => std_logic_vector(to_unsigned(g_deglitch_thr_lo, 12)),
deglitch_thr_hi_i => std_logic_vector(to_unsigned(g_deglitch_thr_hi, 12)),
deglitch_thr_glitch_i => std_logic_vector(to_unsigned(g_deglitch_thr_glitch, 8)),
deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
dbg_dmtdout_o => open);
DMTD_B : dmtd_with_deglitcher
......@@ -167,12 +163,10 @@ begin -- syn
clk_sys_i => clk_sys_i,
clk_in_i => clk_b_i,
tag_o => tag_b,
tag_stb_p_o => tag_b_p,
tag_stb_p1_o => tag_b_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => std_logic_vector(to_unsigned(g_deglitch_thr_lo, 12)),
deglitch_thr_hi_i => std_logic_vector(to_unsigned(g_deglitch_thr_hi, 12)),
deglitch_thr_glitch_i => std_logic_vector(to_unsigned(g_deglitch_thr_glitch, 8)),
deglitch_threshold_i => std_logic_vector(to_unsigned(g_deglitcher_threshold, 16)),
dbg_dmtdout_o => open);
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-04-18
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -46,7 +46,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.common_components.all;
use work.gencores_pkg.all;
entity dmtd_with_deglitcher is
generic (
......@@ -83,13 +83,13 @@ entity dmtd_with_deglitcher is
deglitch_threshold_i : in std_logic_vector(15 downto 0);
-- [clk_dmtd_i] raw DDMTD output (for debugging purposes)
dbg_dmtdout_o : out std_logic
dbg_dmtdout_o : out std_logic;
-- [clk_sys_i] deglitched edge tag value
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
-- [clk_sys_i] pulse indicates new phase tag on tag_o
tag_stb_p1_o : out std_logic;
tag_stb_p1_o : out std_logic
);
end dmtd_with_deglitcher;
......@@ -147,7 +147,7 @@ begin -- rtl
case state is
when WAIT_STABLE_0 => -- out-of-sync
new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length downto 1);
new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length-1 downto 1);
if clk_i_d3 /= '0' then
stab_cntr <= (others => '0');
......@@ -184,9 +184,9 @@ begin -- rtl
end case;
end if;
end if;
end process deglitch;
end process p_deglitch;
U_sync_tag_strobe : sync_ffs
U_sync_tag_strobe : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -197,7 +197,7 @@ begin -- rtl
npulse_o => open,
ppulse_o => new_edge_p);
tag_stb_p_o <= new_edge_p;
tag_stb_p1_o <= new_edge_p;
tag_o <= std_logic_vector(tag_int);
dbg_dmtdout_o <= clk_i_d3;
end rtl;
......@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.common_components.all;
use work.gencores_pkg.all;
entity multi_dmtd_with_deglitcher is
generic (
......@@ -195,7 +195,7 @@ begin -- rtl
--n_zeroes <= f_count_zeroes(dmtd_in);
sync_reset_refclk : sync_ffs
sync_reset_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......
files = [ "minic_packet_buffer.vhd",
"minic_wb_slave.vhd",
"wr_mini_nic.vhd",
"wr_minic_ep_combo.vhd"];
"wr_mini_nic.vhd" ];
......@@ -13,8 +13,8 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library wbgen2;
use wbgen2.wbgen2_pkg.all;
use work.wbgen2_pkg.all;
entity minic_wb_slave is
port (
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2011-03-27
-- Last update: 2011-05-11
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -29,7 +29,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global_defs.all;
use work.endpoint_pkg.all;
entity wr_mini_nic is
......@@ -56,7 +56,7 @@ entity wr_mini_nic is
-------------------------------------------------------------------------------
src_data_o : out std_logic_vector(15 downto 0);
src_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
src_ctrl_o : out std_logic_vector(4 - 1 downto 0);
src_bytesel_o : out std_logic;
src_sof_p1_o : out std_logic;
src_eof_p1_o : out std_logic;
......@@ -66,7 +66,7 @@ entity wr_mini_nic is
src_error_p1_i : in std_logic;
snk_data_i : in std_logic_vector(15 downto 0);
snk_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
snk_ctrl_i : in std_logic_vector(4 - 1 downto 0);
snk_bytesel_i : in std_logic;
snk_sof_p1_i : in std_logic;
snk_eof_p1_i : in std_logic;
......@@ -80,8 +80,8 @@ entity wr_mini_nic is
-------------------------------------------------------------------------------
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_i : in std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
......
......@@ -13,8 +13,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library wbgen2;
use wbgen2.wbgen2_pkg.all;
use work.wbgen2_pkg.all;
entity softpll_wb is
port (
......
......@@ -2,8 +2,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common_components.all;
use work.gencores_pkg.all;
entity wr_softpll is
generic(
......@@ -63,21 +62,19 @@ architecture rtl of wr_softpll is
generic (
g_counter_bits : natural);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p_o : out std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_thr_lo_i : in std_logic_vector(11 downto 0);
deglitch_thr_hi_i : in std_logic_vector(11 downto 0);
deglitch_thr_glitch_i : in std_logic_vector(7 downto 0);
dbg_dmtdout_o : out std_logic);
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_in_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_threshold_i : in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p1_o : out std_logic);
end component;
component softpll_wb
port (
rst_n_i : in std_logic;
......@@ -174,7 +171,7 @@ architecture rtl of wr_softpll is
begin -- rtl
sync_ffs_rst1 : sync_ffs
sync_ffs_rst1 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -185,7 +182,7 @@ begin -- rtl
npulse_o => open,
ppulse_o => open);
sync_ffs_rst2 : sync_ffs
sync_ffs_rst2 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -196,7 +193,7 @@ begin -- rtl
npulse_o => open,
ppulse_o => open);
sync_ffs_rst3 : sync_ffs
sync_ffs_rst3 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
......@@ -266,12 +263,10 @@ begin -- rtl
clk_in_i => clk_rx_buf,
tag_o => tag_ref,
tag_stb_p_o => tag_ref_p,
tag_stb_p1_o => tag_ref_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => deglitch_thr_slv(11 downto 0),
deglitch_thr_hi_i => "000000000000",
deglitch_thr_glitch_i => "00000000",
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
DMTD_FB : dmtd_with_deglitcher
......@@ -286,12 +281,11 @@ begin -- rtl
clk_in_i => clk_ref_buf,
tag_o => tag_fb,
tag_stb_p_o => tag_fb_p,
tag_stb_p1_o => tag_fb_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_thr_lo_i => deglitch_thr_slv(11 downto 0),
deglitch_thr_hi_i => "000000000000",
deglitch_thr_glitch_i => "00000000",
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
end generate gen_with_single_dmtd;
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2011-04-18
-- Last update: 2011-05-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -32,7 +32,6 @@ use ieee.std_logic_1164.all;
library work;
use work.wrcore_pkg.all;
use work.global_defs.all;
use work.wbconmax_pkg.all;
entity wr_core is
......@@ -140,99 +139,6 @@ end wr_core;
architecture struct of wr_core is
component wr_helper_pll
generic (
g_num_ref_inputs : integer := 1;
g_with_wishbone : integer := 1;
g_dacval_bits : integer := 16;
g_output_bias : integer := 32767;
g_div_ref : integer := 0;
g_div_fb : integer := 0;
g_kp_freq : integer := 0;
g_ki_freq : integer := 0;
g_kp_phase : integer := 0;
g_ki_phase : integer := 0;
g_ld_threshold : integer := 0;
g_ld_samples : integer := 0;
g_fd_gating : integer := 0;
g_pd_gating : integer := 0;
g_ferr_setpoint : integer := 0);
port (
rst_n_i : in std_logic;
cfg_enable_i : in std_logic;
cfg_force_freq_i : in std_logic;
cfg_clear_status_i : in std_logic;
cfg_refsel_i : in std_logic_vector(1 downto 0);
stat_flock_o : out std_logic;
stat_plock_o : out std_logic;
stat_lock_lost_o : out std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_sys_i : in std_logic;
clk_fbck_i : in std_logic;
dac_data_o : out std_logic_vector(g_dacval_bits-1 downto 0);
dac_load_p1_o : out std_logic;
auxout1_o : out std_logic;
auxout2_o : out std_logic;
auxout3_o : out std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component wr_dmtd_pll
generic (
g_num_ref_inputs : integer := 1;
g_with_debug_fifo : integer := 0;
g_with_wishbone : integer := 1;
g_dacval_bits : integer := 16;
g_output_bias : integer := 32767;
g_kp_freq : integer := 0;
g_ki_freq : integer := 0;
g_kp_phase : integer := 0;
g_ki_phase : integer := 0;
g_ld_threshold : integer := 0;
g_ld_samples : integer := 0;
g_ref_gthr_lo : integer := 0;
g_ref_gthr_hi : integer := 0;
g_ref_gthr_glitch : integer := 0;
g_fb_gthr_lo : integer := 0;
g_fb_gthr_hi : integer := 0;
g_fb_gthr_glitch : integer := 0;
g_pshifter_speed : integer := 0);
port (
rst_n_i : in std_logic;
cfg_enable_i : in std_logic;
cfg_force_freq_i : in std_logic;
cfg_clear_status_i : in std_logic;
cfg_pshift_load_p1_i : in std_logic;
cfg_pshift_val_i : in std_logic_vector(23 downto 0);
stat_flock_o : out std_logic;
stat_plock_o : out std_logic;
stat_lock_lost_o : out std_logic;
stat_pshift_busy_o : out std_logic;
clk_sys_i : in std_logic;
clk_fbck_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
dac_data_o : out std_logic_vector(g_dacval_bits-1 downto 0);
dac_load_p1_o : out std_logic;
auxout1_o : out std_logic;
auxout2_o : out std_logic;
auxout3_o : out std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
signal s_rst : std_logic;
......@@ -257,7 +163,7 @@ architecture struct of wr_core is
--Endpoint
-----------------------------------------------------------------------------
signal s_ep_rx_data_o : std_logic_vector(15 downto 0);
signal s_ep_rx_ctrl_o : std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
signal s_ep_rx_ctrl_o : std_logic_vector(4 - 1 downto 0);
signal s_ep_rx_bytesel_o : std_logic;
signal s_ep_rx_sof_p1_o : std_logic;
signal s_ep_rx_eof_p1_o : std_logic;
......@@ -266,7 +172,7 @@ architecture struct of wr_core is
signal s_ep_rx_rerror_p1_o : std_logic;
signal s_ep_tx_data_i : std_logic_vector(15 downto 0);
signal s_ep_tx_ctrl_i : std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
signal s_ep_tx_ctrl_i : std_logic_vector(4 - 1 downto 0);
signal s_ep_tx_bytesel_i : std_logic;
signal s_ep_tx_sof_p1_i : std_logic;
signal s_ep_tx_eof_p1_i : std_logic;
......@@ -275,9 +181,8 @@ architecture struct of wr_core is
signal s_ep_tx_terror_p1_o : std_logic;
signal txtsu_port_id_o : std_logic_vector(4 downto 0);
signal txtsu_frame_id_o : std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
signal txtsu_tsval_o : std_logic_vector(c_wrsw_timestamp_size_r +
c_wrsw_timestamp_size_f - 1 downto 0);
signal txtsu_frame_id_o : std_logic_vector(16 -1 downto 0);
signal txtsu_tsval_o : std_logic_vector(28 + 4 - 1 downto 0);
signal txtsu_valid_o : std_logic;
signal txtsu_ack_i : std_logic;
......@@ -432,6 +337,7 @@ begin
wb_ack_o => ppsg_wb_o.ack,
-- Single-pulse PPS output for synchronizing endpoint to
pps_in_i => '0',
pps_csync_o => s_pps_csync,
pps_out_o => pps_p_o
);
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-15
-- Last update: 2011-04-07
-- Last update: 2011-05-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -73,7 +73,7 @@ begin
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
-- g_init_file => g_init_file,
g_dual_clock => g_dual_clock
)
port map(
......
......@@ -2,8 +2,6 @@ library ieee;
use ieee.std_logic_1164.all;
library work;
use work.global_defs.all;
use work.wrczpu_pkg.all;
use work.genram_pkg.all;
use work.wbconmax_pkg.all;
......@@ -23,29 +21,25 @@ package wrcore_pkg is
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
component wrsw_pps_gen is
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Single-pulse PPS output for synchronizing endpoint to
pps_csync_o : out std_logic;
pps_out_o : out std_logic
);
component wrsw_pps_gen
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic);
end component;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--WR Endpoint
-----------------------------------------------------------------------------
component wrsw_endpoint is
......@@ -83,7 +77,7 @@ package wrcore_pkg is
gtp_loopen_o : out std_logic;
--WRF Source
rx_data_o : out std_logic_vector(15 downto 0);
rx_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
rx_ctrl_o : out std_logic_vector(4 - 1 downto 0);
rx_bytesel_o : out std_logic;
rx_sof_p1_o : out std_logic;
rx_eof_p1_o : out std_logic;
......@@ -94,7 +88,7 @@ package wrcore_pkg is
rx_rerror_p1_o : out std_logic;
--WRF Sink
tx_data_i : in std_logic_vector(15 downto 0);
tx_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
tx_ctrl_i : in std_logic_vector(4 -1 downto 0);
tx_bytesel_i : in std_logic;
tx_sof_p1_i : in std_logic;
tx_eof_p1_i : in std_logic;
......@@ -105,19 +99,19 @@ package wrcore_pkg is
tx_terror_p1_o : out std_logic;
--TXTSU
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_frame_id_o : out std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_o : out std_logic_vector(c_wrsw_timestamp_size_r + c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_o : out std_logic;
txtsu_ack_i : in std_logic;
--RTU
rtu_full_i : in std_logic;
rtu_almost_full_i : in std_logic;
rtu_rq_strobe_p1_o : out std_logic;
rtu_rq_smac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(c_wrsw_vid_width - 1 downto 0);
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
rtu_rq_has_vid_o : out std_logic;
rtu_rq_prio_o : out std_logic_vector(c_wrsw_prio_width-1 downto 0);
rtu_rq_prio_o : out std_logic_vector(3-1 downto 0);
rtu_rq_has_prio_o : out std_logic;
--WB
wb_cyc_i : in std_logic;
......@@ -194,7 +188,7 @@ package wrcore_pkg is
mem_wr_o : out std_logic;
-- WRF source/sink
src_data_o : out std_logic_vector(15 downto 0);
src_ctrl_o : out std_logic_vector(c_wrsw_ctrl_size - 1 downto 0);
src_ctrl_o : out std_logic_vector(4 - 1 downto 0);
src_bytesel_o : out std_logic;
src_sof_p1_o : out std_logic;
src_eof_p1_o : out std_logic;
......@@ -204,7 +198,7 @@ package wrcore_pkg is
src_error_p1_i : in std_logic;
snk_data_i : in std_logic_vector(15 downto 0);
snk_ctrl_i : in std_logic_vector(c_wrsw_ctrl_size -1 downto 0);
snk_ctrl_i : in std_logic_vector(4 -1 downto 0);
snk_bytesel_i : in std_logic;
snk_sof_p1_i : in std_logic;
snk_eof_p1_i : in std_logic;
......@@ -214,9 +208,8 @@ package wrcore_pkg is
snk_error_p1_i : in std_logic;
-- TXTSU i/f
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(c_wrsw_oob_frame_id_size -1 downto 0);
txtsu_tsval_i : in std_logic_vector(c_wrsw_timestamp_size_r +
c_wrsw_timestamp_size_f - 1 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 -1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
--WB
......@@ -232,6 +225,7 @@ package wrcore_pkg is
);
end component;
constant maxAddrBitIncIO : integer := 10;
component wrc_zpu
generic (
......
files = [ "wrc_lm32.vhd", "lm32_top.v" ];
\ No newline at end of file
files = [ "wrc_lm32.vhd",
"lm32_cpu.v",
"lm32_addsub.v",
"lm32_top.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_interrupt.v",
"lm32_dp_ram.v"
];
\ No newline at end of file
......@@ -2,11 +2,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.global_defs.all;
package endpoint_pkg is
constant c_endpoint_rx_buffer_size : integer := 4096;
constant c_endpoint_rx_buffer_size_log2 : integer := 12;
......@@ -34,6 +31,19 @@ package endpoint_pkg is
constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
constant c_WRF_OOB : std_logic_vector(1 downto 0) := "01";
-- fixme: remove these along with the non-WB version of the endpoint
constant c_wrsw_ctrl_none : std_logic_vector(4 - 1 downto 0) := x"0";
constant c_wrsw_ctrl_dst_mac : std_logic_vector(4 - 1 downto 0) := x"1";
constant c_wrsw_ctrl_src_mac : std_logic_vector(4 - 1 downto 0) := x"2";
constant c_wrsw_ctrl_ethertype : std_logic_vector(4 - 1 downto 0) := x"3";
constant c_wrsw_ctrl_vid_prio : std_logic_vector(4 - 1 downto 0) := x"4";
constant c_wrsw_ctrl_tx_oob : std_logic_vector(4 - 1 downto 0) := x"5";
constant c_wrsw_ctrl_rx_oob : std_logic_vector(4 - 1 downto 0) := x"6";
constant c_wrsw_ctrl_payload : std_logic_vector(4 - 1 downto 0) := x"7";
constant c_wrsw_ctrl_fcs : std_logic_vector(4 - 1 downto 0) := x"8";