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White Rabbit core collection
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White Rabbit core collection
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38f77982
Commit
38f77982
authored
Dec 14, 2017
by
Grzegorz Daniluk
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platform/xilinx: tx_locked_o also for other families
parent
dcf516c0
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2 changed files
with
5 additions
and
1 deletion
+5
-1
wr_xilinx_pkg.vhd
platform/xilinx/wr_xilinx_pkg.vhd
+1
-0
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+4
-1
No files found.
platform/xilinx/wr_xilinx_pkg.vhd
View file @
38f77982
...
...
@@ -27,6 +27,7 @@ package wr_xilinx_pkg is
clk_62m5_sys_i
:
in
std_logic
:
=
'0'
;
clk_sys_locked_i
:
in
std_logic
:
=
'1'
;
clk_125m_ref_i
:
in
std_logic
:
=
'0'
;
clk_ref_locked_i
:
in
std_logic
:
=
'1'
;
clk_125m_ext_i
:
in
std_logic
:
=
'0'
;
clk_ext_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_stopped_i
:
in
std_logic
:
=
'0'
;
...
...
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
38f77982
...
...
@@ -100,6 +100,7 @@ entity xwrc_platform_xilinx is
clk_sys_locked_i
:
in
std_logic
:
=
'1'
;
-- 125MHz Reference clock
clk_125m_ref_i
:
in
std_logic
:
=
'0'
;
clk_ref_locked_i
:
in
std_logic
:
=
'1'
;
-- 125MHz derived from 10MHz external reference and lock status
-- (when g_with_external_clock_input = TRUE)
clk_125m_ext_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -235,6 +236,7 @@ begin -- architecture rtl
clk_62m5_sys_o
<=
clk_sys_out
;
clk_125m_ref_o
<=
clk_125m_pllref_buf
;
pll_locked_o
<=
pll_sys_locked
and
pll_dmtd_locked
;
clk_ref_locked_o
<=
'1'
;
-- DMTD PLL
cmp_dmtd_clk_pll
:
PLL_BASE
...
...
@@ -824,7 +826,8 @@ begin -- architecture rtl
clk_62m5_dmtd_o
<=
clk_62m5_dmtd_i
;
clk_125m_ref_o
<=
clk_125m_ref_i
;
pll_locked_o
<=
clk_sys_locked_i
and
clk_dmtd_locked_i
;
pll_locked_o
<=
clk_sys_locked_i
and
clk_dmtd_locked_i
;
clk_ref_locked_o
<=
clk_ref_locked_i
;
ext_ref_mul_o
<=
clk_125m_ext_i
;
ext_ref_mul_locked_o
<=
clk_ext_locked_i
;
...
...
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