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White Rabbit core collection
Commit 3c2a6c72 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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move phy records to endpoint package and use them for WRPC

parent 65a8bda9
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Showing with 282 additions and 104 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 3c2a6c72
......@@ -72,6 +72,76 @@ package endpoint_pkg is
end record;
type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
-----------------------------
-- Phy i/f types
-----------------------------
-- 8-bit Serdes
type t_phy_8bits_to_wrc is record
ref_clk : std_logic;
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(7 downto 0);
rx_clk : std_logic;
rx_k : std_logic_vector(0 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(3 downto 0);
rdy : std_logic;
sfp_tx_fault : std_logic;
sfp_los : std_logic;
end record;
type t_phy_8bits_from_wrc is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(7 downto 0);
tx_k : std_logic_vector(0 downto 0);
loopen_vec : std_logic_vector(2 downto 0);
tx_prbs_sel : std_logic_vector(2 downto 0);
sfp_tx_disable : std_logic;
end record;
constant c_dummy_phy8_to_wrc : t_phy_8bits_to_wrc :=
('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0', (others=>'0'), '0',
'0', '0');
constant c_dummy_phy8_from_wrc : t_phy_8bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
-- 16-bit Serdes
type t_phy_16bits_to_wrc is record
ref_clk : std_logic;
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0);
rx_clk : std_logic;
rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
rdy : std_logic;
sfp_tx_fault : std_logic;
sfp_los : std_logic;
end record;
type t_phy_16bits_from_wrc is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0);
loopen_vec : std_logic_vector(2 downto 0);
tx_prbs_sel : std_logic_vector(2 downto 0);
sfp_tx_disable : std_logic;
end record;
constant c_dummy_phy16_to_wrc : t_phy_16bits_to_wrc :=
('0', '0', '0', (others=>'0'), '0', (others=>'0'), '0', (others=>'0'), '0',
'0', '0');
constant c_dummy_phy16_from_wrc : t_phy_16bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
-- debug CS types
type t_dbg_ep_rxpcs is record
fsm : std_logic_vector(2 downto 0);
......@@ -104,6 +174,7 @@ package endpoint_pkg is
g_address_granularity : t_wishbone_address_granularity := WORD;
g_simulation : boolean := false;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_tx_force_gap_length : integer := 0;
g_tx_runt_padding : boolean := false;
g_rx_buffer_size : integer := 1024;
......@@ -146,6 +217,10 @@ package endpoint_pkg is
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
gmii_tx_clk_i : in std_logic := '0';
gmii_txd_o : out std_logic_vector(7 downto 0);
gmii_tx_en_o : out std_logic;
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 3c2a6c72
......@@ -52,6 +52,7 @@ entity xwr_endpoint is
g_tx_force_gap_length : integer := 0;
g_tx_runt_padding : boolean := false;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_rx_buffer_size : integer := 1024;
g_with_rx_buffer : boolean := true;
g_with_flow_control : boolean := true;
......@@ -94,16 +95,17 @@ entity xwr_endpoint is
-- PHY Interace (8/16 bit PCS)
-------------------------------------------------------------------------------
phy_rst_o : out std_logic;
-- 1st option is to use std_logic based I/Os
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
phy_loopen_vec_o : out std_logic_vector(2 downto 0);
phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
phy_sfp_tx_fault_i : in std_logic;
phy_sfp_los_i : in std_logic;
phy_sfp_tx_disable_o : out std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -117,6 +119,12 @@ entity xwr_endpoint is
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
-- 2nd option is to use record-based I/Os
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc;
-------------------------------------------------------------------------------
-- GMII Interface (8-bit)
-------------------------------------------------------------------------------
......@@ -264,6 +272,28 @@ end xwr_endpoint;
architecture syn of xwr_endpoint is
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_enable : std_logic;
signal phy_syncen : std_logic;
signal phy_tx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_prbs_sel : std_logic_vector(2 downto 0);
signal sfp_tx_disable : std_logic;
signal phy_tx_clk : std_logic;
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_clk : std_logic;
signal phy_rx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bts : std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
signal phy_rdy : std_logic;
signal sfp_tx_fault : std_logic;
signal sfp_los : std_logic;
begin
U_Wrapped_Endpoint : wr_endpoint
......@@ -294,26 +324,30 @@ begin
rst_n_i => rst_n_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_valid_i => pps_valid_i,
phy_rst_o => phy_rst_o,
phy_loopen_o => phy_loopen_o,
phy_loopen_vec_o => phy_loopen_vec_o,
phy_tx_prbs_sel_o => phy_tx_prbs_sel_o,
phy_sfp_tx_fault_i => phy_sfp_tx_fault_i,
phy_sfp_los_i => phy_sfp_los_i,
phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
phy_enable_o => phy_enable_o,
phy_syncen_o => phy_syncen_o,
phy_rdy_i => phy_rdy_i,
phy_ref_clk_i => phy_ref_clk_i,
phy_tx_data_o => phy_tx_data_o,
phy_tx_k_o => phy_tx_k_o,
phy_tx_disparity_i => phy_tx_disparity_i,
phy_tx_enc_err_i => phy_tx_enc_err_i,
phy_rx_data_i => phy_rx_data_i,
phy_rx_clk_i => phy_rx_clk_i,
phy_rx_k_i => phy_rx_k_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_i,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
phy_tx_prbs_sel_o => phy_tx_prbs_sel,
phy_enable_o => phy_enable,
phy_syncen_o => phy_syncen,
phy_rdy_i => phy_rdy,
phy_sfp_tx_fault_i => sfp_tx_fault,
phy_sfp_los_i => sfp_los,
phy_sfp_tx_disable_o => sfp_tx_disable,
phy_ref_clk_i => phy_tx_clk,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_clk_i => phy_rx_clk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bts,
gmii_tx_clk_i => gmii_tx_clk_i,
gmii_txd_o => gmii_txd_o,
gmii_tx_en_o => gmii_tx_en_o,
......@@ -393,6 +427,81 @@ begin
wb_o.err <= '0';
wb_o.rty <= '0';
wb_o.int <= '0';
-- Record-based PHY connections, depending on 8/16-bit PCS
GEN_16BIT_IF: if g_pcs_16bit and g_records_for_phy generate
phy16_o.rst <= phy_rst;
phy16_o.loopen <= phy_loopen;
phy16_o.loopen_vec <= phy_loopen_vec;
phy16_o.enable <= phy_enable;
phy16_o.syncen <= phy_syncen;
phy16_o.tx_data <= phy_tx_data;
phy16_o.tx_k <= phy_tx_k;
phy16_o.tx_prbs_sel <= phy_tx_prbs_sel;
phy16_o.sfp_tx_disable <= sfp_tx_disable;
phy_tx_clk <= phy16_i.ref_clk;
phy_tx_disparity <= phy16_i.tx_disparity;
phy_tx_enc_err <= phy16_i.tx_enc_err;
phy_rx_data <= phy16_i.rx_data;
phy_rx_clk <= phy16_i.rx_clk;
phy_rx_k <= phy16_i.rx_k;
phy_rx_enc_err <= phy16_i.rx_enc_err;
phy_rx_bts <= phy16_i.rx_bitslide;
phy_rdy <= phy16_i.rdy;
sfp_tx_fault <= phy16_i.sfp_tx_fault;
sfp_los <= phy16_i.sfp_los;
end generate;
GEN_8BIT_IF: if not g_pcs_16bit and g_records_for_phy generate
phy8_o.rst <= phy_rst;
phy8_o.loopen <= phy_loopen;
phy8_o.loopen_vec <= phy_loopen_vec;
phy8_o.enable <= phy_enable;
phy8_o.syncen <= phy_syncen;
phy8_o.tx_data <= phy_tx_data;
phy8_o.tx_k <= phy_tx_k;
phy8_o.tx_prbs_sel <= phy_tx_prbs_sel;
phy8_o.sfp_tx_disable <= sfp_tx_disable;
phy_tx_clk <= phy8_i.ref_clk;
phy_tx_disparity <= phy8_i.tx_disparity;
phy_tx_enc_err <= phy8_i.tx_enc_err;
phy_rx_data <= phy8_i.rx_data;
phy_rx_clk <= phy8_i.rx_clk;
phy_rx_k <= phy8_i.rx_k;
phy_rx_enc_err <= phy8_i.rx_enc_err;
phy_rx_bts <= phy8_i.rx_bitslide;
phy_rdy <= phy8_i.rdy;
sfp_tx_fault <= phy8_i.sfp_tx_fault;
sfp_los <= phy8_i.sfp_los;
end generate;
-- backwards compatibility
GEN_STD_IF: if not g_records_for_phy generate
phy_rst_o <= phy_rst;
phy_loopen_o <= phy_loopen;
phy_loopen_vec_o <= phy_loopen_vec;
phy_enable_o <= phy_enable;
phy_syncen_o <= phy_syncen;
phy_tx_data_o <= phy_tx_data;
phy_tx_k_o <= phy_tx_k;
phy_tx_prbs_sel_o <= phy_tx_prbs_sel;
phy_sfp_tx_disable_o <= sfp_tx_disable;
phy_tx_clk <= phy_ref_clk_i;
phy_tx_disparity <= phy_tx_disparity_i;
phy_tx_enc_err <= phy_tx_enc_err_i;
phy_rx_data <= phy_rx_data_i;
phy_rx_clk <= phy_rx_clk_i;
phy_rx_k <= phy_rx_k_i;
phy_rx_enc_err <= phy_rx_enc_err_i;
phy_rx_bts <= phy_rx_bitslide_i;
phy_rdy <= phy_rdy_i;
sfp_tx_fault <= phy_sfp_tx_fault_i;
sfp_los <= phy_sfp_los_i;
end generate;
end syn;
......
modules/wrc_core/wr_core.vhd
View file @ 3c2a6c72
......@@ -98,6 +98,7 @@ entity wr_core is
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -165,6 +166,12 @@ entity wr_core is
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
-- PHY I/F record-based
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
-----------------------------------------
--GPIO
-----------------------------------------
......@@ -351,6 +358,7 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--Timing system
-----------------------------------------------------------------------------
signal phy_rx_clk : std_logic;
signal spll_wb_in : t_wishbone_slave_in;
signal spll_wb_out : t_wishbone_slave_out;
......@@ -540,6 +548,17 @@ begin
-----------------------------------------------------------------------------
-- Software PLL
-----------------------------------------------------------------------------
GEN_16BIT_PHY_IF: if g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy16_i.rx_clk;
end generate;
GEN_8BIT_PHY_IF: if not g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy8_i.rx_clk;
end generate;
GEN_STD_PHY_IF: if not g_records_for_phy generate
phy_rx_clk <= phy_rx_rbclk_i;
end generate;
U_SOFTPLL : xwr_softpll_ng
generic map(
......@@ -559,7 +578,7 @@ begin
rst_n_i => rst_net_n,
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i(0) => phy_rx_rbclk_i,
clk_ref_i(0) => phy_rx_clk,
-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
clk_fb_i => clk_fb,
-- DMTD Offset clock
......@@ -630,6 +649,7 @@ begin
g_simulation => f_int_to_bool(g_simulation),
g_tx_runt_padding => g_tx_runt_padding,
g_pcs_16bit => g_pcs_16bit,
g_records_for_phy => g_records_for_phy,
g_rx_buffer_size => g_rx_buffer_size,
g_with_rx_buffer => true,
g_with_flow_control => false,
......@@ -668,6 +688,11 @@ begin
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_i,
phy8_o => phy8_o,
phy8_i => phy8_i,
phy16_o => phy16_o,
phy16_i => phy16_i,
src_o => ep_src_out,
src_i => ep_src_in,
snk_o => ep_snk_out,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 3c2a6c72
......@@ -320,6 +320,7 @@ package wrcore_pkg is
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -341,7 +342,9 @@ package wrcore_pkg is
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-----------------------------------------
-- PHY I/f
-----------------------------------------
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
......@@ -360,6 +363,14 @@ package wrcore_pkg is
phy_sfp_tx_fault_i : in std_logic := '0';
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
-----------------------------------------
-- PHY I/f - record-based
-- selection done with g_records_for_phy
-----------------------------------------
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
led_act_o : out std_logic;
led_link_o : out std_logic;
......@@ -445,6 +456,7 @@ package wrcore_pkg is
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -488,7 +500,9 @@ package wrcore_pkg is
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-----------------------------------------
-- PHY I/f
-----------------------------------------
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -510,6 +524,14 @@ package wrcore_pkg is
phy_sfp_tx_fault_i : in std_logic := '0';
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
-----------------------------------------
-- PHY I/f - record-based
-- selection done with g_records_for_phy
-----------------------------------------
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
-----------------------------------------
--GPIO
......
modules/wrc_core/xwr_core.vhd
View file @ 3c2a6c72
......@@ -82,6 +82,7 @@ entity xwr_core is
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -125,7 +126,9 @@ entity xwr_core is
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-----------------------------------------
-- PHY I/f
-----------------------------------------
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
......@@ -147,6 +150,14 @@ entity xwr_core is
phy_sfp_tx_fault_i : in std_logic := '0';
phy_sfp_los_i : in std_logic := '0';
phy_sfp_tx_disable_o : out std_logic;
-----------------------------------------
-- PHY I/f - record-based
-- selection done with g_records_for_phy
-----------------------------------------
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
-----------------------------------------
--GPIO
......@@ -262,6 +273,7 @@ begin
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_vuart_fifo_size => g_vuart_fifo_size,
g_pcs_16bit => g_pcs_16bit,
g_records_for_phy => g_records_for_phy,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
......@@ -304,6 +316,11 @@ begin
phy_sfp_los_i => phy_sfp_los_i,
phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
phy8_o => phy8_o,
phy8_i => phy8_i,
phy16_o => phy16_o,
phy16_i => phy16_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
scl_o => scl_o,
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ 3c2a6c72
......@@ -6,6 +6,7 @@ use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
package wr_xilinx_pkg is
......@@ -38,66 +39,6 @@ package wr_xilinx_pkg is
pps : std_logic;
end record;
-- types for 8-bit Serdes
type t_phy_8bits_to_wrc is record
ref_clk : std_logic;
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(7 downto 0);
rx_clk : std_logic;
rx_k : std_logic_vector(0 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(3 downto 0);
rdy : std_logic;
sfp_tx_fault : std_logic;
sfp_los : std_logic;
end record;
type t_phy_8bits_from_wrc is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(7 downto 0);
tx_k : std_logic_vector(0 downto 0);
loopen_vec : std_logic_vector(2 downto 0);
tx_prbs_sel : std_logic_vector(2 downto 0);
sfp_tx_disable : std_logic;
end record;
constant c_dummy_phy8_from_wrc : t_phy_8bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
-- types for 16-bit Serdes
type t_phy_16bits_to_wrc is record
ref_clk : std_logic;
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0);
rx_clk : std_logic;
rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
rdy : std_logic;
sfp_tx_fault : std_logic;
sfp_los : std_logic;
end record;
type t_phy_16bits_from_wrc is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0);
loopen_vec : std_logic_vector(2 downto 0);
tx_prbs_sel : std_logic_vector(2 downto 0);
sfp_tx_disable : std_logic;
end record;
constant c_dummy_phy16_from_wrc : t_phy_16bits_from_wrc :=
('0', '0', '0', '0', (others=>'0'), (others=>'0'), (others=>'0'),
(others=>'0'), '0');
-------------------------------------------------------------------------------------------
component xwrc_platform_xilinx
generic
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ 3c2a6c72
......@@ -49,6 +49,7 @@ use work.wishbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wrcore_pkg.all;
use work.gencores_pkg.all;
use work.endpoint_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 3c2a6c72
......@@ -52,6 +52,9 @@ use work.gencores_pkg.all;
use work.wrcore_pkg.all;
-- Use the Xilinx White Rabbit platform-specific package (for xwrc_platform_xilinx)
use work.wr_xilinx_pkg.all;
-- Use the Endpoint package inside the WR PTP Core for definitions of
-- record-based PHY interfaces phy8_o, phy8_i
use work.endpoint_pkg.all;
---------------------------------------------------------------------------
-- Additional packages needed for other HDL modules in this design
......@@ -464,6 +467,7 @@ begin
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => true,
g_pcs_16bit => false,
g_records_for_phy => true,
g_dpram_initf => "wrc.ram",
g_aux_sdb => c_etherbone_sdb,
g_dpram_size => 131072/4,
......@@ -491,24 +495,8 @@ begin
dac_dpll_data_o => wrc_dacs_out.dpll_data,
-- PHY (SerDes) connections
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => wrc_phy_out.tx_data,
phy_tx_k_o => wrc_phy_out.tx_k,
phy_tx_disparity_i => wrc_phy_in.tx_disparity,
phy_tx_enc_err_i => wrc_phy_in.tx_enc_err,
phy_rx_data_i => wrc_phy_in.rx_data,
phy_rx_rbclk_i => wrc_phy_in.rx_clk,
phy_rx_k_i => wrc_phy_in.rx_k,
phy_rx_enc_err_i => wrc_phy_in.rx_enc_err,
phy_rx_bitslide_i => wrc_phy_in.rx_bitslide,
phy_rst_o => wrc_phy_out.rst,
phy_loopen_o => wrc_phy_out.loopen,
phy_loopen_vec_o => wrc_phy_out.loopen_vec,
phy_rdy_i => wrc_phy_in.rdy,
phy_tx_prbs_sel_o => wrc_phy_out.tx_prbs_sel,
phy_sfp_tx_fault_i => wrc_phy_in.sfp_tx_fault,
phy_sfp_los_i => wrc_phy_in.sfp_los,
phy_sfp_tx_disable_o => wrc_phy_out.sfp_tx_disable,
phy8_o => wrc_phy_out,
phy8_i => wrc_phy_in,
-- Timecode & 1-PPS interface
tm_dac_value_o => open,
......
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