wr_core_demo: added aux clock output to the top level module

3cda6a74 · Tomasz Wlostowski · 0b07fcd4 · 3cda6a74
Commit 3cda6a74 authored Oct 26, 2011 by Tomasz Wlostowski
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spec_top.vhd top/spec_1_1/wr_core_demo/spec_top.vhd +1 -0

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--- a/top/spec_1_1/wr_core_demo/spec_top.vhd
+++ b/top/spec_1_1/wr_core_demo/spec_top.vhd
@@ -235,6 +235,7 @@ architecture rtl of spec_top is
      clk_sys_i          : in  std_logic;
      clk_dmtd_i         : in  std_logic;
      clk_ref_i          : in  std_logic;
+      clk_aux_i : in std_logic := '0';
      rst_n_i            : in  std_logic;
      pps_p_o            : out std_logic;
      dac_hpll_load_p1_o : out std_logic;