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White Rabbit core collection
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3e7e52aa
Commit
3e7e52aa
authored
Oct 19, 2018
by
Tomasz Wlostowski
Committed by
Maciej Lipinski
May 13, 2019
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wr_streamers: hopefully fixed all bugs in fixed_latency_ts_match...
parent
05e9bce7
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Showing
2 changed files
with
84 additions
and
45 deletions
+84
-45
fixed_latency_delay.vhd
modules/wr_streamers/fixed_latency_delay.vhd
+1
-1
fixed_latency_ts_match.vhd
modules/wr_streamers/fixed_latency_ts_match.vhd
+83
-44
No files found.
modules/wr_streamers/fixed_latency_delay.vhd
View file @
3e7e52aa
...
...
@@ -214,7 +214,7 @@ begin
tm_tai_i
=>
tm_tai_i
,
tm_cycles_i
=>
tm_cycles_i
,
match_o
=>
delay_match
,
miss
_o
=>
delay_miss
);
late
_o
=>
delay_miss
);
p_fsm_comb
:
process
(
state
,
rx_dreq_i
,
fifo_empty
,
delay_miss
,
fifo_last
,
delay_match
,
fifo_target_ts_en
,
fifo_valid
)
begin
...
...
modules/wr_streamers/fixed_latency_ts_match.vhd
View file @
3e7e52aa
...
...
@@ -29,17 +29,26 @@ entity fixed_latency_ts_match is
match_o
:
out
std_logic
;
miss_o
:
out
std_logic
late_o
:
out
std_logic
);
end
entity
;
architecture
rtl
of
fixed_latency_ts_match
is
type
t_state
is
(
IDLE
,
WRAP_ADJ_TS
,
CHECK_LATE
,
WAIT_TRIG
);
impure
function
f_cycles_counter_range
return
integer
is
begin
if
g_simulation
=
1
then
if
g_clk_ref_rate
=
62500000
then
return
2
*
g_sim_cycle_counter_range
;
else
return
g_sim_cycle_counter_range
;
end
if
;
else
return
125000000
;
end
if
;
...
...
@@ -48,15 +57,17 @@ architecture rtl of fixed_latency_ts_match is
constant
c_rollover_threshold_lo
:
integer
:
=
f_cycles_counter_range
/
4
;
constant
c_rollover_threshold_hi
:
integer
:
=
f_cycles_counter_range
*
3
/
4
;
signal
ts_adjusted
:
unsigned
(
28
downto
0
);
signal
target_cycles
:
unsigned
(
28
downto
0
);
signal
arm_d
:
std_logic_vector
(
2
downto
0
);
signal
armed
:
std_logic
;
signal
tm_cycles_scaled
:
unsigned
(
28
downto
0
);
signal
ts_latency_scaled
:
unsigned
(
28
downto
0
);
signal
match
:
std_logic
;
signal
state
:
t_state
;
signal
ts_adj_next_cycle
,
roll_lo
,
roll_hi
:
std_logic
;
begin
process
(
tm_cycles_i
,
ts_latency_i
)
...
...
@@ -79,44 +90,72 @@ begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
armed
<=
'0'
;
arm_d
<=
(
others
=>
'0'
);
miss_o
<=
'0'
;
late_o
<=
'0'
;
match
<=
'0'
;
State
<=
IDLE
;
else
arm_d
<=
arm_d
(
1
downto
0
)
&
arm_i
;
case
State
is
when
IDLE
=>
match
<=
'0'
;
late_o
<=
'0'
;
armed
<=
'0'
;
if
arm_i
=
'1'
then
match_o
<=
'0'
;
miss_o
<=
'0'
;
ts_adjusted
<=
resize
(
unsigned
(
ts_origin_i
)
+
unsigned
(
ts_latency_i
),
29
);
State
<=
WRAP_ADJ_TS
;
armed
<=
'1'
;
end
if
;
if
ts_adjusted
<
c_rollover_threshold_lo
and
tm_cycles_scaled
>
c_rollover_threshold_hi
then
target_cycles
<=
tm_cycles_scaled
+
f_cycles_counter_range
;
if
arm_d
(
0
)
=
'1'
then
ts_adjusted
<=
ts_adjusted
+
f_cycles_counter_range
;
when
WRAP_ADJ_TS
=>
ts_adj_next_cycle
<=
'0'
;
roll_lo
<=
'0'
;
roll_hi
<=
'0'
;
if
ts_adjusted
>=
f_cycles_counter_range
then
ts_adj_next_cycle
<=
'1'
;
ts_adjusted
<=
ts_adjusted
-
f_cycles_counter_range
;
end
if
;
else
target_cycles
<=
tm_cycles_scaled
;
if
ts_adjusted
<
c_rollover_threshold_lo
then
roll_lo
<=
'1'
;
end
if
;
if
tm_cycles_scaled
>
c_rollover_threshold_hi
then
roll_hi
<=
'1'
;
end
if
;
if
(
arm_d
(
1
)
=
'1'
)
then
if
ts_adjusted
<
target_cycles
then
miss_o
<=
'1'
;
State
<=
CHECK_LATE
;
when
CHECK_LATE
=>
if
roll_lo
=
'1'
and
roll_hi
=
'1'
then
if
ts_adj_next_cycle
=
'0'
then
late_o
<=
'1'
;
State
<=
IDLE
;
else
armed
<=
'1'
;
State
<=
WAIT_TRIG
;
end
if
;
else
State
<=
WAIT_TRIG
;
end
if
;
if
armed
=
'1'
and
ts_adjusted
=
tm_cycles_scaled
then
match_o
<=
'1'
;
armed
<=
'0'
;
else
match_o
<=
'0'
;
when
WAIT_TRIG
=>
if
ts_adjusted
=
tm_cycles_scaled
then
match
<=
'1'
;
State
<=
IDLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
match_o
<=
match
;
end
rtl
;
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