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White Rabbit core collection
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4482c478
Commit
4482c478
authored
Oct 18, 2019
by
Tomasz Wlostowski
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board/svec7: initial version
parent
ad01cd09
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Showing
5 changed files
with
900 additions
and
2 deletions
+900
-2
Manifest.py
board/Manifest.py
+1
-1
Manifest.py
board/svec7/Manifest.py
+11
-0
wr_svec7_pkg.vhd
board/svec7/wr_svec7_pkg.vhd
+320
-0
xwrc_board_svec7.vhd
board/svec7/xwrc_board_svec7.vhd
+563
-0
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+5
-1
No files found.
board/Manifest.py
View file @
4482c478
try
:
if
board
in
[
"spec"
,
"svec"
,
"vfchd"
,
"common"
]:
if
board
in
[
"spec"
,
"svec"
,
"vfchd"
,
"common"
,
"svec7"
]:
modules
=
{
"local"
:
[
board
]
}
except
NameError
:
pass
board/svec7/Manifest.py
0 → 100644
View file @
4482c478
files
=
[
"wr_svec7_pkg.vhd"
,
"xwrc_board_svec7.vhd"
# "wrc_board_svec.vhd",
]
modules
=
{
"local"
:
[
"../common"
,
]
}
board/svec7/wr_svec7_pkg.vhd
0 → 100644
View file @
4482c478
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for SVEC package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_svec_pkg.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2019-09-25
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wrcore_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
streamers_pkg
.
all
;
package
wr_svec_pkg
is
component
xwrc_board_svec
is
generic
(
g_simulation
:
integer
:
=
0
;
g_verbose
:
boolean
:
=
TRUE
;
g_with_external_clock_input
:
boolean
:
=
TRUE
;
g_aux_clks
:
integer
:
=
0
;
g_fabric_iface
:
t_board_fabric_iface
:
=
plain
;
g_streamers_op_mode
:
t_streamers_op_mode
:
=
TX_AND_RX
;
g_tx_streamer_params
:
t_tx_streamer_params
:
=
c_tx_streamer_params_defaut
;
g_rx_streamer_params
:
t_rx_streamer_params
:
=
c_rx_streamer_params_defaut
;
g_dpram_initf
:
string
:
=
"default_xilinx"
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
g_aux_pll_cfg
:
t_auxpll_cfg_array
:
=
c_AUXPLL_CFG_ARRAY_DEFAULT
);
port
(
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_dmtd_125m_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
clk_pll_aux_o
:
out
std_logic_vector
(
3
downto
0
);
rst_pll_aux_n_o
:
out
std_logic_vector
(
3
downto
0
);
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
pll25dac_din_o
:
out
std_logic
;
pll25dac_sclk_o
:
out
std_logic
;
pll25dac_sync_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
:
=
'1'
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
:
=
'1'
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
aux_master_o
:
out
t_wishbone_master_out
;
aux_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_params
.
data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_svec
;
component
wrc_board_svec
is
generic
(
g_simulation
:
integer
:
=
0
;
g_verbose
:
integer
:
=
1
;
g_with_external_clock_input
:
integer
:
=
1
;
g_aux_clks
:
integer
:
=
0
;
g_fabric_iface
:
string
:
=
"plainfbrc"
;
g_streamers_op_mode
:
t_streamers_op_mode
:
=
TX_AND_RX
;
g_tx_streamer_params
:
t_tx_streamer_params
:
=
c_tx_streamer_params_defaut
;
g_rx_streamer_params
:
t_rx_streamer_params
:
=
c_rx_streamer_params_defaut
;
g_dpram_initf
:
string
:
=
"default_xilinx"
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
port
(
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_pllref_p_i
:
in
std_logic
;
clk_125m_pllref_n_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
pll25dac_din_o
:
out
std_logic
;
pll25dac_sclk_o
:
out
std_logic
;
pll25dac_sync_n_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_we_i
:
in
std_logic
:
=
'0'
;
wb_cyc_i
:
in
std_logic
:
=
'0'
;
wb_stb_i
:
in
std_logic
:
=
'0'
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
aux_master_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
aux_master_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
aux_master_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
aux_master_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
aux_master_we_o
:
out
std_logic
;
aux_master_cyc_o
:
out
std_logic
;
aux_master_stb_o
:
out
std_logic
;
aux_master_ack_i
:
in
std_logic
:
=
'0'
;
aux_master_err_i
:
in
std_logic
:
=
'0'
;
aux_master_rty_i
:
in
std_logic
:
=
'0'
;
aux_master_stall_i
:
in
std_logic
:
=
'0'
;
wrf_src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
wrf_src_cyc_o
:
out
std_logic
;
wrf_src_stb_o
:
out
std_logic
;
wrf_src_we_o
:
out
std_logic
;
wrf_src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
wrf_src_ack_i
:
in
std_logic
;
wrf_src_stall_i
:
in
std_logic
;
wrf_src_err_i
:
in
std_logic
;
wrf_src_rty_i
:
in
std_logic
;
wrf_snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
wrf_snk_cyc_i
:
in
std_logic
;
wrf_snk_stb_i
:
in
std_logic
;
wrf_snk_we_i
:
in
std_logic
;
wrf_snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
wrf_snk_ack_o
:
out
std_logic
;
wrf_snk_stall_o
:
out
std_logic
;
wrf_snk_err_o
:
out
std_logic
;
wrf_snk_rty_o
:
out
std_logic
;
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_params
.
data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_tx_cfg_mac_t_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"ffffffffffff"
;
wrs_tx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_mac_l_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_mac_r_i
:
in
std_logic_vector
(
47
downto
0
)
:
=
x"000000000000"
;
wrs_rx_cfg_etype_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"dbff"
;
wrs_rx_cfg_acc_b_i
:
in
std_logic
:
=
'1'
;
wrs_rx_cfg_flt_r_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_fix_l_i
:
in
std_logic_vector
(
27
downto
0
)
:
=
x"0000000"
;
wb_eth_adr_o
:
out
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
wb_eth_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_eth_dat_i
:
in
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wb_eth_sel_o
:
out
std_logic_vector
(
c_wishbone_address_width
/
8-1
downto
0
);
wb_eth_we_o
:
out
std_logic
;
wb_eth_cyc_o
:
out
std_logic
;
wb_eth_stb_o
:
out
std_logic
;
wb_eth_ack_i
:
in
std_logic
:
=
'0'
;
wb_eth_err_i
:
in
std_logic
:
=
'0'
;
wb_eth_rty_i
:
in
std_logic
:
=
'0'
;
wb_eth_stall_i
:
in
std_logic
:
=
'0'
;
aux_diag_i
:
in
std_logic_vector
(
g_diag_ro_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
aux_diag_o
:
out
std_logic_vector
(
g_diag_rw_vector_width
-
1
downto
0
)
:
=
(
others
=>
'0'
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tstamps_stb_o
:
out
std_logic
;
tstamps_tsval_o
:
out
std_logic_vector
(
31
downto
0
);
tstamps_port_id_o
:
out
std_logic_vector
(
5
downto
0
);
tstamps_frame_id_o
:
out
std_logic_vector
(
15
downto
0
);
tstamps_incorrect_o
:
out
std_logic
;
tstamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
wrc_board_svec
;
end
wr_svec_pkg
;
board/svec7/xwrc_board_svec7.vhd
0 → 100644
View file @
4482c478
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for SVEC7
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_svec7.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2019-10-17
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SVEC board.
-- http://www.ohwr.org/projects/svec/
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wrcore_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
streamers_pkg
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_svec_pkg
.
all
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
xwrc_board_svec7
is
generic
(
-- set to 1 to speed up some initialization processes during simulation
g_simulation
:
integer
:
=
0
;
-- set to false to reduce information messages during simulation
g_verbose
:
boolean
:
=
TRUE
;
-- Select whether to include external ref clock input
g_with_external_clock_input
:
boolean
:
=
TRUE
;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks
:
integer
:
=
0
;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface
:
t_board_fabric_iface
:
=
plain
;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode
:
t_streamers_op_mode
:
=
TX_AND_RX
;
g_tx_streamer_params
:
t_tx_streamer_params
:
=
c_tx_streamer_params_defaut
;
g_rx_streamer_params
:
t_rx_streamer_params
:
=
c_rx_streamer_params_defaut
;
-- memory initialisation file for embedded CPU
g_dpram_initf
:
string
:
=
"default_xilinx"
;
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
-- User-defined PLL_BASE outputs config
g_aux_pll_cfg
:
t_auxpll_cfg_array
:
=
c_AUXPLL_CFG_ARRAY_DEFAULT
);
port
(
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i
:
in
std_logic
;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
-- Clock inputs from the board
clk_20m_vcxo_i
:
in
std_logic
;
clk_62m5_pllref_p_i
:
in
std_logic
;
clk_62m5_pllref_n_i
:
in
std_logic
;
clk_125m_gtx_n_i
:
in
std_logic
;
clk_125m_gtx_p_i
:
in
std_logic
;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i
:
in
std_logic
:
=
'0'
;
-- 62.5MHz sys clock output
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
clk_ref_62m5_o
:
out
std_logic
;
-- 125.x MHz DDMTD clock
clk_dmtd_62m5_o
:
out
std_logic
;
-- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
clk_pll_aux_o
:
out
std_logic_vector
(
3
downto
0
);
-- active low reset outputs, synchronous to clk_pll_aux_o clocks
rst_pll_aux_n_o
:
out
std_logic_vector
(
3
downto
0
);
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_62m5_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
pll20dac_din_o
:
out
std_logic
;
pll20dac_sclk_o
:
out
std_logic
;
pll20dac_sync_n_o
:
out
std_logic
;
pll25dac_din_o
:
out
std_logic
;
pll25dac_sclk_o
:
out
std_logic
;
pll25dac_sync_n_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_i
:
in
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i
:
in
std_logic
;
onewire_oen_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- SPI (flash is connected to SFPGA and routed to AFPGA
-- once the boot process is complete)
---------------------------------------------------------------------------
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_slave_o
:
out
t_wishbone_slave_out
;
wb_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
aux_master_o
:
out
t_wishbone_master_out
;
aux_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
:
=
c_dummy_src_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_snk_i
:
in
t_wrf_sink_in
:
=
c_dummy_snk_in
;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i
:
in
std_logic_vector
(
g_tx_streamer_params
.
data_width
-1
downto
0
)
:
=
(
others
=>
'0'
);
wrs_tx_valid_i
:
in
std_logic
:
=
'0'
;
wrs_tx_dreq_o
:
out
std_logic
;
wrs_tx_last_i
:
in
std_logic
:
=
'1'
;
wrs_tx_flush_i
:
in
std_logic
:
=
'0'
;
wrs_tx_cfg_i
:
in
t_tx_streamer_cfg
:
=
c_tx_streamer_cfg_default
;
wrs_rx_first_o
:
out
std_logic
;
wrs_rx_last_o
:
out
std_logic
;
wrs_rx_data_o
:
out
std_logic_vector
(
g_rx_streamer_params
.
data_width
-1
downto
0
);
wrs_rx_valid_o
:
out
std_logic
;
wrs_rx_dreq_i
:
in
std_logic
:
=
'0'
;
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_master_o
:
out
t_wishbone_master_out
;
wb_eth_master_i
:
in
t_wishbone_master_in
:
=
cc_dummy_master_in
;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o
:
out
std_logic
;
tm_time_valid_o
:
out
std_logic
;
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o
:
out
std_logic
;
led_link_o
:
out
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
end
entity
xwrc_board_svec7
;
architecture
struct
of
xwrc_board_svec7
is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- IBUFDS
signal
clk_62m5_pllref_buf
:
std_logic
;
-- PLLs
signal
clk_pll_sys_62m5
:
std_logic
;
signal
clk_pll_ref_62m5
:
std_logic
;
signal
clk_pll_dmtd
:
std_logic
;
signal
pll_locked
:
std_logic
;
signal
clk_10m_ext
:
std_logic
;
signal
clk_pll_aux
:
std_logic_vector
(
3
downto
0
);
attribute
keep
:
string
;
attribute
keep
of
clk_pll_dmtd
:
signal
is
"TRUE"
;
-- Reset logic
signal
areset_edge_ppulse
:
std_logic
;
signal
rst_62m5_n
:
std_logic
;
signal
rstlogic_arst
:
std_logic
;
signal
rstlogic_clk_in
:
std_logic_vector
(
5
downto
0
);
signal
rstlogic_rst_out
:
std_logic_vector
(
5
downto
0
);
-- PLL DAC ARB
signal
dac_sync_n
:
std_logic_vector
(
1
downto
0
);
signal
dac_sclk
:
std_logic
;
signal
dac_din
:
std_logic
;
signal
dac_hpll_load_p1
:
std_logic
;
signal
dac_hpll_data
:
std_logic_vector
(
15
downto
0
);
signal
dac_dpll_load_p1
:
std_logic
;
signal
dac_dpll_data
:
std_logic_vector
(
15
downto
0
);
-- OneWire
signal
onewire_in
:
std_logic_vector
(
1
downto
0
);
signal
onewire_en
:
std_logic_vector
(
1
downto
0
);
-- PHY
signal
phy16_to_wrc
:
t_phy_16bits_to_wrc
;
signal
phy16_from_wrc
:
t_phy_16bits_from_wrc
;
-- External reference
signal
ext_ref_mul
:
std_logic
;
signal
ext_ref_mul_locked
:
std_logic
;
signal
ext_ref_mul_stopped
:
std_logic
;
signal
ext_ref_rst
:
std_logic
;
signal
clk_pll_62m5
:
std_logic
;
begin
-- architecture struct
-----------------------------------------------------------------------------
-- Platform-dependent part (PHY, PLLs, buffers, etc)
-----------------------------------------------------------------------------
cmp_ibufgds_pllref
:
IBUFGDS
generic
map
(
DIFF_TERM
=>
TRUE
,
IBUF_LOW_PWR
=>
TRUE
,
IOSTANDARD
=>
"DEFAULT"
)
port
map
(
O
=>
clk_62m5_pllref_buf
,
I
=>
clk_62m5_pllref_p_i
,
IB
=>
clk_62m5_pllref_n_i
);
cmp_xwrc_platform
:
entity
work
.
xwrc_platform_xilinx
generic
map
(
g_fpga_family
=>
"kintex7"
,
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_use_default_plls
=>
TRUE
,
g_aux_pll_cfg
=>
g_aux_pll_cfg
,
g_simulation
=>
g_simulation
)
port
map
(
areset_n_i
=>
areset_n_i
,
clk_10m_ext_i
=>
clk_10m_ext_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_62m5_pllref_i
=>
clk_62m5_pllref_buf
,
-- fixme : different clock
-- freq
clk_125m_gtp_p_i
=>
clk_125m_gtx_p_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtx_n_i
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_los_i
=>
sfp_los_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
clk_pll_aux_o
=>
clk_pll_aux
,
clk_62m5_sys_o
=>
clk_pll_sys_62m5
,
clk_62m5_ref_o
=>
clk_pll_ref_62m5
,
clk_62m5_dmtd_o
=>
clk_pll_dmtd
,
pll_locked_o
=>
pll_locked
,
clk_10m_ext_o
=>
clk_10m_ext
,
phy16_o
=>
phy16_to_wrc
,
phy16_i
=>
phy16_from_wrc
,
ext_ref_mul_o
=>
ext_ref_mul
,
ext_ref_mul_locked_o
=>
ext_ref_mul_locked
,
ext_ref_mul_stopped_o
=>
ext_ref_mul_stopped
,
ext_ref_rst_i
=>
ext_ref_rst
);
clk_sys_62m5_o
<=
clk_pll_sys_62m5
;
clk_ref_62m5_o
<=
clk_pll_ref_62m5
;
clk_pll_aux_o
<=
clk_pll_aux
;
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_pll_62m5
,
rst_n_i
=>
'1'
,
data_i
=>
areset_edge_n_i
,
ppulse_o
=>
areset_edge_ppulse
);
-- logic AND of all async reset sources (active high)
rstlogic_arst
<=
(
not
pll_locked
)
and
(
not
areset_n_i
)
and
areset_edge_ppulse
;
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in
(
0
)
<=
clk_pll_sys_62m5
;
rstlogic_clk_in
(
1
)
<=
clk_pll_ref_62m5
;
rstlogic_clk_in
(
5
downto
2
)
<=
clk_pll_aux
;
cmp_rstlogic_reset
:
gc_reset_multi_aasd
generic
map
(
g_CLOCKS
=>
6
,
-- 62.5MHz, 125MHz, + 4x pll_aux
g_RST_LEN
=>
16
)
-- 16 clock cycles
port
map
(
arst_i
=>
rstlogic_arst
,
clks_i
=>
rstlogic_clk_in
,
rst_n_o
=>
rstlogic_rst_out
);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n
<=
rstlogic_rst_out
(
0
);
rst_sys_62m5_n_o
<=
rst_62m5_n
;
rst_ref_62m5_n_o
<=
rstlogic_rst_out
(
1
);
rst_pll_aux_n_o
<=
rstlogic_rst_out
(
5
downto
2
);
-----------------------------------------------------------------------------
-- 2x SPI DAC
-----------------------------------------------------------------------------
cmp_dac_arb
:
spec_serial_dac_arb
generic
map
(
g_invert_sclk
=>
FALSE
,
g_num_extra_bits
=>
8
)
port
map
(
clk_i
=>
clk_pll_62m5
,
rst_n_i
=>
rst_62m5_n
,
val1_i
=>
dac_dpll_data
,
load1_i
=>
dac_dpll_load_p1
,
val2_i
=>
dac_hpll_data
,
load2_i
=>
dac_hpll_load_p1
,
dac_cs_n_o
=>
dac_sync_n
,
dac_sclk_o
=>
dac_sclk
,
dac_din_o
=>
dac_din
);
pll20dac_din_o
<=
dac_din
;
pll20dac_sclk_o
<=
dac_sclk
;
pll20dac_sync_n_o
<=
dac_sync_n
(
1
);
pll25dac_din_o
<=
dac_din
;
pll25dac_sclk_o
<=
dac_sclk
;
pll25dac_sync_n_o
<=
dac_sync_n
(
0
);
-----------------------------------------------------------------------------
-- The WR PTP core with optional fabric interface attached
-----------------------------------------------------------------------------
cmp_board_common
:
xwrc_board_common
generic
map
(
g_simulation
=>
g_simulation
,
g_verbose
=>
g_verbose
,
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_board_name
=>
"SVE7"
,
g_flash_secsz_kb
=>
256
,
-- default for M25P128
g_flash_sdbfs_baddr
=>
16
#
600000
#
,
-- default for M25P128
g_phys_uart
=>
TRUE
,
g_virtual_uart
=>
TRUE
,
g_aux_clks
=>
g_aux_clks
,
g_ep_rxbuf_size
=>
1024
,
g_tx_runt_padding
=>
TRUE
,
g_dpram_initf
=>
g_dpram_initf
,
g_dpram_size
=>
131072
/
4
,
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_aux_sdb
=>
c_wrc_periph3_sdb
,
g_softpll_enable_debugger
=>
FALSE
,
g_vuart_fifo_size
=>
1024
,
g_pcs_16bit
=>
TRUE
,
g_diag_id
=>
g_diag_id
,
g_diag_ver
=>
g_diag_ver
,
g_diag_ro_size
=>
g_diag_ro_size
,
g_diag_rw_size
=>
g_diag_rw_size
,
g_streamers_op_mode
=>
g_streamers_op_mode
,
g_tx_streamer_params
=>
g_tx_streamer_params
,
g_rx_streamer_params
=>
g_rx_streamer_params
,
g_fabric_iface
=>
g_fabric_iface
)
port
map
(
clk_sys_i
=>
clk_pll_sys_62m5
,
clk_dmtd_i
=>
clk_pll_dmtd
,
clk_ref_i
=>
clk_pll_ref_62m5
,
clk_aux_i
=>
clk_aux_i
,
clk_10m_ext_i
=>
clk_10m_ext
,
clk_ext_mul_i
=>
ext_ref_mul
,
clk_ext_mul_locked_i
=>
ext_ref_mul_locked
,
clk_ext_stopped_i
=>
ext_ref_mul_stopped
,
clk_ext_rst_o
=>
ext_ref_rst
,
pps_ext_i
=>
pps_ext_i
,
rst_n_i
=>
rst_62m5_n
,
dac_hpll_load_p1_o
=>
dac_hpll_load_p1
,
dac_hpll_data_o
=>
dac_hpll_data
,
dac_dpll_load_p1_o
=>
dac_dpll_load_p1
,
dac_dpll_data_o
=>
dac_dpll_data
,
phy16_o
=>
phy16_from_wrc
,
phy16_i
=>
phy16_to_wrc
,
scl_o
=>
eeprom_scl_o
,
scl_i
=>
eeprom_scl_i
,
sda_o
=>
eeprom_sda_o
,
sda_i
=>
eeprom_sda_i
,
sfp_scl_o
=>
sfp_scl_o
,
sfp_scl_i
=>
sfp_scl_i
,
sfp_sda_o
=>
sfp_sda_o
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_det_i
=>
sfp_det_i
,
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
owr_pwren_o
=>
open
,
owr_en_o
=>
onewire_en
,
owr_i
=>
onewire_in
,
wb_slave_i
=>
wb_slave_i
,
wb_slave_o
=>
wb_slave_o
,
aux_master_o
=>
aux_master_o
,
aux_master_i
=>
aux_master_i
,
wrf_src_o
=>
wrf_src_o
,
wrf_src_i
=>
wrf_src_i
,
wrf_snk_o
=>
wrf_snk_o
,
wrf_snk_i
=>
wrf_snk_i
,
wrs_tx_data_i
=>
wrs_tx_data_i
,
wrs_tx_valid_i
=>
wrs_tx_valid_i
,
wrs_tx_dreq_o
=>
wrs_tx_dreq_o
,
wrs_tx_last_i
=>
wrs_tx_last_i
,
wrs_tx_flush_i
=>
wrs_tx_flush_i
,
wrs_tx_cfg_i
=>
wrs_tx_cfg_i
,
wrs_rx_first_o
=>
wrs_rx_first_o
,
wrs_rx_last_o
=>
wrs_rx_last_o
,
wrs_rx_data_o
=>
wrs_rx_data_o
,
wrs_rx_valid_o
=>
wrs_rx_valid_o
,
wrs_rx_dreq_i
=>
wrs_rx_dreq_i
,
wrs_rx_cfg_i
=>
wrs_rx_cfg_i
,
wb_eth_master_o
=>
wb_eth_master_o
,
wb_eth_master_i
=>
wb_eth_master_i
,
aux_diag_i
=>
aux_diag_i
,
aux_diag_o
=>
aux_diag_o
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en_i
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked_o
,
timestamps_o
=>
timestamps_o
,
timestamps_ack_i
=>
timestamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_time_valid_o
=>
tm_time_valid_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
link_ok_o
=>
link_ok_o
);
sfp_rate_select_o
<=
'1'
;
onewire_oen_o
<=
onewire_en
(
0
);
onewire_in
(
0
)
<=
onewire_i
;
onewire_in
(
1
)
<=
'1'
;
clk_dmtd_62m5_o
<=
clk_pll_dmtd
;
end
architecture
struct
;
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
4482c478
...
...
@@ -93,8 +93,11 @@ entity xwrc_platform_xilinx is
clk_20m_vcxo_i
:
in
std_logic
:
=
'0'
;
-- 125.000 MHz PLL reference
clk_125m_pllref_i
:
in
std_logic
:
=
'0'
;
clk_62m5_pllref_i
:
in
std_logic
:
=
'0'
;
-- 124.992 MHz DMTD reference (CLBv3 reference design)
clk_125m_dmtd_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
---------------------------------------------------------------------------
...
...
@@ -151,6 +154,7 @@ entity xwrc_platform_xilinx is
-- PLL outputs
clk_62m5_sys_o
:
out
std_logic
;
clk_125m_ref_o
:
out
std_logic
;
clk_62m5_ref_o
:
out
std_logic
;
clk_20m_o
:
out
std_logic
;
clk_ref_locked_o
:
out
std_logic
;
clk_62m5_dmtd_o
:
out
std_logic
;
...
...
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