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White Rabbit core collection
Commit 471b2740 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_softpll: added wb slave adapter and xwb module

parent 79013c4e
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Showing with 184 additions and 44 deletions
modules/wr_softpll/wr_softpll.vhd
View file @ 471b2740
......@@ -3,11 +3,14 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wr_softpll is
generic(
g_deglitcher_threshold : integer;
g_tag_bits : integer
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
......@@ -16,7 +19,7 @@ entity wr_softpll is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i: in std_logic := '0';
clk_aux_i : in std_logic := '0';
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
......@@ -24,16 +27,17 @@ entity wr_softpll is
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
);
end wr_softpll;
......@@ -130,7 +134,7 @@ architecture rtl of wr_softpll is
signal per_hpll_p : std_logic;
signal tag_ref_p : std_logic;
signal tag_fb_p : std_logic;
signal tag_aux_p : std_logic;
signal tag_aux_p : std_logic;
signal rst_n_refclk : std_logic;
signal rst_n_dmtdclk : std_logic;
......@@ -141,12 +145,12 @@ architecture rtl of wr_softpll is
signal spll_per_hpll : std_logic_vector(31 downto 0);
signal spll_tag_ref : std_logic_vector(31 downto 0);
signal spll_tag_fb : std_logic_vector(31 downto 0);
signal spll_tag_aux : std_logic_vector(31 downto 0);
signal spll_tag_aux : std_logic_vector(31 downto 0);
signal tag_hpll_rd_period_ack : std_logic;
signal tag_ref_rd_ack : std_logic;
signal tag_fb_rd_ack : std_logic;
signal tag_aux_rd_ack : std_logic;
signal tag_aux_rd_ack : std_logic;
signal spll_csr_tag_en : std_logic_vector(3 downto 0);
signal spll_csr_tag_rdy : std_logic_vector(3 downto 0);
......@@ -170,9 +174,40 @@ architecture rtl of wr_softpll is
O : out std_logic;
I : in std_logic);
end component;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin -- rtl
resized_addr(5 downto 0) <= wb_addr_i;
resized_addr(c_wishbone_address_width-1 downto 4) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_data_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_data_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
sync_ffs_rst1 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -281,12 +316,12 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => clk_rx_buf,
tag_o => tag_ref,
tag_stb_p1_o => tag_ref_p,
shift_en_i => '0',
shift_dir_i => '0',
tag_o => tag_ref,
tag_stb_p1_o => tag_ref_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
dbg_dmtdout_o => open);
DMTD_AUX : dmtd_with_deglitcher
generic map (
......@@ -299,12 +334,12 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => clk_aux_i,
tag_o => tag_aux,
tag_stb_p1_o => tag_aux_p,
shift_en_i => '0',
shift_dir_i => '0',
tag_o => tag_aux,
tag_stb_p1_o => tag_aux_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
dbg_dmtdout_o => open);
DMTD_FB : dmtd_with_deglitcher
generic map (
......@@ -317,13 +352,13 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => clk_ref_buf,
tag_o => tag_fb,
tag_stb_p1_o => tag_fb_p,
shift_en_i => '0',
shift_dir_i => '0',
tag_o => tag_fb,
tag_stb_p1_o => tag_fb_p,
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
dbg_dmtdout_o => open);
end generate gen_with_single_dmtd;
--buf_rx_clk : BUFG
......@@ -338,8 +373,8 @@ begin -- rtl
clk_ref_buf <= clk_ref_i;
clk_rx_buf <= clk_rx_i;
clk_rx_buf <= clk_rx_i;
PERIOD_DET : hpll_period_detect
port map (
clk_ref_i => clk_rx_buf,
......@@ -358,14 +393,14 @@ begin -- rtl
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_addr_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_addr_i => wb_in.adr(3 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_irq_o => wb_irq_o,
spll_csr_tag_en_o => spll_csr_tag_en,
......@@ -374,8 +409,8 @@ begin -- rtl
tag_ref_rd_ack_o => tag_ref_rd_ack,
spll_tag_fb_i => spll_tag_fb,
tag_fb_rd_ack_o => tag_fb_rd_ack,
spll_tag_aux_i => spll_tag_aux,
tag_aux_rd_ack_o => tag_aux_rd_ack,
spll_tag_aux_i => spll_tag_aux,
tag_aux_rd_ack_o => tag_aux_rd_ack,
spll_per_hpll_i => spll_per_hpll,
tag_hpll_rd_period_o => tag_hpll_rd_period_ack,
......@@ -425,7 +460,7 @@ begin -- rtl
end if;
if(tag_aux_p = '1') then
spll_tag_aux <= std_logic_vector(to_unsigned(0, 32-g_tag_bits)) & tag_aux;
spll_tag_aux <= std_logic_vector(to_unsigned(0, 32-g_tag_bits)) & tag_aux;
spll_csr_tag_rdy(0) <= spll_csr_tag_en(0);
elsif(tag_aux_rd_ack = '1') then
spll_csr_tag_rdy(0) <= '0';
......
modules/wr_softpll/xwb_wr_softpll.vhd 0 → 100644
View file @ 471b2740
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xwb_wr_softpll is
generic(
g_deglitcher_threshold : integer;
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i : in std_logic := '0';
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
);
end wr_softpll;
architecture behavioral of xwb_wr_softpll is
component wr_softpll is
generic(
g_deglitcher_threshold : integer;
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
clk_aux_i : in std_logic := '0';
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0)
);
end component;
begin -- behavioral
WRAPPED_SOFTPLL : wr_softpll
generic map(
g_deglitcher_threshold => g_deglitcher_threshold,
g_tag_bits => g_tag_bits,
g_interface_mode => CLASSIC;
g_address_granularity => WORD
);
port(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
clk_ref_i => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_i,
clk_aux_i => clk_aux_i,
dac_hpll_data_o => dac_hpll_data_o,
dac_hpll_load_o => dac_hpll_load_o,
dac_dmpll_data_o => dac_dmpll_data_o,
dac_dmpll_load_o => dac_dmpll_load_o,
wb_addr_i => slave_i.adr(5 downto 0);
wb_data_i => slave_i.dat,
wb_data_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
wb_irq_o => wb_irq_o,
debug_o => debug_o
);
end behavioral;
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