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White Rabbit core collection
Commits
47bfe8f0
Commit
47bfe8f0
authored
Sep 25, 2013
by
Grzegorz Daniluk
Browse files
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Plain Diff
[spi-flash]: add gpio lines for binbanging SPI to access flash
parent
26ea7f84
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Showing
10 changed files
with
212 additions
and
6 deletions
+212
-6
wr_core.vhd
modules/wrc_core/wr_core.vhd
+6
-0
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+30
-0
wrc_syscon_pkg.vhd
modules/wrc_core/wrc_syscon_pkg.vhd
+22
-1
wrc_syscon_regs.h
modules/wrc_core/wrc_syscon_regs.h
+16
-1
wrc_syscon_wb.vhd
modules/wrc_core/wrc_syscon_wb.vhd
+55
-4
wrc_syscon_wb.wb
modules/wrc_core/wrc_syscon_wb.wb
+51
-0
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+9
-0
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+6
-0
spec_top.ucf
top/spec_1_1/wr_core_demo/spec_top.ucf
+8
-0
spec_top.vhd
top/spec_1_1/wr_core_demo/spec_top.vhd
+9
-0
No files found.
modules/wrc_core/wr_core.vhd
View file @
47bfe8f0
...
...
@@ -166,6 +166,9 @@ entity wr_core is
sfp_det_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
:
=
'0'
;
-----------------------------------------
--UART
...
...
@@ -757,6 +760,9 @@ begin
memsize_i
=>
"0000"
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
spi_sclk_o
=>
spi_sclk_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
slave_i
=>
periph_slave_i
,
slave_o
=>
periph_slave_o
,
...
...
modules/wrc_core/wrc_periph.vhd
View file @
47bfe8f0
...
...
@@ -60,6 +60,9 @@ entity wrc_periph is
memsize_i
:
in
std_logic_vector
(
3
downto
0
);
btn1_i
:
in
std_logic
;
btn2_i
:
in
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in_array
(
0
to
2
);
slave_o
:
out
t_wishbone_slave_out_array
(
0
to
2
);
...
...
@@ -238,6 +241,33 @@ begin
sysc_regs_i
.
gpsr_sfp_det_i
<=
sfp_det_i
;
-------------------------------------
-- SPI - Flash
-------------------------------------
p_drive_spi
:
process
(
clk_sys_i
)
begin
if
rst_n_i
=
'0'
then
spi_sclk_o
<=
'0'
;
spi_mosi_o
<=
'0'
;
else
if
(
sysc_regs_o
.
gpsr_spi_sclk_load_o
=
'1'
and
sysc_regs_o
.
gpsr_spi_sclk_o
=
'1'
)
then
spi_sclk_o
<=
'1'
;
elsif
(
sysc_regs_o
.
gpcr_spi_sclk_o
=
'1'
)
then
spi_sclk_o
<=
'0'
;
end
if
;
if
(
sysc_regs_o
.
gpsr_spi_mosi_load_o
=
'1'
and
sysc_regs_o
.
gpsr_spi_mosi_o
=
'1'
)
then
spi_mosi_o
<=
'1'
;
elsif
(
sysc_regs_o
.
gpcr_spi_mosi_o
=
'1'
)
then
spi_mosi_o
<=
'0'
;
end
if
;
end
if
;
end
process
;
sysc_regs_i
.
gpsr_spi_sclk_i
<=
'0'
;
sysc_regs_i
.
gpsr_spi_mosi_i
<=
'0'
;
sysc_regs_i
.
gpsr_spi_miso_i
<=
spi_miso_i
;
----------------------------------------
-- SYSCON
----------------------------------------
...
...
modules/wrc_core/wrc_syscon_pkg.vhd
View file @
47bfe8f0
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created :
Thu Feb 14 10:45:15
2013
-- Created :
Wed Sep 25 08:57:01
2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...
...
@@ -27,6 +27,9 @@ package sysc_wbgen2_pkg is
gpsr_sfp_det_i
:
std_logic
;
gpsr_sfp_scl_i
:
std_logic
;
gpsr_sfp_sda_i
:
std_logic
;
gpsr_spi_sclk_i
:
std_logic
;
gpsr_spi_mosi_i
:
std_logic
;
gpsr_spi_miso_i
:
std_logic
;
hwfr_memsize_i
:
std_logic_vector
(
3
downto
0
);
tcr_tdiv_i
:
std_logic_vector
(
11
downto
0
);
tvr_i
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -40,6 +43,9 @@ package sysc_wbgen2_pkg is
gpsr_sfp_det_i
=>
'0'
,
gpsr_sfp_scl_i
=>
'0'
,
gpsr_sfp_sda_i
=>
'0'
,
gpsr_spi_sclk_i
=>
'0'
,
gpsr_spi_mosi_i
=>
'0'
,
gpsr_spi_miso_i
=>
'0'
,
hwfr_memsize_i
=>
(
others
=>
'0'
),
tcr_tdiv_i
=>
(
others
=>
'0'
),
tvr_i
=>
(
others
=>
'0'
)
...
...
@@ -62,12 +68,18 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_load_o
:
std_logic
;
gpsr_sfp_sda_o
:
std_logic
;
gpsr_sfp_sda_load_o
:
std_logic
;
gpsr_spi_sclk_o
:
std_logic
;
gpsr_spi_sclk_load_o
:
std_logic
;
gpsr_spi_mosi_o
:
std_logic
;
gpsr_spi_mosi_load_o
:
std_logic
;
gpcr_led_stat_o
:
std_logic
;
gpcr_led_link_o
:
std_logic
;
gpcr_fmc_scl_o
:
std_logic
;
gpcr_fmc_sda_o
:
std_logic
;
gpcr_sfp_scl_o
:
std_logic
;
gpcr_sfp_sda_o
:
std_logic
;
gpcr_spi_sclk_o
:
std_logic
;
gpcr_spi_mosi_o
:
std_logic
;
tcr_enable_o
:
std_logic
;
end
record
;
...
...
@@ -86,12 +98,18 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_load_o
=>
'0'
,
gpsr_sfp_sda_o
=>
'0'
,
gpsr_sfp_sda_load_o
=>
'0'
,
gpsr_spi_sclk_o
=>
'0'
,
gpsr_spi_sclk_load_o
=>
'0'
,
gpsr_spi_mosi_o
=>
'0'
,
gpsr_spi_mosi_load_o
=>
'0'
,
gpcr_led_stat_o
=>
'0'
,
gpcr_led_link_o
=>
'0'
,
gpcr_fmc_scl_o
=>
'0'
,
gpcr_fmc_sda_o
=>
'0'
,
gpcr_sfp_scl_o
=>
'0'
,
gpcr_sfp_sda_o
=>
'0'
,
gpcr_spi_sclk_o
=>
'0'
,
gpcr_spi_mosi_o
=>
'0'
,
tcr_enable_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_sysc_in_registers
)
return
t_sysc_in_registers
;
...
...
@@ -130,6 +148,9 @@ tmp.gpsr_btn2_i := f_x_to_zero(left.gpsr_btn2_i) or f_x_to_zero(right.gpsr_btn2_
tmp
.
gpsr_sfp_det_i
:
=
f_x_to_zero
(
left
.
gpsr_sfp_det_i
)
or
f_x_to_zero
(
right
.
gpsr_sfp_det_i
);
tmp
.
gpsr_sfp_scl_i
:
=
f_x_to_zero
(
left
.
gpsr_sfp_scl_i
)
or
f_x_to_zero
(
right
.
gpsr_sfp_scl_i
);
tmp
.
gpsr_sfp_sda_i
:
=
f_x_to_zero
(
left
.
gpsr_sfp_sda_i
)
or
f_x_to_zero
(
right
.
gpsr_sfp_sda_i
);
tmp
.
gpsr_spi_sclk_i
:
=
f_x_to_zero
(
left
.
gpsr_spi_sclk_i
)
or
f_x_to_zero
(
right
.
gpsr_spi_sclk_i
);
tmp
.
gpsr_spi_mosi_i
:
=
f_x_to_zero
(
left
.
gpsr_spi_mosi_i
)
or
f_x_to_zero
(
right
.
gpsr_spi_mosi_i
);
tmp
.
gpsr_spi_miso_i
:
=
f_x_to_zero
(
left
.
gpsr_spi_miso_i
)
or
f_x_to_zero
(
right
.
gpsr_spi_miso_i
);
tmp
.
hwfr_memsize_i
:
=
f_x_to_zero
(
left
.
hwfr_memsize_i
)
or
f_x_to_zero
(
right
.
hwfr_memsize_i
);
tmp
.
tcr_tdiv_i
:
=
f_x_to_zero
(
left
.
tcr_tdiv_i
)
or
f_x_to_zero
(
right
.
tcr_tdiv_i
);
tmp
.
tvr_i
:
=
f_x_to_zero
(
left
.
tvr_i
)
or
f_x_to_zero
(
right
.
tvr_i
);
...
...
modules/wrc_core/wrc_syscon_regs.h
View file @
47bfe8f0
...
...
@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created :
Thu Feb 14 10:45:15
2013
* Created :
Wed Sep 25 08:57:01
2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...
...
@@ -74,6 +74,15 @@
/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MOSI WBGEN2_GEN_MASK(11, 1)
/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(12, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
...
...
@@ -94,6 +103,12 @@
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
...
...
modules/wrc_core/wrc_syscon_wb.vhd
View file @
47bfe8f0
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created :
Thu Feb 14 10:45:15
2013
-- Created :
Wed Sep 25 08:57:01
2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...
...
@@ -56,6 +56,10 @@ signal sysc_gpcr_sfp_scl_dly0 : std_logic ;
signal
sysc_gpcr_sfp_scl_int
:
std_logic
;
signal
sysc_gpcr_sfp_sda_dly0
:
std_logic
;
signal
sysc_gpcr_sfp_sda_int
:
std_logic
;
signal
sysc_gpcr_spi_sclk_dly0
:
std_logic
;
signal
sysc_gpcr_spi_sclk_int
:
std_logic
;
signal
sysc_gpcr_spi_mosi_dly0
:
std_logic
;
signal
sysc_gpcr_spi_mosi_int
:
std_logic
;
signal
sysc_tcr_enable_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -93,12 +97,16 @@ begin
sysc_gpsr_net_rst_int
<=
'0'
;
regs_o
.
gpsr_sfp_scl_load_o
<=
'0'
;
regs_o
.
gpsr_sfp_sda_load_o
<=
'0'
;
regs_o
.
gpsr_spi_sclk_load_o
<=
'0'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'0'
;
sysc_gpcr_led_stat_int
<=
'0'
;
sysc_gpcr_led_link_int
<=
'0'
;
sysc_gpcr_fmc_scl_int
<=
'0'
;
sysc_gpcr_fmc_sda_int
<=
'0'
;
sysc_gpcr_sfp_scl_int
<=
'0'
;
sysc_gpcr_sfp_sda_int
<=
'0'
;
sysc_gpcr_spi_sclk_int
<=
'0'
;
sysc_gpcr_spi_mosi_int
<=
'0'
;
sysc_tcr_enable_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
...
...
@@ -114,12 +122,16 @@ begin
sysc_gpsr_net_rst_int
<=
'0'
;
regs_o
.
gpsr_sfp_scl_load_o
<=
'0'
;
regs_o
.
gpsr_sfp_sda_load_o
<=
'0'
;
regs_o
.
gpsr_spi_sclk_load_o
<=
'0'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'0'
;
sysc_gpcr_led_stat_int
<=
'0'
;
sysc_gpcr_led_link_int
<=
'0'
;
sysc_gpcr_fmc_scl_int
<=
'0'
;
sysc_gpcr_fmc_sda_int
<=
'0'
;
sysc_gpcr_sfp_scl_int
<=
'0'
;
sysc_gpcr_sfp_sda_int
<=
'0'
;
sysc_gpcr_spi_sclk_int
<=
'0'
;
sysc_gpcr_spi_mosi_int
<=
'0'
;
ack_in_progress
<=
'0'
;
else
regs_o
.
rstr_trig_wr_o
<=
'0'
;
...
...
@@ -127,6 +139,8 @@ begin
regs_o
.
gpsr_fmc_sda_load_o
<=
'0'
;
regs_o
.
gpsr_sfp_scl_load_o
<=
'0'
;
regs_o
.
gpsr_sfp_sda_load_o
<=
'0'
;
regs_o
.
gpsr_spi_sclk_load_o
<=
'0'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
...
...
@@ -179,6 +193,8 @@ begin
sysc_gpsr_net_rst_int
<=
wrdata_reg
(
4
);
regs_o
.
gpsr_sfp_scl_load_o
<=
'1'
;
regs_o
.
gpsr_sfp_sda_load_o
<=
'1'
;
regs_o
.
gpsr_spi_sclk_load_o
<=
'1'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
1
)
<=
'0'
;
...
...
@@ -190,9 +206,9 @@ begin
rddata_reg
(
7
)
<=
regs_i
.
gpsr_sfp_det_i
;
rddata_reg
(
8
)
<=
regs_i
.
gpsr_sfp_scl_i
;
rddata_reg
(
9
)
<=
regs_i
.
gpsr_sfp_sda_i
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
10
)
<=
regs_i
.
gpsr_spi_sclk_i
;
rddata_reg
(
11
)
<=
regs_i
.
gpsr_spi_mosi_i
;
rddata_reg
(
12
)
<=
regs_i
.
gpsr_spi_miso_i
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
...
...
@@ -222,6 +238,8 @@ begin
sysc_gpcr_fmc_sda_int
<=
wrdata_reg
(
3
);
sysc_gpcr_sfp_scl_int
<=
wrdata_reg
(
8
);
sysc_gpcr_sfp_sda_int
<=
wrdata_reg
(
9
);
sysc_gpcr_spi_sclk_int
<=
wrdata_reg
(
10
);
sysc_gpcr_spi_mosi_int
<=
wrdata_reg
(
11
);
end
if
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
1
)
<=
'0'
;
...
...
@@ -229,6 +247,8 @@ begin
rddata_reg
(
3
)
<=
'0'
;
rddata_reg
(
8
)
<=
'0'
;
rddata_reg
(
9
)
<=
'0'
;
rddata_reg
(
10
)
<=
'0'
;
rddata_reg
(
11
)
<=
'0'
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
...
...
@@ -398,6 +418,11 @@ begin
regs_o
.
gpsr_sfp_scl_o
<=
wrdata_reg
(
8
);
-- SFP I2C bitbanged SDA
regs_o
.
gpsr_sfp_sda_o
<=
wrdata_reg
(
9
);
-- SPI bitbanged SCLK
regs_o
.
gpsr_spi_sclk_o
<=
wrdata_reg
(
10
);
-- SPI bitbanged MOSI
regs_o
.
gpsr_spi_mosi_o
<=
wrdata_reg
(
11
);
-- SPI bitbanged MISO
-- Status LED
process
(
clk_sys_i
,
rst_n_i
)
begin
...
...
@@ -476,6 +501,32 @@ begin
end
process
;
-- SPI bitbanged SCLK
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
sysc_gpcr_spi_sclk_dly0
<=
'0'
;
regs_o
.
gpcr_spi_sclk_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
sysc_gpcr_spi_sclk_dly0
<=
sysc_gpcr_spi_sclk_int
;
regs_o
.
gpcr_spi_sclk_o
<=
sysc_gpcr_spi_sclk_int
and
(
not
sysc_gpcr_spi_sclk_dly0
);
end
if
;
end
process
;
-- SPI bitbanged MOSI
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
sysc_gpcr_spi_mosi_dly0
<=
'0'
;
regs_o
.
gpcr_spi_mosi_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
sysc_gpcr_spi_mosi_dly0
<=
sysc_gpcr_spi_mosi_int
;
regs_o
.
gpcr_spi_mosi_o
<=
sysc_gpcr_spi_mosi_int
and
(
not
sysc_gpcr_spi_mosi_dly0
);
end
if
;
end
process
;
-- Memory size
-- Timer Divider
-- Timer Enable
...
...
modules/wrc_core/wrc_syscon_wb.wb
View file @
47bfe8f0
...
...
@@ -127,6 +127,41 @@ peripheral {
load = LOAD_EXT;
align = 9;
};
field {
name = "SPI bitbanged SCLK";
prefix = "spi_sclk";
description = "write 1: drive SPI clk to 1\
read: always 0";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 10;
};
field {
name = "SPI bitbanged MOSI";
prefix = "spi_mosi";
description = "write 1: drive SPI MOSI line to 1\
read: always 0";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 11;
};
field {
name = "SPI bitbanged MISO";
prefix = "spi_miso";
description = "read: current state of SPI MISO line";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
align = 12;
};
};
...
...
@@ -180,6 +215,22 @@ peripheral {
align = 9;
};
field {
name = "SPI bitbanged SCLK";
prefix = "spi_sclk";
description = "write 1: Set SPI clk line to 0.";
type = MONOSTABLE;
align = 10;
};
field {
name = "SPI bitbanged MOSI";
prefix = "spi_mosi";
description = "write 1: Set SPI MOSI line to 0.";
type = MONOSTABLE;
align = 11;
};
};
reg {
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
47bfe8f0
...
...
@@ -215,6 +215,9 @@ package wrcore_pkg is
memsize_i
:
in
std_logic_vector
(
3
downto
0
);
btn1_i
:
in
std_logic
;
btn2_i
:
in
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in_array
(
0
to
2
);
slave_o
:
out
t_wishbone_slave_out_array
(
0
to
2
);
uart_rxd_i
:
in
std_logic
;
...
...
@@ -345,6 +348,9 @@ package wrcore_pkg is
sfp_det_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'H'
;
btn2_i
:
in
std_logic
:
=
'H'
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
:
=
'0'
;
uart_rxd_i
:
in
std_logic
:
=
'H'
;
uart_txd_o
:
out
std_logic
;
...
...
@@ -473,6 +479,9 @@ package wrcore_pkg is
sfp_det_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
:
=
'0'
;
-----------------------------------------
--UART
...
...
modules/wrc_core/xwr_core.vhd
View file @
47bfe8f0
...
...
@@ -150,6 +150,9 @@ entity xwr_core is
sfp_det_i
:
in
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
:
=
'0'
;
-----------------------------------------
--UART
...
...
@@ -273,6 +276,9 @@ begin
sfp_det_i
=>
sfp_det_i
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
spi_sclk_o
=>
spi_sclk_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
...
...
top/spec_1_1/wr_core_demo/spec_top.ucf
View file @
47bfe8f0
...
...
@@ -83,6 +83,14 @@ NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "SPI_NCS_O" LOC = AA3;
NET "SPI_NCS_O" IOSTANDARD = "LVCMOS25";
NET "SPI_SCLK_O" LOC = Y20;
NET "SPI_SCLK_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MOSI_O" LOC = AB20;
NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS25";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
...
...
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @
47bfe8f0
...
...
@@ -86,6 +86,11 @@ entity spec_top is
button1_i
:
in
std_logic
:
=
'H'
;
button2_i
:
in
std_logic
:
=
'H'
;
spi_ncs_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
:
=
'L'
;
thermo_id
:
inout
std_logic
;
-- 1-Wire interface to DS18B20
...
...
@@ -699,6 +704,9 @@ begin
sfp_det_i
=>
sfp_mod_def0_b
,
btn1_i
=>
button1_i
,
btn2_i
=>
button2_i
,
spi_sclk_o
=>
spi_sclk_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
...
...
@@ -896,6 +904,7 @@ begin
dio_sdn_n_o
<=
'1'
;
sfp_tx_disable_o
<=
'0'
;
spi_ncs_o
<=
'0'
;
end
rtl
;
...
...
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